forked from tonioni/WinUAE
-
Notifications
You must be signed in to change notification settings - Fork 1
/
akiko.cpp
2325 lines (2094 loc) · 60 KB
/
akiko.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* UAE - The Un*x Amiga Emulator
*
* CD32 Akiko emulation
*
* - C2P
* - NVRAM
* - CDROM
*
* Copyright 2001-2016 Toni Wilen
*
*/
#define EEPROM_DEBUG 0
/*
B80000-B80003: $C0CACAFE (Read-only identifier)
B80004.L: INTREQ (RO)
B80008.L: INTENA (R/W)
31 $80000000 = Subcode interrupt (One subcode buffer filled and B0018.B has changed)
30 $40000000 = Drive has received all command bytes and executed the command (PIO only)
29 $20000000 = Drive has status data pending (PIO only)
28 $10000000 = Drive command DMA transmit complete (DMA only)
27 $08000000 = Drive status DMA receive complete (DMA only)
26 $04000000 = Drive data DMA complete
25 $02000000 = DMA overflow (lost data)?
INTREQ is read-only, each interrupt bit has different clearing method (see below).
B80010.L: DMA data base address (R/W. Must be 64k aligned)
B80014.L: Command/Status/Subcode DMA base. (R/W. Must be 1024 byte aligned)
Base + 0x000: 256 byte circular command DMA buffer. (Memory to drive)
Base + 0x100: Subcode DMA buffer (Doublebuffered, 2x128 byte buffers)
Base + 0x200: 256 byte circular status DMA buffer. (Drive to memory)
B00018.B READ = Subcode DMA offset (ROM only checks if non-zero: second buffer in use)
B00018.B WRITE = Clear subcode interrupt (bit 31)
B0001D.B READ = Transmit DMA circular buffer current position.
B0001D.B WRITE = Transmit DMA circular buffer end position.
If written value is different than current: transmit DMA starts and sends command bytes to drive until value matches end position.
Clears also transmit interrupt (bit 28)
B0001E.B READ = Receive DMA circular buffer current position.
B0001F.B WRITE = Receive DMA circular buffer end position.
If written value is different than current: receive DMA fills DMA buffer if drive has response data remaining, until value matches end position.
Clears also Receive interrupt (bit 27)
B80020.W WRITE = DMA transfer block enable
Each bit marks position in DMA data address.
Bit 0 = DMA base address + 0
Bit 1 = DMA base address + 0x1000
..
Bit 14 = DMA base address + 0xe000
Bit 15 = DMA base address + 0xf000
When writing, if bit is one, matching register bit gets set, if bit is zero, nothing happens, it is not possible to clear already set bits.
All one bit blocks (CD sectors) are transferred one by one. Bit 15 is always checked and processed first, then 14 and so on..
Interrupt is generated after each transferred block and matching register bit is cleared.
Writing to this register also clears INTREQ bit 26. Writing zero will only clear interrupt.
If CONFIG data transfer DMA enable is not active: register gets cleared and writes are ignored.
Structure of each block:
0-2: zeroed
3: low 5 bits of sector number
4 to 2352: 2348 bytes raw sector data (with first 4 bytes skipped)
0xc00: 146 bytes of CD error correction data?
The rest is unused(?).
B80020.W READ = Read current DMA transfer status.
B80024.L: CONFIG (R/W)
31 $80000000 = Subcode DMA enable
30 $40000000 = Command write (to CD) DMA enable
29 $20000000 = Status read (from CD) DMA enable
28 $10000000 = Memory access mode?
27 $08000000 = Data transfer DMA enable
26 $04000000 = CD interface enable?
25 $02000000 = CD data mode?
24 $01000000 = CD data mode?
23 $00800000 = Akiko internal CIA faked vsync rate (0=50Hz,1=60Hz)
00-22 = unused
B80028.B WRITE = PIO write (If CONFIG bit 30 off). Clears also interrupt bit 30.
B80028.B READ = PIO read (If CONFIG bit 29 off). Clears also interrupt bit 29 if no data available anymore.
B80030.B NVRAM I2C IO. Bit 7 = SCL, bit 6 = SDA
B80032.B NVRAM I2C DIRECTION. Bit 7 = SCL direction, bit 6 = SDA direction)
B80038.L C2P
Commands:
1 = STOP
Size: 1 byte
Returns status response
2 = PAUSE
Size: 1 byte
Returns status response
3 = UNPAUSE
Size: 1 byte
Returns status response
4 = PLAY/READ
Size: 12 bytes
Response: 2 bytes
5 = LED (2 bytes)
Size: 2 bytes. Bit 7 set in second byte = response wanted.
Response: no response or 2 bytes. Second byte non-zero: led is currently lit.
6 = SUBCODE
Size: 1 byte
Response: 15 bytes
7 = INFO
Size: 1 byte
Response: 20 bytes (status and firmware version)
Common status response: 2 bytes
Status second byte bit 7 = Error, bit 3 = Playing, bit 0 = Door closed.
First byte of command is combined 4 bit counter and command code.
Command response's first byte is same as command.
Counter byte can be used to match command with response.
Command and response bytes have checksum byte appended.
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "memory.h"
#include "events.h"
#include "savestate.h"
#include "blkdev.h"
#include "zfile.h"
#include "threaddep/thread.h"
#include "akiko.h"
#include "gui.h"
#include "crc32.h"
#include "uae.h"
#include "custom.h"
#include "newcpu.h"
#include "flashrom.h"
#include "debug.h"
#include "rommgr.h"
#include "devices.h"
#define AKIKO_DEBUG_IO 1
#define AKIKO_DEBUG_IO_CMD 1
#define AKIKO_DEBUG_IRQ 0
int log_cd32 = 0;
// 43 48 49 4E 4F 4E 20 20 4F 2D 36 35 38 2D 32 20 32 34
#define FIRMWAREVERSION "CHINON O-658-2 24"
static void irq (void)
{
safe_interrupt_set(IRQ_SOURCE_CD32CDTV, 0, false);
}
/*
* CD32 1Kb NVRAM (EEPROM) emulation
*
* NVRAM chip is 24C08 CMOS EEPROM (1024x8 bits = 1Kb)
* Chip interface is I2C (2 wire serial)
* Akiko addresses used:
* 0xb80030: bit 7 = SCL (clock), 6 = SDA (data)
* 0xb80032: 0xb80030 data direction register (0 = input, 1 = output)
*
*/
static uae_u8 *cd32_nvram;
static int cd32_nvram_size;
static void *cd32_eeprom;
static uae_u8 cd32_i2c_direction;
static bool cd32_i2c_data_scl, cd32_i2c_data_sda;
struct zfile *cd32_flashfile;
extern uae_u8 *cubo_nvram;
static void nvram_read (void)
{
cubo_nvram = NULL;
zfile_fclose(cd32_flashfile);
cd32_flashfile = NULL;
eeprom_free(cd32_eeprom);
cd32_eeprom = NULL;
cd32_i2c_data_scl = cd32_i2c_data_sda = true;
cd32_i2c_direction = 0;
if (!currprefs.cs_cd32nvram)
return;
int maxlen = currprefs.cs_cd32nvram_size;
if (is_board_enabled(&currprefs, ROMTYPE_CUBO, 0))
maxlen += 2048 + 16;
if (!cd32_nvram || cd32_nvram_size != maxlen) {
xfree(cd32_nvram);
cd32_nvram = xmalloc(uae_u8, maxlen);
}
memset(cd32_nvram, 0, maxlen);
if (is_board_enabled(&currprefs, ROMTYPE_CUBO, 0)) {
cubo_nvram = cd32_nvram + currprefs.cs_cd32nvram_size;
}
TCHAR path[MAX_DPATH];
cfgfile_resolve_path_out_load(currprefs.flashfile, path, MAX_DPATH, PATH_ROM);
cd32_flashfile = zfile_fopen (path, _T("rb+"), ZFD_NORMAL);
if (!cd32_flashfile)
cd32_flashfile = zfile_fopen (path, _T("wb"), 0);
if (cd32_flashfile) {
size_t size = zfile_fread(cd32_nvram, 1, currprefs.cs_cd32nvram_size, cd32_flashfile);
if (size == currprefs.cs_cd32nvram_size && maxlen > currprefs.cs_cd32nvram_size)
size += zfile_fread(cubo_nvram, 1, maxlen - currprefs.cs_cd32nvram_size, cd32_flashfile);
if (size < maxlen)
zfile_fwrite(cd32_nvram + size, 1, maxlen - size, cd32_flashfile);
}
cd32_eeprom = eeprom_new(cd32_nvram, currprefs.cs_cd32nvram_size, cd32_flashfile);
}
static void akiko_nvram_write (int offset, uae_u32 v)
{
switch (offset)
{
case 0:
{
#if EEPROM_DEBUG
uae_u8 o = (cd32_i2c_data_scl ? 0x80 : 0x00) | (cd32_i2c_data_sda ? 0x40 : 0x00);
#endif
if (cd32_i2c_direction & 0x80)
cd32_i2c_data_scl = (v & 0x80) != 0;
else
cd32_i2c_data_scl = true;
eeprom_i2c_set(cd32_eeprom, BITBANG_I2C_SCL, cd32_i2c_data_scl);
if (cd32_i2c_direction & 0x40)
cd32_i2c_data_sda = (v & 0x40) != 0;
else
cd32_i2c_data_sda = true;
eeprom_i2c_set(cd32_eeprom, BITBANG_I2C_SDA, cd32_i2c_data_sda);
#if EEPROM_DEBUG
uae_u8 n = (cd32_i2c_data_scl ? 0x80 : 0x00) | (cd32_i2c_data_sda ? 0x40 : 0x00);
write_log(_T("Data write: %02x->%02x (%02x)\n"), o, v, n);
#endif
break;
}
case 2:
{
#if EEPROM_DEBUG
if (cd32_i2c_direction != v) {
write_log(_T("Direction write: %02x->%02x\n"), cd32_i2c_direction, v);
}
#endif
cd32_i2c_direction = v;
break;
}
}
}
static uae_u32 akiko_nvram_read (int offset)
{
uae_u32 v = 0;
switch (offset)
{
case 0:
v |= eeprom_i2c_set(cd32_eeprom, BITBANG_I2C_SCL, cd32_i2c_data_scl) ? 0x80 : 0x00;
v |= eeprom_i2c_set(cd32_eeprom, BITBANG_I2C_SDA, cd32_i2c_data_sda) ? 0x40 : 0x00;
#if EEPROM_DEBUG
write_log(_T("Data read: %02x\n"), v);
#endif
break;
case 2:
v = cd32_i2c_direction;
#if EEPROM_DEBUG
write_log(_T("Direction read: %02x\n"), v);
#endif
break;
}
return v;
}
/* CD32 Chunky to Planar hardware emulation
* Akiko addresses used:
* 0xb80038-0xb8003b
*/
static uae_u32 akiko_buffer[8];
static int akiko_read_offset, akiko_write_offset;
static uae_u32 akiko_result[8];
#if 0
static void akiko_c2p_do (void)
{
int i;
for (i = 0; i < 8; i++)
akiko_result[i] = 0;
/* FIXME: better c2p algoritm than this piece of crap.... */
for (i = 0; i < 8 * 32; i++) {
if (akiko_buffer[7 - (i >> 5)] & (1 << (i & 31)))
akiko_result[i & 7] |= 1 << (i >> 3);
}
}
#else
/* Optimised Chunky-to-Planar algorithm by Mequa */
static uae_u32 akiko_precalc_shift[32];
static uae_u32 akiko_precalc_bytenum[32][8];
static void akiko_c2p_precalculate(void)
{
uae_u32 i, j;
for (i = 0; i < 32; i++) {
akiko_precalc_shift[i] = 1 << i;
for (j = 0; j < 8; j++) {
akiko_precalc_bytenum[i][j] = (i >> 3) + ((7 - j) << 2);
}
}
}
static void akiko_c2p_do(void)
{
int i;
for (i = 0; i < 8; i++) {
akiko_result[i] = (((akiko_buffer[0] & akiko_precalc_shift[i]) != 0) << (akiko_precalc_bytenum[i][0]) )
| (((akiko_buffer[1] & akiko_precalc_shift[i]) != 0) << (akiko_precalc_bytenum[i][1]) )
| (((akiko_buffer[2] & akiko_precalc_shift[i]) != 0) << (akiko_precalc_bytenum[i][2]) )
| (((akiko_buffer[3] & akiko_precalc_shift[i]) != 0) << (akiko_precalc_bytenum[i][3]) )
| (((akiko_buffer[4] & akiko_precalc_shift[i]) != 0) << (akiko_precalc_bytenum[i][4]) )
| (((akiko_buffer[5] & akiko_precalc_shift[i]) != 0) << (akiko_precalc_bytenum[i][5]) )
| (((akiko_buffer[6] & akiko_precalc_shift[i]) != 0) << (akiko_precalc_bytenum[i][6]) )
| (((akiko_buffer[7] & akiko_precalc_shift[i]) != 0) << (akiko_precalc_bytenum[i][7]) )
| (((akiko_buffer[0] & akiko_precalc_shift[i+8]) != 0) << (akiko_precalc_bytenum[i+8][0]) )
| (((akiko_buffer[1] & akiko_precalc_shift[i+8]) != 0) << (akiko_precalc_bytenum[i+8][1]) )
| (((akiko_buffer[2] & akiko_precalc_shift[i+8]) != 0) << (akiko_precalc_bytenum[i+8][2]) )
| (((akiko_buffer[3] & akiko_precalc_shift[i+8]) != 0) << (akiko_precalc_bytenum[i+8][3]) )
| (((akiko_buffer[4] & akiko_precalc_shift[i+8]) != 0) << (akiko_precalc_bytenum[i+8][4]) )
| (((akiko_buffer[5] & akiko_precalc_shift[i+8]) != 0) << (akiko_precalc_bytenum[i+8][5]) )
| (((akiko_buffer[6] & akiko_precalc_shift[i+8]) != 0) << (akiko_precalc_bytenum[i+8][6]) )
| (((akiko_buffer[7] & akiko_precalc_shift[i+8]) != 0) << (akiko_precalc_bytenum[i+8][7]) )
| (((akiko_buffer[0] & akiko_precalc_shift[i+16]) != 0) << (akiko_precalc_bytenum[i+16][0]))
| (((akiko_buffer[1] & akiko_precalc_shift[i+16]) != 0) << (akiko_precalc_bytenum[i+16][1]))
| (((akiko_buffer[2] & akiko_precalc_shift[i+16]) != 0) << (akiko_precalc_bytenum[i+16][2]))
| (((akiko_buffer[3] & akiko_precalc_shift[i+16]) != 0) << (akiko_precalc_bytenum[i+16][3]))
| (((akiko_buffer[4] & akiko_precalc_shift[i+16]) != 0) << (akiko_precalc_bytenum[i+16][4]))
| (((akiko_buffer[5] & akiko_precalc_shift[i+16]) != 0) << (akiko_precalc_bytenum[i+16][5]))
| (((akiko_buffer[6] & akiko_precalc_shift[i+16]) != 0) << (akiko_precalc_bytenum[i+16][6]))
| (((akiko_buffer[7] & akiko_precalc_shift[i+16]) != 0) << (akiko_precalc_bytenum[i+16][7]))
| (((akiko_buffer[0] & akiko_precalc_shift[i+24]) != 0) << (akiko_precalc_bytenum[i+24][0]))
| (((akiko_buffer[1] & akiko_precalc_shift[i+24]) != 0) << (akiko_precalc_bytenum[i+24][1]))
| (((akiko_buffer[2] & akiko_precalc_shift[i+24]) != 0) << (akiko_precalc_bytenum[i+24][2]))
| (((akiko_buffer[3] & akiko_precalc_shift[i+24]) != 0) << (akiko_precalc_bytenum[i+24][3]))
| (((akiko_buffer[4] & akiko_precalc_shift[i+24]) != 0) << (akiko_precalc_bytenum[i+24][4]))
| (((akiko_buffer[5] & akiko_precalc_shift[i+24]) != 0) << (akiko_precalc_bytenum[i+24][5]))
| (((akiko_buffer[6] & akiko_precalc_shift[i+24]) != 0) << (akiko_precalc_bytenum[i+24][6]))
| (((akiko_buffer[7] & akiko_precalc_shift[i+24]) != 0) << (akiko_precalc_bytenum[i+24][7]));
}
}
#endif
static void akiko_c2p_write(int offset, uae_u32 v)
{
if (offset == 3)
akiko_buffer[akiko_write_offset] = 0;
akiko_buffer[akiko_write_offset] |= v << ( 8 * (3 - offset));
if (offset == 0) {
akiko_write_offset++;
akiko_write_offset &= 7;
}
akiko_read_offset = -1;
}
static uae_u32 akiko_c2p_read(int offset)
{
uae_u32 v;
if (akiko_read_offset < 0) {
akiko_c2p_do();
akiko_read_offset = 0;
}
akiko_write_offset = 0;
v = akiko_result[akiko_read_offset];
return v >> (8 * (3 - offset));
}
/* CD32 CDROM hardware emulation
* Akiko addresses used:
* 0xb80004-0xb80028
*/
#define CDINTERRUPT_SUBCODE 0x80000000
#define CDINTERRUPT_DRIVEXMIT 0x40000000 /* not used by ROM. PIO mode. */
#define CDINTERRUPT_DRIVERECV 0x20000000 /* not used by ROM. PIO mode. */
#define CDINTERRUPT_RXDMADONE 0x10000000
#define CDINTERRUPT_TXDMADONE 0x08000000
#define CDINTERRUPT_PBX 0x04000000
#define CDINTERRUPT_OVERFLOW 0x02000000
#define CDFLAG_SUBCODE 0x80000000 // 31
#define CDFLAG_TXD 0x40000000 // 30
#define CDFLAG_RXD 0x20000000 // 29
#define CDFLAG_CAS 0x10000000 // 28
#define CDFLAG_PBX 0x08000000 // 27
#define CDFLAG_ENABLE 0x04000000 // 26
#define CDFLAG_RAW 0x02000000 // 25
#define CDFLAG_MSB 0x01000000 // 24
#define CDFLAG_NTSC 0x00800000 // 23
#define CDS_ERROR 0x80
#define CDS_PLAYING 0x08
#define CDS_PLAYEND 0x00
#define CH_ERR_BADCOMMAND 0x80 // %10000000
#define CH_ERR_CHECKSUM 0x88 // %10001000
#define CH_ERR_DRAWERSTUCK 0x90 // %10010000
#define CH_ERR_DISKUNREADABLE 0x98 // %10011000
#define CH_ERR_INVALIDADDRESS 0xa0 // %10100000
#define CH_ERR_WRONGDATA 0xa8 // %10101000
#define CH_ERR_FOCUSERROR 0xc8 // %11001000
#define CH_ERR_SPINDLEERROR 0xd0 // %11010000
#define CH_ERR_TRACKINGERROR 0xd8 // %11011000
#define CH_ERR_SLEDERROR 0xe0 // %11100000
#define CH_ERR_TRACKJUMP 0xe8 // %11101000
#define CH_ERR_ABNORMALSEEK 0xf0 // %11110000
#define CH_ERR_NODISK 0xf8 // %11111000
static int subcodecounter;
#define MAX_SUBCODEBUFFER 36
static volatile int subcodebufferoffset, subcodebufferoffsetw;
static uae_u8 subcodebufferinuse[MAX_SUBCODEBUFFER];
static uae_u8 subcodebuffer[MAX_SUBCODEBUFFER * SUB_CHANNEL_SIZE];
static uae_u32 cdrom_intreq, cdrom_intena;
static uae_u8 cdrom_subcodeoffset;
static uae_u32 cdrom_addressdata, cdrom_addressmisc;
static uae_u32 subcode_address, cdrx_address, cdtx_address;
static uae_u32 cdrom_flags;
static uae_u32 cdrom_pbx;
static uae_u8 cdcomtxinx; /* 0x19 */
static uae_u8 cdcomrxinx; /* 0x1a */
static uae_u8 cdcomtxcmp; /* 0x1d */
static uae_u8 cdcomrxcmp; /* 0x1f */
static uae_u8 cdrom_result_buffer[32];
static uae_u8 cdrom_command_buffer[32];
static uae_u8 cdrom_command;
static uae_u8 cdrom_last_rx;
static int cdrom_toc_counter;
static uae_u32 cdrom_toc_crc;
static uae_u8 cdrom_toc_buffer[MAX_TOC_ENTRIES * 13];
static struct cd_toc_head cdrom_toc_cd_buffer;
static uae_u8 qcode_buf[SUBQ_SIZE];
static int qcode_valid;
static int cdrom_disk, cdrom_paused, cdrom_playing, cdrom_audiostatus;
static int cdrom_command_active;
static int cdrom_command_length;
static int cdrom_checksum_error, cdrom_unknown_command;
static int cdrom_data_offset, cdrom_speed, cdrom_sector_counter;
static int cdrom_current_sector, cdrom_seek_delay;
static int cdrom_audiotimeout;
static int cdrom_led;
static int cdrom_receive_length, cdrom_receive_offset;
static int cdrom_muted;
static int cd_initialized;
static int cdrom_tx_dma_delay, cdrom_rx_dma_delay;
static uae_u8 *sector_buffer_1, *sector_buffer_2;
static int sector_buffer_sector_1, sector_buffer_sector_2;
#define SECTOR_BUFFER_SIZE 64
static uae_u8 *sector_buffer_info_1, *sector_buffer_info_2;
static int unitnum = -1;
static uae_u8 cdrom_door = 1;
static bool akiko_inited;
static volatile int mediachanged, mediacheckcounter;
static volatile int frame2counter;
static smp_comm_pipe requests;
static volatile int akiko_thread_running;
static uae_sem_t akiko_sem, sub_sem, cda_sem;
static void checkint (void)
{
if (cdrom_intreq & cdrom_intena) {
irq ();
#if AKIKO_DEBUG_IRQ
write_log(_T("CD32: Akiko INT %08x\n"), cdrom_intreq & cdrom_intena);
#endif
#if AKIKO_DEBUG_IO
if (log_cd32 > 1)
write_log(_T("CD32: Akiko INT %08x\n"), cdrom_intreq & cdrom_intena);
#endif
}
}
static void set_status (uae_u32 status)
{
#if AKIKO_DEBUG_IO
if (log_cd32 > 1) {
if (!(cdrom_intreq & status))
write_log (_T("CD32: Akiko IRQ %08x | %08x = %08x\n"), status, cdrom_intreq, cdrom_intreq | status);
}
#endif
cdrom_intreq |= status;
checkint ();
cdrom_led ^= LED_CD_ACTIVE2;
}
static void rethink_akiko(void)
{
checkint ();
}
static void cdaudiostop_do (void)
{
qcode_valid = 0;
if (unitnum < 0)
return;
sys_command_cd_pause (unitnum, 0);
sys_command_cd_stop (unitnum);
}
static void cdaudiostop (void)
{
cdrom_audiostatus = 0;
cdrom_audiotimeout = 0;
cdrom_paused = 0;
cdrom_playing = 0;
write_comm_pipe_u32 (&requests, 0x0104, 1);
}
static void subfunc (uae_u8 *data, int cnt)
{
if (!(cdrom_flags & CDFLAG_SUBCODE))
return;
uae_sem_wait (&sub_sem);
#if 0
int total = 0;
for (int i = 0; i < MAX_SUBCODEBUFFER; i++) {
if (subcodebufferinuse[i])
total++;
}
write_log (_T("%d "), total);
#endif
if (subcodebufferinuse[subcodebufferoffsetw]) {
memset (subcodebufferinuse, 0,sizeof (subcodebufferinuse));
subcodebufferoffsetw = subcodebufferoffset = 0;
uae_sem_post (&sub_sem);
//write_log (_T("CD32: subcode buffer overflow 1\n"));
return;
}
int offset = subcodebufferoffsetw;
while (cnt > 0) {
if (subcodebufferinuse[offset]) {
write_log (_T("CD32: subcode buffer overflow 2\n"));
break;
}
subcodebufferinuse[offset] = 1;
memcpy (&subcodebuffer[offset * SUB_CHANNEL_SIZE], data, SUB_CHANNEL_SIZE);
data += SUB_CHANNEL_SIZE;
offset++;
if (offset >= MAX_SUBCODEBUFFER)
offset = 0;
cnt--;
}
subcodebufferoffsetw = offset;
uae_sem_post (&sub_sem);
}
static int statusfunc(int status, int playpos)
{
if (status == -1)
return 0;
if (status == -2)
return 10;
if (status < 0)
return 0;
if (cdrom_audiostatus != status) {
if (status == AUDIO_STATUS_IN_PROGRESS) {
if (cdrom_playing == 0)
cdrom_playing = 1;
cdrom_audiotimeout = 1;
}
if (cdrom_playing && status != AUDIO_STATUS_IN_PROGRESS && status != AUDIO_STATUS_PAUSED && status != AUDIO_STATUS_NOT_SUPPORTED) {
cdrom_audiotimeout = -1;
}
}
cdrom_audiostatus = status;
return 0;
}
static int statusfunc_imm(int status, int playpos)
{
if (status == -3 || status > AUDIO_STATUS_IN_PROGRESS)
uae_sem_post(&cda_sem);
if (status < 0)
return 0;
return statusfunc(status, playpos);
}
static void cdaudioplay_do(bool immediate)
{
uae_u32 startlsn = read_comm_pipe_u32_blocking(&requests);
uae_u32 endlsn = read_comm_pipe_u32_blocking(&requests);
uae_u32 scan = read_comm_pipe_u32_blocking(&requests);
qcode_valid = 0;
if (unitnum < 0)
return;
sys_command_cd_pause(unitnum, 0);
sys_command_cd_play(unitnum, startlsn, endlsn, scan, immediate ? statusfunc_imm : statusfunc, subfunc);
}
static bool isaudiotrack (int startlsn)
{
struct cd_toc *s = NULL;
uae_u32 addr;
int i;
if (!cdrom_toc_cd_buffer.points)
return false;
for (i = 0; i < cdrom_toc_cd_buffer.points; i++) {
s = &cdrom_toc_cd_buffer.toc[i];
addr = s->paddress;
if (s->track > 0 && s->track < 100 && addr >= startlsn)
break;
s++;
}
if (s && (s->control & 0x0c) == 0x04) {
write_log (_T("CD32: tried to play data track %d!\n"), s->track);
return false;
}
return true;
}
static struct cd_toc *get_track (int startlsn)
{
for (int i = cdrom_toc_cd_buffer.first_track_offset + 1; i <= cdrom_toc_cd_buffer.last_track_offset + 1; i++) {
struct cd_toc *s = &cdrom_toc_cd_buffer.toc[i];
uae_u32 addr = s->paddress;
if (startlsn < addr)
return s - 1;
}
return NULL;
}
static int last_play_end;
static int cd_play_audio (int startlsn, int endlsn, int scan)
{
struct cd_toc *s = NULL;
if (!cdrom_toc_cd_buffer.points)
return 0;
s = get_track (startlsn);
if (s && (s->control & 0x0c) == 0x04) {
s = get_track (startlsn + 150);
if (s && (s->control & 0x0c) == 0x04) {
write_log (_T("CD32: tried to play data track %d!\n"), s->track);
s++;
startlsn = s->paddress;
s++;
endlsn = s->paddress;
}
startlsn = s->paddress;
}
qcode_valid = 0;
last_play_end = endlsn;
cdrom_audiotimeout = 10;
cdrom_paused = 0;
write_comm_pipe_u32 (&requests, 0x0110, 0);
write_comm_pipe_u32 (&requests, startlsn, 0);
write_comm_pipe_u32 (&requests, endlsn, 0);
write_comm_pipe_u32 (&requests, scan, 1);
return 1;
}
/* read qcode */
static int last_play_pos;
static int cd_qcode (uae_u8 *d)
{
uae_u8 *buf, *s, as;
if (d)
memset (d, 0, 11);
last_play_pos = 0;
buf = qcode_buf;
as = buf[1];
buf[2] = 0x80;
if (!qcode_valid)
return 0;
if (cdrom_audiostatus != AUDIO_STATUS_IN_PROGRESS && cdrom_audiostatus != AUDIO_STATUS_PAUSED)
return 0;
s = buf + 4;
last_play_pos = msf2lsn (fromlongbcd (s + 7));
if (!d)
return 0;
buf[2] = 0;
/* ??? */
d[0] = 0;
/* CtlAdr */
d[1] = s[0];
/* Track */
d[2] = s[1];
/* Index */
d[3] = s[2];
/* TrackPos */
d[4] = s[3];
d[5] = s[4];
d[6] = s[5];
/* DiskPos */
d[7] = 0;
d[8] = s[7];
d[9] = s[8];
d[10] = s[9];
if (as == AUDIO_STATUS_IN_PROGRESS) {
/* Make sure end of disc position is not missed.
*/
if (last_play_pos >= cdrom_toc_cd_buffer.lastaddress || cdrom_toc_cd_buffer.lastaddress - last_play_pos < 10) {
int msf = lsn2msf (cdrom_toc_cd_buffer.lastaddress);
d[8] = tobcd ((uae_u8)(msf >> 16));
d[9] = tobcd ((uae_u8)(msf >> 8));
d[10] = tobcd ((uae_u8)(msf >> 0));
}
}
// write_log (_T("%02X.%02X.%02X.%02X.%02X.%02X.%02X.%02X.%02X.%02X.%02X.%02X\n"),
// d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], d[8], d[9], d[10], d[11]);
return 0;
}
/* read toc */
static int get_cdrom_toc (void)
{
int j;
int datatrack = 0, secondtrack = 0;
cdrom_toc_counter = -1;
if (!sys_command_cd_toc (unitnum, &cdrom_toc_cd_buffer))
return 1;
memset (cdrom_toc_buffer, 0, MAX_TOC_ENTRIES * 13);
for (j = 0; j < cdrom_toc_cd_buffer.points; j++) {
struct cd_toc *s = &cdrom_toc_cd_buffer.toc[j];
uae_u8 *d = &cdrom_toc_buffer[j * 13];
int addr = s->paddress;
int msf = lsn2msf (addr);
if (s->point == 0xa0 || s->point == 0xa1)
msf = s->track << 16;
d[1] = (s->adr << 0) | (s->control << 4);
d[3] = s->point < 100 ? tobcd (s->point) : s->point;
d[8] = tobcd ((msf >> 16) & 0xff);
d[9] = tobcd ((msf >> 8) & 0xff);
d[10] = tobcd ((msf >> 0) & 0xff);
if (s->point == 1 && (s->control & 0x0c) == 0x04)
datatrack = 1;
if (s->point >= 2 && s->point < 100 && (s->control & 0x0c) != 0x04 && !secondtrack)
secondtrack = addr;
}
cdrom_toc_crc = get_crc32 (cdrom_toc_buffer, cdrom_toc_cd_buffer.points * 13);
return 0;
}
static bool is_valid_data_sector(int sector)
{
for (int i = 0; i < cdrom_toc_cd_buffer.points; i++) {
struct cd_toc *s = &cdrom_toc_cd_buffer.toc[i];
if (s->point < 1 || s->point > 99)
continue;
if ((s->control & 0x0c) != 4)
continue;
if (sector >= s->paddress && (sector < s[1].paddress || s[1].point >= 0xa1))
return true;
}
return false;
}
/* open device */
static int sys_cddev_open (void)
{
struct device_info di = { 0 };
unitnum = get_standard_cd_unit (CD_STANDARD_UNIT_CD32);
sys_command_info (unitnum, &di, 0);
write_log (_T("CD32: using drive %s (unit %d, media %d)\n"), di.label, unitnum, di.media_inserted);
/* make sure CD audio is not playing */
cdaudiostop_do ();
return 0;
}
/* close device */
static void sys_cddev_close (void)
{
if (unitnum >= 0) {
cdaudiostop_do ();
sys_command_close (unitnum);
}
unitnum = -1;
}
static bool cdrom_can_return_data(void)
{
if (cdrom_receive_length > 0)
return false;
return true;
}
static int cdrom_start_return_data (int len)
{
if (!cdrom_can_return_data())
return 0;
if (len <= 0)
return -1;
cdrom_receive_length = len;
uae_u8 checksum = 0xff;
for (int i = 0; i < cdrom_receive_length; i++) {
checksum -= cdrom_result_buffer[i];
}
cdrom_result_buffer[cdrom_receive_length++] = checksum;
#if AKIKO_DEBUG_IO_CMD
if (log_cd32 > 0) {
write_log(_T("CD32: OUT "));
for (int i = 0; i < cdrom_receive_length; i++) {
write_log(_T("%02X "), cdrom_result_buffer[i]);
}
write_log(_T("\n"));
}
#endif
cdrom_receive_offset = 0;
set_status(CDINTERRUPT_DRIVERECV);
return 1;
}
/*
RX DMA channel writes bytes to memory if DMA enabled, cdcomrxinx != cdcomrxcmp
and there is data available from CDROM firmware code.
Triggers CDINTERRUPT_RXDMADONE and stops transfer (even if there is
more data available) when cdcomrxinx matches cdcomrxcmp
*/
static void cdrom_return_data (void)
{
uae_u32 cmd_buf = cdrx_address;
if (!cdrom_receive_length)
return;
if (!(cdrom_flags & CDFLAG_RXD))
return;
if (cdcomrxinx == cdcomrxcmp)
return;
if (cdrom_rx_dma_delay > 0)
return;
#if AKIKO_DEBUG_IO_CMD
if (log_cd32 > 0)
write_log (_T("CD32: OUT IDX=0x%02X-0x%02X LEN=%d,%08x:"), cdcomrxinx, cdcomrxcmp, cdrom_receive_length, cmd_buf + cdcomrxinx);
#endif
while (cdrom_receive_offset < cdrom_receive_length) {
cdrom_last_rx = cdrom_result_buffer[cdrom_receive_offset];
put_byte (cmd_buf + cdcomrxinx, cdrom_last_rx);
cdcomrxinx++;
cdrom_receive_offset++;
if (cdcomrxinx == cdcomrxcmp) {
set_status(CDINTERRUPT_RXDMADONE);
#if AKIKO_DEBUG_IO
if (log_cd32 > 1)
write_log(_T("CD32: RXDMADONE %d/%d\n"), cdrom_receive_offset, cdrom_receive_length);
#endif
break;
}
}
if (cdrom_receive_offset == cdrom_receive_length) {
cdrom_receive_length = 0;
cdrom_receive_offset = 0;
cdrom_intreq &= ~CDINTERRUPT_DRIVERECV;
set_status(CDINTERRUPT_DRIVEXMIT);
}
}
static int cdrom_command_led (void)
{
int v = cdrom_command_buffer[1];
int old = cdrom_led;
cdrom_led &= ~LED_CD_ACTIVE;
cdrom_led |= (v & 1) ? LED_CD_ACTIVE : 0;
#if AKIKO_DEBUG_IO_CMD
if (log_cd32 > 0)
write_log(_T("CD32: LED=%d\n"), v & 1);
#endif
if (cdrom_led != old)
gui_flicker_led (LED_CD, 0, cdrom_led);
if (v & 0x80) { // result wanted?
cdrom_result_buffer[0] = cdrom_command;
cdrom_result_buffer[1] = (cdrom_led & LED_CD_ACTIVE) ? 1 : 0;
return 2;
}
return 0;
}
static int cdrom_command_idle_status (void)
{
cdrom_result_buffer[0] = 0x0a;
cdrom_result_buffer[1] = 0x70;
return 2;
}
static int cdrom_command_media_status (void)
{
cdrom_result_buffer[0] = 0x0a;
cdrom_result_buffer[1] = sys_command_ismedia (unitnum, 0) > 0 ? 0x01: 0x00;
return 2;
}
/* check if cd drive door is open or closed, return firmware info */
static int cdrom_command_status (void)
{
#if AKIKO_DEBUG_IO_CMD
if (log_cd32 > 0)
write_log(_T("CD32: INFO\n"));
#endif
cdrom_result_buffer[1] = cdrom_door;
if (unitnum >= 0)
get_cdrom_toc ();
/* firmware info */
memcpy (cdrom_result_buffer + 2, FIRMWAREVERSION, sizeof FIRMWAREVERSION);
cdrom_result_buffer[0] = cdrom_command;
cd_initialized = 2;
return 20;
}
/* return one TOC entry, each TOC entry repeats 3 times */
#define TOC_REPEAT 3
static int cdrom_return_toc_entry (void)
{
cdrom_result_buffer[0] = 6;
#if AKIKO_DEBUG_IO_CMD
if (log_cd32 > 0)
write_log (_T("CD32: TOC entry %d/%d\n"), cdrom_toc_counter / TOC_REPEAT, cdrom_toc_cd_buffer.points);
#endif
if (cdrom_toc_cd_buffer.points == 0) {
cdrom_result_buffer[1] = CDS_ERROR | cdrom_door;
return 15;
}
cdrom_result_buffer[1] = 0x0a; // unknown but real CD32 sets it
memcpy (cdrom_result_buffer + 2, cdrom_toc_buffer + (cdrom_toc_counter / TOC_REPEAT) * 13, 13);
cdrom_result_buffer[6] = tobcd(99);
cdrom_result_buffer[7] = tobcd(24 + cdrom_toc_counter / 75);
cdrom_result_buffer[8] = tobcd(cdrom_toc_counter % 75);
cdrom_toc_counter++;
if (cdrom_toc_counter / TOC_REPEAT >= cdrom_toc_cd_buffer.points)
cdrom_toc_counter = -1;
return 15;
}
static int checkerr (void)
{
if (!cdrom_disk) {
cdrom_result_buffer[1] = CH_ERR_NODISK | cdrom_door;
return 1;
}
return 0;
}
static int cdrom_command_stop (void)
{
#if AKIKO_DEBUG_IO_CMD
if (log_cd32 > 0)
write_log(_T("CD32: STOP: %d\n"), cdrom_playing);
#endif
cdrom_audiotimeout = 0;
cdrom_result_buffer[0] = cdrom_command;
if (checkerr ())
return 2;
cdrom_result_buffer[1] = 0;
cdaudiostop ();
return 2;
}
/* pause CD audio */
static int cdrom_command_pause (void)
{
#if AKIKO_DEBUG_IO_CMD