diff --git a/src/cpu/instructions/arithmetic_and_logic/add.rs b/src/cpu/instructions/arithmetic_and_logic/add.rs
index d170fdd..6dfd57b 100644
--- a/src/cpu/instructions/arithmetic_and_logic/add.rs
+++ b/src/cpu/instructions/arithmetic_and_logic/add.rs
@@ -18,8 +18,10 @@ impl CPU {
         } else {
             0
         };
-        let (result, overflow) = target_value.overflowing_add(value + carry);
-
+        let (partial, overflow) = value.overflowing_add(carry);
+        let (result, overflow2) = target_value.overflowing_add(partial);
+        let overflow = overflow || overflow2;
+        
         self.set_8bit_register(target, result);
 
         ConditionCodes {
diff --git a/src/cpu/instructions/arithmetic_and_logic/sub.rs b/src/cpu/instructions/arithmetic_and_logic/sub.rs
index 921cf18..6630ec5 100644
--- a/src/cpu/instructions/arithmetic_and_logic/sub.rs
+++ b/src/cpu/instructions/arithmetic_and_logic/sub.rs
@@ -21,7 +21,10 @@ impl CPU {
                 },
                 subtract: FlagState::Set,
                 half_carry: if ((a ^ value) & 0x10) != (result & 0x10) {FlagState::Set} else {FlagState::Unset},
-                carry: if value > a {FlagState::Set} else {FlagState::Unset},
+                carry: if add_carry {
+                    if value.wrapping_add(carry) > a {FlagState::Set} else {FlagState::Unset}
+                }else {
+                    if value > a {FlagState::Set} else {FlagState::Unset}},
             },
         }
     }