diff --git a/firmware/FT0/PM/hdl/fit.vhd b/firmware/FT0/PM/hdl/fit.vhd index 157e536..877d08c 100644 --- a/firmware/FT0/PM/hdl/fit.vhd +++ b/firmware/FT0/PM/hdl/fit.vhd @@ -294,7 +294,7 @@ signal ev_tout_cnt : STD_LOGIC_VECTOR (7 downto 0); signal CH_N0, CH_N1, CH_N0_0, CH_N1_0, CH_NUM : STD_LOGIC_VECTOR (3 downto 0); signal CH_NUM1, CH_NUM2 : STD_LOGIC_VECTOR (2 downto 0); signal WRDS_NUM : STD_LOGIC_VECTOR (2 downto 0); -signal Orbit_ID, hspid_w32, hspid_r32, tstamp, hspib_32 : STD_LOGIC_VECTOR (31 downto 0); +signal Orbit_ID, hspid_w32, hspid_r32, tstamp, hspib_32, mcu_tstamp : STD_LOGIC_VECTOR (31 downto 0); signal xadc_r, xadc_out : STD_LOGIC_VECTOR (15 downto 0); signal xadc_a: STD_LOGIC_VECTOR (6 downto 0); signal EV_ID_in, EV_ID_out : STD_LOGIC_VECTOR (55 downto 0); @@ -408,26 +408,6 @@ component TDCCHAN is end component; --- component GBT_TX_RX is --- Port ( RESET : in STD_LOGIC; --- MgtRefClk : in STD_LOGIC; --- MGT_RX_P : in STD_LOGIC; --- MGT_RX_N : in STD_LOGIC; --- MGT_TX_P : out STD_LOGIC; --- MGT_TX_N : out STD_LOGIC; --- TXDataClk : in STD_LOGIC; --- TXData : in STD_LOGIC_VECTOR (79 downto 0); --- TXData_SC : in STD_LOGIC_VECTOR (3 downto 0); --- IsTXData : in STD_LOGIC; --- RXDataClk : out STD_LOGIC; --- RXData : out STD_LOGIC_VECTOR (79 downto 0); --- RXData_SC : out STD_LOGIC_VECTOR (3 downto 0); --- IsRXData : out STD_LOGIC; --- RX_ready : out STD_LOGIC; --- RX_errors : out STD_LOGIC --- ); --- end component; - component EVENTID_FIFO Port ( clk : IN STD_LOGIC; srst : IN STD_LOGIC; @@ -1398,8 +1378,12 @@ if (HSCKI'event and HSCKI='0') then when 16#D8# to 16#e7# => if (hspi_h='0') then HSPI_DATA<=ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)(31 downto 16); else HSPI_DATA<=ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)(15 downto 0); end if; - when 16#E8# to 16#FB# => HSPI_DATA<=hspib_32(31 downto 16); hspi_32l <=hspib_32(15 downto 0); + when 16#E8# to 16#F6# => HSPI_DATA<=hspib_32(31 downto 16); hspi_32l <=hspib_32(15 downto 0); + + when 16#F7# => HSPI_DATA<=mcu_tstamp(31 downto 16); hspi_32l <=mcu_tstamp(15 downto 0); + when 16#F8# to 16#FB# => HSPI_DATA<=hspib_32(31 downto 16); hspi_32l <=hspib_32(15 downto 0); + when 16#FC# to 16#FE# => HSPI_DATA<=(others=>'0'); hspi_32l <=xadc_r; when 16#FF# => HSPI_DATA<=tstamp(31 downto 16); hspi_32l <=tstamp(15 downto 0); @@ -1439,7 +1423,10 @@ if (SCKi'event and SCKi='0') then MISOI<=SPI_DATA(15); end if; if (SCKI'event and SCKI='1') then if (spi_bit_count="11111") then spi_bit_count<="10000"; spi_na<='1'; - if (spi_rd='0') then spi_wr_data<=SPI_DATA(14 downto 0) & MOSII; + if (spi_rd='0') then + if (spi_addr(7 downto 0) = x"F5") then mcu_tstamp(15 downto 0) <= SPI_DATA(14 downto 0) & MOSII; end if; + if (spi_addr(7 downto 0) = x"F6") then mcu_tstamp(31 downto 16) <= SPI_DATA(14 downto 0) & MOSII; end if; + spi_wr_data<=SPI_DATA(14 downto 0) & MOSII; if (spi_addr(7)='0') then spi_wr_rdy<='1'; else if (spi_addr(6)='0') then spibuf_wr<='1'; end if; end if; end if; else diff --git a/firmware/FT0/TCM/hdl/BC_correlator.vhd b/firmware/FT0/TCM/hdl/BC_correlator.vhd new file mode 100644 index 0000000..b350f1b --- /dev/null +++ b/firmware/FT0/TCM/hdl/BC_correlator.vhd @@ -0,0 +1,102 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01/05/2021 08:02:13 PM +-- Design Name: +-- Module Name: BC_correlator - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity BC_correlator is + Port ( clk320 : in STD_LOGIC; + BC_cou : in STD_LOGIC_VECTOR (11 downto 0); + mt_cou : in STD_LOGIC_VECTOR (2 downto 0); + inc : in STD_LOGIC; + clr : in STD_LOGIC; + ipb_clk : in STD_LOGIC; + rd : in STD_LOGIC; + addr : in STD_LOGIC_VECTOR (11 downto 0); + data : out STD_LOGIC_VECTOR (31 downto 0) + ); +end BC_correlator; + +architecture RTL of BC_correlator is + +signal ack0, clr_mem, clr_req, inc_i : STD_LOGIC; +signal wea : STD_LOGIC_vector (0 downto 0); +signal m_rd, m_wr : STD_LOGIC_vector (31 downto 0); + +COMPONENT BC_corr_mem + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + clkb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + + +begin + +m0 : BC_corr_mem PORT MAP (clka => clk320, wea => wea, addra => BC_cou, dina => m_wr, douta => m_rd, clkb => ipb_clk, web => "0", addrb => addr, dinb => (others=>'0'), doutb => data); + + +m_wr<= x"0000000" & "000" & inc_i when (clr_mem='1') else m_rd+1; + +process(clk320) +begin +if (clk320'event and clk320='1') then + + if (clr='1') then clr_req<='1'; else + if (clr_req='1') and (BC_cou=0) and (mt_cou="010") then clr_req<='0'; end if; + end if; + +if (BC_cou=0) and (mt_cou="010") then clr_mem<=clr_req; end if; + +if (mt_cou="011") then + + inc_i<= inc; + + if (clr_mem='1') or (inc='1') then wea(0)<= '1'; end if; + +else + wea(0)<= '0'; +end if; + + + +end if; +end process; + +end RTL; diff --git a/firmware/FT0/TCM/hdl/pm-spi.vhd b/firmware/FT0/TCM/hdl/pm-spi.vhd index 129b44f..cf18f66 100644 --- a/firmware/FT0/TCM/hdl/pm-spi.vhd +++ b/firmware/FT0/TCM/hdl/pm-spi.vhd @@ -47,7 +47,8 @@ entity pm_spi is spi_mosi : out STD_LOGIC; spi_miso : in STD_LOGIC; cnt_rd : in STD_LOGIC; - PM_rst : in STD_LOGIC + PM_rst : in STD_LOGIC; + ena : in STD_LOGIC ); end pm_spi; @@ -60,7 +61,7 @@ signal A_old, A_spi : STD_LOGIC_VECTOR (7 downto 0); signal fifo_out : STD_LOGIC_VECTOR (31 downto 0); signal A_cou : STD_LOGIC_VECTOR (4 downto 0); signal cont, mode16, eoc, n_addr, rd_cou, smode, rd_spi, cs_spi, fifo_wr, fifo_rd, fifo_full, fifo_empty, reg_rd, spi_inp, rd_old : STD_LOGIC; -signal xmg_sel, xmg_md, xmg_smpl, x_wait, cmd_rst, cmd_rst1, rst_rq : STD_LOGIC; +signal xmg_sel, xmg_md, xmg_smpl, x_wait, cmd_rst, cmd_rst1, rst_rq, spi_sel_i : STD_LOGIC; signal fifo_cou : STD_LOGIC_VECTOR (9 downto 0); @@ -99,14 +100,15 @@ xmg_sel<='1' when (cs='1') and (A='1' & x"02") else '0'; xmg_md<= (xmg_sel and not smode) or cmd_rst; -spi_mosi<=Dreg(47); +spi_mosi<=Dreg(47) and ena; +spi_sel<= spi_sel_i and ena; spi_inp<=xmg_smpl when (xmg_md='1') else not spi_miso; A_spi<=A(7 downto 0) when (smode='0') else "110" & A_cou; rd_spi<= rd when (smode='0') else '1'; -spi_clk <= count(1) when ((count(7 downto 2)/="000000") and (xmg_md='0')) or (x_wait='0') else '0'; +spi_clk <= count(1) when (((count(7 downto 2)/="000000") and (xmg_md='0')) or (x_wait='0')) and (ena='1') else '0'; mode16<= '1' when A_spi(7 downto 4) ipb_clk, RST=> ipb_rst, DI=> ipb_data_out, DO=> spi_bus_in(i), A=> ipb_addr(8 downto 0), wr=> ipb_iswr, rd=> ipb_isrd, cs=> pm_select(i), rdy=> pm_rdy_a(i), spi_sel=> selai(i), spi_clk=> sckai(i), - spi_mosi=> mosiai(i), spi_miso=> misoai(i), cnt_rd=> cnt_rd, PM_rst =>PM_rst); + spi_mosi=> mosiai(i), spi_miso=> misoai(i), cnt_rd=> cnt_rd, PM_rst =>PM_rst, ena=> pm_ena(i)); pm_spiC: pm_spi Port map ( CLK=> ipb_clk, RST=> ipb_rst, DI=> ipb_data_out, DO=> spi_bus_in(i+10), A=> ipb_addr(8 downto 0), wr=> ipb_iswr, rd=> ipb_isrd, cs=> pm_select(i+10), rdy=> pm_rdy_a(i+10), spi_sel=>selci(i), spi_clk=> sckci(i), - spi_mosi=> mosici(i), spi_miso=> misoci(i), cnt_rd=> cnt_rd, PM_rst =>PM_rst); + spi_mosi=> mosici(i), spi_miso=> misoci(i), cnt_rd=> cnt_rd, PM_rst =>PM_rst, ena=> pm_ena(i+10)); end generate; cctrl_rst <= ipb_rst or PM_rst; @@ -894,6 +893,7 @@ hdmiac_select <= ipb_str when ipb_addr(31 downto 0)= x"0000001A" else '0'; lmode_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001B" else '0'; lpatt0_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001C" else '0'; lpatt1_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001D" else '0'; +pmena_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001E" else '0'; hdmics_select <= ipb_str when (ipb_addr(31 downto 4)= x"0000003") and (ipb_addr(3 downto 0)= x"000000D8") and (ipb_addr(31 downto 0)<= x"000000E7") else '0'; -rdouts_sel <= ipb_str when (ipb_addr(31 downto 0)>= x"000000E8") and (ipb_addr(31 downto 0)<= x"000000f7") and (ipb_isrd='1') else '0'; +rdouts_sel <= ipb_str when (ipb_addr(31 downto 0)>= x"000000E8") and (ipb_addr(31 downto 0)<= x"000000f6") and (ipb_isrd='1') else '0'; +mcuts_sel <= ipb_str when (ipb_addr(31 downto 0)= x"000000F7") and (ipb_isrd='1') else '0'; flshreg_sel <= ipb_str when (ipb_addr(31 downto 2)= x"000000F" & "10") else '0'; fifo_sel <= ipb_str when (ipb_addr(31 downto 0)= x"00000100") and (ipb_isrd='1') else '0'; fifo_csel <= ipb_str when (ipb_addr(31 downto 0)= x"00000101") and (ipb_isrd='1') else '0'; pm_adr_sel <= ipb_str when (ipb_addr(31 downto 14)= 0) and (ipb_addr(13 downto 9)/=0) and (ipb_addr(13 downto 9)<=20) else '0' ; tstamp_sel <= ipb_str when (ipb_addr(31 downto 0)= x"000000FF") and (ipb_isrd='1') else '0'; adc_sel<= ipb_str when (ipb_addr(31 downto 2)= x"000000F" & "11") and (ipb_isrd='1') and ipb_addr(1 downto 0)/="11" else '0'; - +bccorr_sel<= ipb_str when (ipb_addr(31 downto 12)= x"00004") and (ipb_isrd='1') else '0'; +bccorrA_sel<= ipb_str when (ipb_addr(31 downto 12)= x"00008") and (ipb_isrd='1') else '0'; +bccorrC_sel<= ipb_str when (ipb_addr(31 downto 12)= x"0000C") and (ipb_isrd='1') else '0'; + PM_sel: for i in 0 to 19 generate -pm_select(i)<= pm_adr_sel when (ipb_addr(13 downto 9)= i+1) else '0'; +pm_select(i)<= (pm_adr_sel and pm_ena(i)) when (ipb_addr(13 downto 9)= i+1) else '0'; end generate; @@ -927,6 +931,7 @@ ipb_iswr<=ipb_out.ipb_write and ipb_out.ipb_strobe; ipb_isrd<=(not ipb_out.ipb_w ipb_str<=ipb_out.ipb_strobe; ipb_wr<= ipb_out.ipb_write; pm_rdy<=pm_rdy_a(to_integer(unsigned(ipb_addr(14 downto 9)))-1); +pm_err<=not pm_ena(to_integer(unsigned(ipb_addr(14 downto 9)))-1); ipb_in.ipb_ack<= tcmx_ack when (tcmx_select='1') else tcmr_ack when (tcmr_select='1') @@ -937,13 +942,15 @@ else pm_rdy when (pm_adr_sel='1') else '1' when ((Tout_sel or Tmode_sel)='1') else Tcnt_ack when (Tcnt_sel='1') else '1' when (rdoutc_sel='1') -else rdouts_ack when (rdouts_sel='1') -else '1' when (fifo_sel or fifo_csel or lmode_sel or lpatt0_sel or lpatt1_sel or tstamp_sel) ='1' +else '1' when (rdouts_sel='1') +else '1' when (fifo_sel or fifo_csel or lmode_sel or lpatt0_sel or lpatt1_sel or tstamp_sel or mcuts_sel or pmena_sel) ='1' else d_rdy when (adc_sel='1') +else bccorr_ack when (bccorr_rd='1') else '0'; ipb_in.ipb_err<= tcmx_err when (tcmx_select='1') else Tcnt_err when (Tcnt_sel='1') +else pm_err when (pm_adr_sel='1') else '0'; @@ -954,12 +961,14 @@ else Status_a when ((hdmias_select='1') or (hdmiac_select='1')) and (ipb_isrd=' else l_mode when (lmode_sel='1') and (ipb_isrd='1') else l_patt0 when (lpatt0_sel='1') and (ipb_isrd='1') else l_patt1 when (lpatt1_sel='1') and (ipb_isrd='1') +else x"000" & pm_ena when (pmena_sel='1') and (ipb_isrd='1') else Status_C when ((hdmics_select='1') or (hdmicc_select='1')) and (ipb_isrd='1') else cnt_ctrl_data when (cnt_ctrl_sel='1') and (ipb_isrd='1') else trg_r(to_integer(unsigned(ipb_addr(3 downto 1)))) when (Tout_sel='1') and (ipb_isrd='1') and (ipb_addr(3 downto 0)'0'); with ipb_addr(2 downto 0) select @@ -976,7 +989,7 @@ local_reg_rd<= x"0000" & std_logic_vector(resize(signed(Tlow),16)) when "000", x"0000" & SC_C when "011", x"0000" & C_A when "100", x"0000" & C_C when "101", - x"0000" & x"000" & Tmode when "110", + x"0000" & x"00" & Tmode when "110", PM_rq & RST_req & clk_l & gbt_global_status & GBTRXerr_ipb & GBTRX_ready & clk_src & rst_fl & pll_lock_c & pll_lock_a when "111"; Tcnt_clr<= ipb_str when (ipb_addr(31 downto 0)= x"0000000F") and (ipb_iswr='1') and (ipb_data_out(9)='1') else '0'; @@ -999,8 +1012,6 @@ ipb_stat_rd<= '1' when (ipb_isrd='1') and (tcmr_select='1') and (ipb_addr(2 down hdmis_ack<= '1' when (ipb_isrd='1') else '0'; -rdouts_ack<= '1' when (rdouts_sel='1') and (ipb_isrd='1') else '0'; - stat_clrA<=hdmiac_select and ipb_isrd; stat_clrC<=hdmicc_select and ipb_isrd; UA2 : USR_ACCESSE2 port map (CFGCLK => open, DATA => t_stmp, DATAVALID => open ); @@ -1106,6 +1117,8 @@ if (SCKi'event and SCKi='1') then when 16#F2# => mac_addr(15 downto 0)<=SPI_DATA(14 downto 0) & MOSIi; when 16#F3# => mac_addr(31 downto 16)<=SPI_DATA(14 downto 0) & MOSIi; when 16#F4# => ipb_stp<='0'; mac_addr(47 downto 32)<=SPI_DATA(14 downto 0) & MOSIi; + when 16#F5# => mcu_ts(15 downto 0)<=SPI_DATA(14 downto 0) & MOSIi; + when 16#F6# => mcu_ts(31 downto 16)<=SPI_DATA(14 downto 0) & MOSIi; when others => null; end case; end if; @@ -1127,7 +1140,7 @@ if (SCKi'event and SCKi='1') then when 3 => SPI_DATA<= SC_C; when 4 => SPI_DATA<= C_A; when 5 => SPI_DATA<= C_C; - when 6 => SPI_DATA<=x"000" & Tmode; + when 6 => SPI_DATA<=x"00" & Tmode; when 16#10# to 16#17# => SPI_DATA<=spi_buf_out; when 16#18# => SPI_DATA<= x"000" & ldr; @@ -1138,6 +1151,8 @@ if (SCKi'event and SCKi='1') then when 16#F2# => SPI_DATA<=mac_addr(15 downto 0); when 16#F3# => SPI_DATA<=mac_addr(31 downto 16); when 16#F4# => SPI_DATA<=mac_addr(47 downto 32); + when 16#F5# => SPI_DATA<=mcu_ts(15 downto 0); + when 16#F6# => SPI_DATA<=mcu_ts(31 downto 16); when 16#F8# => SPI_DATA<=x"00" & "000" & rd_buf_vector; when others => SPI_DATA<=x"0000"; end case; @@ -1156,10 +1171,14 @@ irqi<= dcs_irq or IPB_chg or GBT_chg or GBTRXerr or RST_req when (irq_cnt="11") PM_rst <= rst_spi2 and (not rst_spi1); +bccorr_rd<= bccorr_sel or bccorrA_sel or bccorrC_sel; bccorr_ack<=bccorr_ack0 and bccorr_rd; + process(ipb_clk) begin if (ipb_clk'event and ipb_clk='1') then +if (bccorr_ack0='0') and (bccorr_rd='1') then bccorr_ack0<='1'; else bccorr_ack0<='0'; end if; + adc_sel1<=adc_sel and not d_rdy; for i in 0 to 9 loop @@ -1203,6 +1222,7 @@ if (rst_spi1='1') then l_mode<=(others=>'0'); end if; if (lpatt0_sel='1') and (ipb_iswr='1') then l_patt0<=ipb_data_out(31 downto 0); end if; if (lpatt1_sel='1') and (ipb_iswr='1') then l_patt1<=ipb_data_out(31 downto 0); end if; +if (pmena_sel='1') and (ipb_iswr='1') then pm_ena<=ipb_data_out(19 downto 0); end if; if (rst_spi1='1') or ((GBTRX_ready2='1') and (GBTRX_ready1='0')) then readout_conf(0)(22)<='1'; else @@ -1275,7 +1295,7 @@ spi_wr2<=spi_wr1; spi_wr1<=spi_wr0; spi_wr0<=spi_wr_rdy; when "011" => SC_C<=Treg_data; when "100" => C_A<=Treg_data; when "101" => C_C<=Treg_data; - when "110" => Tmode<=Treg_data(3 downto 0); + when "110" => Tmode<=Treg_data(7 downto 0); when others => null; end case; @@ -1337,6 +1357,28 @@ cou_AC: counter32 port map (clk320=> clk320A, cout=> count_r(11), rd=> cnt_lock cou_CC: counter32 port map (clk320=> clk320A, cout=> count_r(12), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Cclr); cou_orc: counter32 port map (clk320=> clk320A, cout=> count_r(13), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Orclr); cou_andc: counter32 port map (clk320=> clk320A, cout=> count_r(14), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Andclr); + +with Tmode(7 downto 4) select corr_inc<= + '0' when x"0", + orA_str when x"1", + orC_i when x"2", + SC_str when x"3", + CC_str when x"4", + V_str when x"5", + bkgndA when x"6", + bkgndC when x"7", + bkgndA and bkgndC when x"8", + bkgndA or bkgndC when x"9", + orA_str and orC_i when x"A", + orA_str or orC_i when x"B", + bkgndA and not orA_str when x"C", + bkgndC and not orC_i when x"D", + (bkgndA and not orA_str) or (bkgndC and not orC_i) when x"E", + (bkgndA and not orA_str) and (bkgndC and not orC_i) when x"F"; + +m_cr: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>corr_inc, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorr_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrl); +m_crA: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orA_str, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorrA_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrA); +m_crC: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orC_i, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorrC_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrC); Vertex_0<= '1' when (signed(Tdiff)>=signed(Tlow)) and (signed(Tdiff)<=signed(Thigh)) and (OrA_i='1') and (OrC_i='1') else '0'; @@ -1414,7 +1456,8 @@ if (bitcnt_A="010") then gbt_wr<='1'; end if; - orA_str<= OrA_i; + orA_str<= OrA_i; SC_str<= SC_0; CC_str<= C_0; V_str<=Vertex_0; + end if; diff --git a/firmware/FT0/TCM/ipcore_properties/BC_corr_mem.txt b/firmware/FT0/TCM/ipcore_properties/BC_corr_mem.txt new file mode 100644 index 0000000..9b506f4 --- /dev/null +++ b/firmware/FT0/TCM/ipcore_properties/BC_corr_mem.txt @@ -0,0 +1,78 @@ +Property Type Read-only Value +CONFIG.AXILITE_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_ID_Width string false 4 +CONFIG.AXI_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_Slave_Type string false Memory_Slave +CONFIG.AXI_Type string false AXI4_Full +CONFIG.Additional_Inputs_for_Power_Estimation string false false +CONFIG.Algorithm string false Minimum_Area +CONFIG.Assume_Synchronous_Clk string false false +CONFIG.Byte_Size string false 9 +CONFIG.CLK.ACLK.INSERT_VIP string false 0 +CONFIG.CTRL_ECC_ALGO string false NONE +CONFIG.Coe_File string false no_coe_file_loaded +CONFIG.Collision_Warnings string false ALL +CONFIG.Component_Name string false BC_corr_mem +CONFIG.Disable_Collision_Warnings string false false +CONFIG.Disable_Out_of_Range_Warnings string false false +CONFIG.ECC string false false +CONFIG.EN_DEEPSLEEP_PIN string false false +CONFIG.EN_ECC_PIPE string false false +CONFIG.EN_SAFETY_CKT string false false +CONFIG.EN_SHUTDOWN_PIN string false false +CONFIG.EN_SLEEP_PIN string false false +CONFIG.Enable_32bit_Address string false false +CONFIG.Enable_A string false Always_Enabled +CONFIG.Enable_B string false Always_Enabled +CONFIG.Error_Injection_Type string false Single_Bit_Error_Injection +CONFIG.Fill_Remaining_Memory_Locations string false false +CONFIG.Interface_Type string false Native +CONFIG.Load_Init_File string false false +CONFIG.MEM_FILE string false no_mem_loaded +CONFIG.Memory_Type string false True_Dual_Port_RAM +CONFIG.Operating_Mode_A string false NO_CHANGE +CONFIG.Operating_Mode_B string false READ_FIRST +CONFIG.Output_Reset_Value_A string false 0 +CONFIG.Output_Reset_Value_B string false 0 +CONFIG.PRIM_type_to_Implement string false BRAM +CONFIG.Pipeline_Stages string false 0 +CONFIG.Port_A_Clock string false 100 +CONFIG.Port_A_Enable_Rate string false 100 +CONFIG.Port_A_Write_Rate string false 50 +CONFIG.Port_B_Clock string false 100 +CONFIG.Port_B_Enable_Rate string false 100 +CONFIG.Port_B_Write_Rate string false 50 +CONFIG.Primitive string false 8kx2 +CONFIG.RD_ADDR_CHNG_A string false false +CONFIG.RD_ADDR_CHNG_B string false false +CONFIG.READ_LATENCY_A string false 1 +CONFIG.READ_LATENCY_B string false 1 +CONFIG.RST.ARESETN.INSERT_VIP string false 0 +CONFIG.Read_Width_A string false 32 +CONFIG.Read_Width_B string false 32 +CONFIG.Register_PortA_Output_of_Memory_Core string false false +CONFIG.Register_PortA_Output_of_Memory_Primitives string false false +CONFIG.Register_PortB_Output_of_Memory_Core string false false +CONFIG.Register_PortB_Output_of_Memory_Primitives string false false +CONFIG.Remaining_Memory_Locations string false 0 +CONFIG.Reset_Memory_Latch_A string false false +CONFIG.Reset_Memory_Latch_B string false false +CONFIG.Reset_Priority_A string false CE +CONFIG.Reset_Priority_B string false CE +CONFIG.Reset_Type string false SYNC +CONFIG.Use_AXI_ID string false false +CONFIG.Use_Byte_Write_Enable string false false +CONFIG.Use_Error_Injection_Pins string false false +CONFIG.Use_REGCEA_Pin string false false +CONFIG.Use_REGCEB_Pin string false false +CONFIG.Use_RSTA_Pin string false false +CONFIG.Use_RSTB_Pin string false false +CONFIG.Write_Depth_A string false 4096 +CONFIG.Write_Width_A string false 32 +CONFIG.Write_Width_B string false 32 +CONFIG.ecctype string false No_ECC +CONFIG.register_porta_input_of_softecc string false false +CONFIG.register_portb_output_of_softecc string false false +CONFIG.softecc string false false +CONFIG.use_bram_block string false Stand_Alone +IPDEF string true xilinx.com:ip:blk_mem_gen:8.4 diff --git a/firmware/FT0/TCM/make.tcl b/firmware/FT0/TCM/make.tcl index 854ed89..bfe9dc7 100644 --- a/firmware/FT0/TCM/make.tcl +++ b/firmware/FT0/TCM/make.tcl @@ -78,7 +78,7 @@ if { $::argc > 0 } { # Set the directory path for the original project from where this script was exported set orig_proj_dir "[file normalize "$origin_dir/build"]" -if {[string equal [open_project -quiet "build/TCM.xpr"] ""]} { +if {[string equal [open_project -quiet "build/TCM_proto.xpr"] ""]} { set proj_create "yes" puts ${proj_create} puts ${project_name} @@ -122,12 +122,13 @@ set obj [get_filesets sources_1] set files [list \ [file normalize "${origin_dir}/hdl/counter32.vhd" ]\ [file normalize "${origin_dir}/hdl/Flash_prog.vhd" ]\ - [file normalize "${origin_dir}/hdl/tcm.vhd" ]\ + [file normalize "${origin_dir}/hdl/tcm_proto.vhd" ]\ [file normalize "${origin_dir}/hdl/pm-spi.vhd" ]\ [file normalize "${origin_dir}/hdl/cnt_ctrl.vhd" ]\ [file normalize "${origin_dir}/hdl/trigger_out.vhd" ]\ [file normalize "${origin_dir}/hdl/tcm_side.vhd" ]\ [file normalize "${origin_dir}/hdl/HDMIRX.vhd" ]\ + [file normalize "${origin_dir}/../TCM/hdl/BC_correlator.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_dualportram.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_arp.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd" ]\ @@ -254,7 +255,7 @@ if {[string equal $proj_create "yes"]} { # Set 'sources_1' fileset properties set_property \ -dict [list \ - "top" "tcm"] \ + "top" "tcm_proto"] \ [get_filesets sources_1] # Create 'constrs_1' fileset (if not found) diff --git a/firmware/FT0/TCM/xdc/timing.xdc b/firmware/FT0/TCM/xdc/timing.xdc index 5db0ebc..5382c70 100644 --- a/firmware/FT0/TCM/xdc/timing.xdc +++ b/firmware/FT0/TCM/xdc/timing.xdc @@ -23,8 +23,8 @@ set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {Fi set_max_delay -datapath_only -from [get_clocks CLKsys40] -to [get_pins readout_laser_out_ff0_reg/D] 3.000 set_max_delay -datapath_only -from [get_clocks MCLKA] -to [get_cells laser_t0_reg] 3.000 -set_multicycle_path -setup -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]}}] 2 -set_multicycle_path -hold -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]}}] 1 +set_multicycle_path -setup -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]} V_str_reg}] 2 +set_multicycle_path -hold -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]} V_str_reg}] 1 set_multicycle_path -setup -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks CLKA320] 2 @@ -32,8 +32,11 @@ set_multicycle_path -hold -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks set_multicycle_path -setup -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 2 set_multicycle_path -hold -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 1 -set_multicycle_path -setup -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg}] 2 -set_multicycle_path -hold -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg}] 1 +set_multicycle_path -setup -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg SC_str_reg CC_str_reg}] 2 +set_multicycle_path -hold -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg SC_str_reg CC_str_reg}] 1 + +set_multicycle_path -setup -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 2 +set_multicycle_path -hold -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 1 set_max_delay -datapath_only -from [get_clocks CLKC320] -to [get_clocks CLKA320] 3.000 @@ -56,3 +59,5 @@ set_false_path -from [get_clocks -include_generated_clocks MCLKA] -to [get_clock set_false_path -from [get_clocks RXDataCLK] -to [get_cells {rout_buf_reg[*]}] + + diff --git a/firmware/FT0/TCM_v1/hdl/tcm.vhd b/firmware/FT0/TCM_v1/hdl/tcm.vhd index 1f8c1d4..61b51a7 100644 --- a/firmware/FT0/TCM_v1/hdl/tcm.vhd +++ b/firmware/FT0/TCM_v1/hdl/tcm.vhd @@ -159,7 +159,7 @@ type rdout_stat_arr is array (7 downto 0) of std_logic_vector (31 downto 0); signal HDMIA_P, HDMIA_N, HDMIC_P, HDMIC_N, TDA_P, TDA_N, TDC_P, TDC_N : HDMI_trig; signal TDA, TDC, TDC0, TDC1, TDC2 : Trgdat; -signal hdmia_config, hdmic_config, Status_A, Status_C, f_out, f_inp, l_mode, l_patt0, l_patt1, Orbit_ID, flash_data_out, t_stmp, rout_buf : STD_LOGIC_VECTOR (31 downto 0); +signal hdmia_config, hdmic_config, Status_A, Status_C, f_out, f_inp, l_mode, l_patt0, l_patt1, Orbit_ID, flash_data_out, t_stmp, rout_buf, mcu_ts, bc_corrl, bc_corrA, bc_corrC : STD_LOGIC_VECTOR (31 downto 0); signal trig_mod: STD_LOGIC_VECTOR (14 downto 0); signal trg_r_wr : STD_LOGIC_VECTOR (4 downto 0); signal trg_r : Tout_arr; @@ -216,21 +216,24 @@ signal lpatt_cnt, Nchan_A, Nchan_C, Nchan_C0, Nchan_C1, Nchan_C2 : STD_LOGIC_VEC signal lpatt_sreg : STD_LOGIC_VECTOR (63 downto 0); signal lfreq_cnt : STD_LOGIC_VECTOR (23 downto 0); signal BC_cou : STD_LOGIC_VECTOR(11 downto 0); -signal Tmode, ldr : STD_LOGIC_VECTOR(3 downto 0); +signal ldr : STD_LOGIC_VECTOR(3 downto 0); +signal Tmode : STD_LOGIC_VECTOR(7 downto 0); signal Rd_word, FIFO_in : STD_LOGIC_VECTOR(159 downto 0); -signal gbt_wr, gbt_empty, rdoutc_sel, rdoutc_ack, rdoutc_wr, rdouts_sel, rdouts_ack, RST_req : STD_LOGIC; +signal gbt_wr, gbt_empty, rdoutc_sel, rdoutc_ack, rdoutc_wr, rdouts_sel, RST_req : STD_LOGIC; --signal readout_conf : rdout_conf_arr; --signal readout_stat : rdout_stat_arr; signal readout_conf : cntr_reg_addrreg_type; signal readout_stat : status_reg_addrreg_type; signal New_BCID : STD_LOGIC; signal las_o, l_st, flshreg_sel, bkgndA, bkgndC, bkgndC0, bkgndC1, bkgndC2, bgA_inc, bgC_inc, bgOr, bgAnd, orA_str, orA_cnt, orC_cnt, Or_or, Or_and, Bg_Aclr, Bg_Cclr, Bg_Orclr, Bg_Andclr, sca, scc, ca, cc, scb, cb : STD_LOGIC; -signal tstamp_sel, d_rd, d_rdy, adc_sel, adc_sel1, rout_lock0, rout_lock1, rout_lock2, PM_rst, cctrl_rst, clk_src, clk_l, clk_frs : STD_LOGIC; +signal tstamp_sel, d_rd, d_rdy, adc_sel, adc_sel1, rout_lock0, rout_lock1, rout_lock2, PM_rst, cctrl_rst, clk_src, clk_l, clk_frs, mcuts_sel, pmena_sel, pm_err, bccorr_sel, bccorr_ack, corr_inc, SC_str, CC_str, V_str : STD_LOGIC; +signal bccorrA_sel, bccorrC_sel, bccorr_ack0, bccorr_rd : STD_LOGIC; signal d_addr : STD_LOGIC_VECTOR(6 DOWNTO 0); signal d_sns : STD_LOGIC_VECTOR(15 DOWNTO 0); signal rx_phase_status : std_logic_vector(3 downto 0); signal laser_t0, laser_t : std_logic; +signal pm_ena : std_logic_vector(19 downto 0) := x"00000"; component tcm_side is Port (CLKA : in STD_LOGIC; @@ -303,25 +306,6 @@ END COMPONENT; ); end component; --- component GBT_TX_RX is - -- Port ( RESET : in STD_LOGIC; - -- MgtRefClk : in STD_LOGIC; - -- MGT_RX_P : in STD_LOGIC; - -- MGT_RX_N : in STD_LOGIC; - -- MGT_TX_P : out STD_LOGIC; - -- MGT_TX_N : out STD_LOGIC; - -- TXDataClk : in STD_LOGIC; - -- TXData : in STD_LOGIC_VECTOR (79 downto 0); - -- TXData_SC : in STD_LOGIC_VECTOR (3 downto 0); - -- IsTXData : in STD_LOGIC; - -- RXDataClk : out STD_LOGIC; - -- RXData : out STD_LOGIC_VECTOR (79 downto 0); - -- RXData_SC : out STD_LOGIC_VECTOR (3 downto 0); - -- IsRXData : out STD_LOGIC; - -- RX_ready : out STD_LOGIC; - -- RX_errors : out STD_LOGIC - -- ); --- end component; component FLASH generic ( @@ -351,7 +335,18 @@ component counter32 ); end component; - +component BC_correlator is + Port ( clk320 : in STD_LOGIC; + BC_cou : in STD_LOGIC_VECTOR (11 downto 0); + mt_cou : in STD_LOGIC_VECTOR (2 downto 0); + inc : in STD_LOGIC; + clr : in STD_LOGIC; + ipb_clk : in STD_LOGIC; + rd : in STD_LOGIC; + addr : in STD_LOGIC_VECTOR (11 downto 0); + data : out STD_LOGIC_VECTOR (31 downto 0) + ); +end component; -- ############################################### -- ######### GBT Readout ######################## @@ -456,7 +451,8 @@ END COMPONENT; spi_mosi : out STD_LOGIC; spi_miso : in STD_LOGIC; cnt_rd : in STD_LOGIC; - PM_rst : in STD_LOGIC + PM_rst : in STD_LOGIC; + ena : in STD_LOGIC ); end component; @@ -883,10 +879,10 @@ t100ms <='1' when cou_100ms=3999999 else '0'; PM_SC: for i in 0 to 9 generate pm_spiA: pm_spi Port map ( CLK => ipb_clk, RST=> ipb_rst, DI=> ipb_data_out, DO=> spi_bus_in(i), A=> ipb_addr(8 downto 0), wr=> ipb_iswr, rd=> ipb_isrd, cs=> pm_select(i), rdy=> pm_rdy_a(i), spi_sel=> selai(i), spi_clk=> sckai(i), - spi_mosi=> mosiai(i), spi_miso=> misoai(i), cnt_rd=> cnt_rd, PM_rst =>PM_rst); + spi_mosi=> mosiai(i), spi_miso=> misoai(i), cnt_rd=> cnt_rd, PM_rst =>PM_rst, ena=> pm_ena(i)); pm_spiC: pm_spi Port map ( CLK=> ipb_clk, RST=> ipb_rst, DI=> ipb_data_out, DO=> spi_bus_in(i+10), A=> ipb_addr(8 downto 0), wr=> ipb_iswr, rd=> ipb_isrd, cs=> pm_select(i+10), rdy=> pm_rdy_a(i+10), spi_sel=>selci(i), spi_clk=> sckci(i), - spi_mosi=> mosici(i), spi_miso=> misoci(i), cnt_rd=> cnt_rd, PM_rst =>PM_rst); + spi_mosi=> mosici(i), spi_miso=> misoci(i), cnt_rd=> cnt_rd, PM_rst =>PM_rst, ena=> pm_ena(i+10)); end generate; cctrl_rst <= ipb_rst or PM_rst; @@ -906,6 +902,7 @@ hdmiac_select <= ipb_str when ipb_addr(31 downto 0)= x"0000001A" else '0'; lmode_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001B" else '0'; lpatt0_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001C" else '0'; lpatt1_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001D" else '0'; +pmena_sel<= ipb_str when ipb_addr(31 downto 0)= x"0000001E" else '0'; hdmics_select <= ipb_str when (ipb_addr(31 downto 4)= x"0000003") and (ipb_addr(3 downto 0)= x"000000D8") and (ipb_addr(31 downto 0)<= x"000000E7") else '0'; -rdouts_sel <= ipb_str when (ipb_addr(31 downto 0)>= x"000000E8") and (ipb_addr(31 downto 0)<= x"000000f7") and (ipb_isrd='1') else '0'; +rdouts_sel <= ipb_str when (ipb_addr(31 downto 0)>= x"000000E8") and (ipb_addr(31 downto 0)<= x"000000F6") and (ipb_isrd='1') else '0'; +mcuts_sel <= ipb_str when (ipb_addr(31 downto 0)= x"000000F7") and (ipb_isrd='1') else '0'; flshreg_sel <= ipb_str when (ipb_addr(31 downto 2)= x"000000F" & "10") else '0'; fifo_sel <= ipb_str when (ipb_addr(31 downto 0)= x"00000100") and (ipb_isrd='1') else '0'; fifo_csel <= ipb_str when (ipb_addr(31 downto 0)= x"00000101") and (ipb_isrd='1') else '0'; pm_adr_sel <= ipb_str when (ipb_addr(31 downto 14)= 0) and (ipb_addr(13 downto 9)/=0) and (ipb_addr(13 downto 9)<=20) else '0' ; tstamp_sel <= ipb_str when (ipb_addr(31 downto 0)= x"000000FF") and (ipb_isrd='1') else '0'; adc_sel<= ipb_str when (ipb_addr(31 downto 2)= x"000000F" & "11") and (ipb_isrd='1') and ipb_addr(1 downto 0)/="11" else '0'; +bccorr_sel<= ipb_str when (ipb_addr(31 downto 12)= x"00004") and (ipb_isrd='1') else '0'; +bccorrA_sel<= ipb_str when (ipb_addr(31 downto 12)= x"00008") and (ipb_isrd='1') else '0'; +bccorrC_sel<= ipb_str when (ipb_addr(31 downto 12)= x"0000C") and (ipb_isrd='1') else '0'; PM_sel: for i in 0 to 19 generate -pm_select(i)<= pm_adr_sel when (ipb_addr(13 downto 9)= i+1) else '0'; +pm_select(i)<= (pm_adr_sel and pm_ena(i)) when (ipb_addr(13 downto 9)= i+1) else '0'; end generate; @@ -939,6 +940,7 @@ ipb_iswr<=ipb_out.ipb_write and ipb_out.ipb_strobe; ipb_isrd<=(not ipb_out.ipb_w ipb_str<=ipb_out.ipb_strobe; ipb_wr<= ipb_out.ipb_write; pm_rdy<=pm_rdy_a(to_integer(unsigned(ipb_addr(14 downto 9)))-1); +pm_err<=not pm_ena(to_integer(unsigned(ipb_addr(14 downto 9)))-1); ipb_in.ipb_ack<= tcmx_ack when (tcmx_select='1') else tcmr_ack when (tcmr_select='1') @@ -949,13 +951,15 @@ else pm_rdy when (pm_adr_sel='1') else '1' when ((Tout_sel or Tmode_sel)='1') else Tcnt_ack when (Tcnt_sel='1') else '1' when (rdoutc_sel='1') -else rdouts_ack when (rdouts_sel='1') -else '1' when (fifo_sel or fifo_csel or lmode_sel or lpatt0_sel or lpatt1_sel or tstamp_sel) ='1' +else '1' when (rdouts_sel='1') +else '1' when (fifo_sel or fifo_csel or lmode_sel or lpatt0_sel or lpatt1_sel or tstamp_sel or mcuts_sel or pmena_sel) ='1' else d_rdy when (adc_sel='1') +else bccorr_ack when (bccorr_rd='1') else '0'; ipb_in.ipb_err<= tcmx_err when (tcmx_select='1') else Tcnt_err when (Tcnt_sel='1') +else pm_err when (pm_adr_sel='1') else '0'; @@ -966,12 +970,14 @@ else Status_a when ((hdmias_select='1') or (hdmiac_select='1')) and (ipb_isrd=' else l_mode when (lmode_sel='1') and (ipb_isrd='1') else l_patt0 when (lpatt0_sel='1') and (ipb_isrd='1') else l_patt1 when (lpatt1_sel='1') and (ipb_isrd='1') +else x"000" & pm_ena when (pmena_sel='1') and (ipb_isrd='1') else Status_C when ((hdmics_select='1') or (hdmicc_select='1')) and (ipb_isrd='1') else cnt_ctrl_data when (cnt_ctrl_sel='1') and (ipb_isrd='1') else trg_r(to_integer(unsigned(ipb_addr(3 downto 1)))) when (Tout_sel='1') and (ipb_isrd='1') and (ipb_addr(3 downto 0)'0'); with ipb_addr(2 downto 0) select @@ -988,7 +997,7 @@ local_reg_rd<= x"0000" & std_logic_vector(resize(signed(Tlow),16)) when "000", x"0000" & SC_C when "011", x"0000" & C_A when "100", x"0000" & C_C when "101", - x"0000" & x"000" & Tmode when "110", + x"0000" & x"00" & Tmode when "110", PM_rq & RST_req & clk_l & gbt_global_status & GBTRXerr_ipb & GBTRX_ready & clk_src & rst_fl & pll_lock_c & pll_lock_a when "111"; Tcnt_clr<= ipb_str when (ipb_addr(31 downto 0)= x"0000000F") and (ipb_iswr='1') and (ipb_data_out(9)='1') else '0'; @@ -1011,7 +1020,6 @@ ipb_stat_rd<= '1' when (ipb_isrd='1') and (tcmr_select='1') and (ipb_addr(2 down hdmis_ack<= '1' when (ipb_isrd='1') else '0'; -rdouts_ack<= '1' when (rdouts_sel='1') and (ipb_isrd='1') else '0'; stat_clrA<=hdmiac_select and ipb_isrd; stat_clrC<=hdmicc_select and ipb_isrd; @@ -1126,6 +1134,8 @@ if (SCKi'event and SCKi='1') then when 16#F2# => mac_addr(15 downto 0)<=SPI_DATA(14 downto 0) & MOSIi; when 16#F3# => mac_addr(31 downto 16)<=SPI_DATA(14 downto 0) & MOSIi; when 16#F4# => ipb_stp<='0'; mac_addr(47 downto 32)<=SPI_DATA(14 downto 0) & MOSIi; + when 16#F5# => mcu_ts(15 downto 0)<=SPI_DATA(14 downto 0) & MOSIi; + when 16#F6# => mcu_ts(31 downto 16)<=SPI_DATA(14 downto 0) & MOSIi; when others => null; end case; end if; @@ -1147,7 +1157,7 @@ if (SCKi'event and SCKi='1') then when 3 => SPI_DATA<= SC_C; when 4 => SPI_DATA<= C_A; when 5 => SPI_DATA<= C_C; - when 6 => SPI_DATA<=x"000" & Tmode; + when 6 => SPI_DATA<=x"00" & Tmode; when 16#10# to 16#17# => SPI_DATA<=spi_buf_out; when 16#18# => SPI_DATA<= x"000" & ldr; @@ -1158,6 +1168,8 @@ if (SCKi'event and SCKi='1') then when 16#F2# => SPI_DATA<=mac_addr(15 downto 0); when 16#F3# => SPI_DATA<=mac_addr(31 downto 16); when 16#F4# => SPI_DATA<=mac_addr(47 downto 32); + when 16#F5# => SPI_DATA<=mcu_ts(15 downto 0); + when 16#F6# => SPI_DATA<=mcu_ts(31 downto 16); when 16#F8# => SPI_DATA<=x"00" & "000" & rd_buf_vector; when others => SPI_DATA<=x"0000"; end case; @@ -1176,10 +1188,14 @@ irqi<= dcs_irq or IPB_chg or GBT_chg or GBTRXerr or RST_req when (irq_cnt="11") PM_rst <= rst_spi2 and (not rst_spi1); +bccorr_rd<= bccorr_sel or bccorrA_sel or bccorrC_sel; bccorr_ack<=bccorr_ack0 and bccorr_rd; + process(ipb_clk) begin if (ipb_clk'event and ipb_clk='1') then +if (bccorr_ack0='0') and (bccorr_rd='1') then bccorr_ack0<='1'; else bccorr_ack0<='0'; end if; + adc_sel1<=adc_sel and not d_rdy; for i in 0 to 9 loop @@ -1222,6 +1238,7 @@ if (rst_spi1='1') then l_mode<=(others=>'0'); end if; if (lpatt0_sel='1') and (ipb_iswr='1') then l_patt0<=ipb_data_out(31 downto 0); end if; if (lpatt1_sel='1') and (ipb_iswr='1') then l_patt1<=ipb_data_out(31 downto 0); end if; +if (pmena_sel='1') and (ipb_iswr='1') then pm_ena<=ipb_data_out(19 downto 0); end if; if (rst_spi1='1') or ((GBTRX_ready2='1') and (GBTRX_ready1='0')) then readout_conf(0)(22)<='1'; else @@ -1294,7 +1311,7 @@ spi_wr2<=spi_wr1; spi_wr1<=spi_wr0; spi_wr0<=spi_wr_rdy; when "011" => SC_C<=Treg_data; when "100" => C_A<=Treg_data; when "101" => C_C<=Treg_data; - when "110" => Tmode<=Treg_data(3 downto 0); + when "110" => Tmode<=Treg_data(7 downto 0); when others => null; end case; @@ -1355,7 +1372,29 @@ cou_orand: counter32 port map (clk320=> clk320A, cout=> count_r(10), rd=> cnt_l cou_AC: counter32 port map (clk320=> clk320A, cout=> count_r(11), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Aclr); cou_CC: counter32 port map (clk320=> clk320A, cout=> count_r(12), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Cclr); cou_orc: counter32 port map (clk320=> clk320A, cout=> count_r(13), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Orclr); -cou_andc: counter32 port map (clk320=> clk320A, cout=> count_r(14), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Andclr); +cou_andc: counter32 port map (clk320=> clk320A, cout=> count_r(14), rd=> cnt_lock, clr=> cnt_clr, inc=> bg_Andclr); + +with Tmode(7 downto 4) select corr_inc<= + '0' when x"0", + orA_str when x"1", + orC_i when x"2", + SC_str when x"3", + CC_str when x"4", + V_str when x"5", + bkgndA when x"6", + bkgndC when x"7", + bkgndA and bkgndC when x"8", + bkgndA or bkgndC when x"9", + orA_str and orC_i when x"A", + orA_str or orC_i when x"B", + bkgndA and not orA_str when x"C", + bkgndC and not orC_i when x"D", + (bkgndA and not orA_str) or (bkgndC and not orC_i) when x"E", + (bkgndA and not orA_str) and (bkgndC and not orC_i) when x"F"; + +m_cr: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>corr_inc, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorr_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrl); +m_crA: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orA_str, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorrA_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrA); +m_crC: BC_correlator port map(clk320 =>CLK320A, BC_cou =>BC_COU, mt_cou =>bitcnt_A, inc =>orC_i, clr =>cnt_clr, ipb_clk => ipb_clk, rd =>bccorrC_sel, addr =>ipb_addr(11 downto 0), data =>bc_corrC); Vertex_0<= '1' when (signed(Tdiff)>=signed(Tlow)) and (signed(Tdiff)<=signed(Thigh)) and (OrA_i='1') and (OrC_i='1') else '0'; @@ -1433,7 +1472,7 @@ if (bitcnt_A="010") then gbt_wr<='1'; end if; - orA_str<= OrA_i; + orA_str<= OrA_i; SC_str<= SC_0; CC_str<= C_0; V_str<=Vertex_0; end if; diff --git a/firmware/FT0/TCM_v1/ipcore_properties/BC_corr_mem.txt b/firmware/FT0/TCM_v1/ipcore_properties/BC_corr_mem.txt new file mode 100644 index 0000000..9b506f4 --- /dev/null +++ b/firmware/FT0/TCM_v1/ipcore_properties/BC_corr_mem.txt @@ -0,0 +1,78 @@ +Property Type Read-only Value +CONFIG.AXILITE_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_ID_Width string false 4 +CONFIG.AXI_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_Slave_Type string false Memory_Slave +CONFIG.AXI_Type string false AXI4_Full +CONFIG.Additional_Inputs_for_Power_Estimation string false false +CONFIG.Algorithm string false Minimum_Area +CONFIG.Assume_Synchronous_Clk string false false +CONFIG.Byte_Size string false 9 +CONFIG.CLK.ACLK.INSERT_VIP string false 0 +CONFIG.CTRL_ECC_ALGO string false NONE +CONFIG.Coe_File string false no_coe_file_loaded +CONFIG.Collision_Warnings string false ALL +CONFIG.Component_Name string false BC_corr_mem +CONFIG.Disable_Collision_Warnings string false false +CONFIG.Disable_Out_of_Range_Warnings string false false +CONFIG.ECC string false false +CONFIG.EN_DEEPSLEEP_PIN string false false +CONFIG.EN_ECC_PIPE string false false +CONFIG.EN_SAFETY_CKT string false false +CONFIG.EN_SHUTDOWN_PIN string false false +CONFIG.EN_SLEEP_PIN string false false +CONFIG.Enable_32bit_Address string false false +CONFIG.Enable_A string false Always_Enabled +CONFIG.Enable_B string false Always_Enabled +CONFIG.Error_Injection_Type string false Single_Bit_Error_Injection +CONFIG.Fill_Remaining_Memory_Locations string false false +CONFIG.Interface_Type string false Native +CONFIG.Load_Init_File string false false +CONFIG.MEM_FILE string false no_mem_loaded +CONFIG.Memory_Type string false True_Dual_Port_RAM +CONFIG.Operating_Mode_A string false NO_CHANGE +CONFIG.Operating_Mode_B string false READ_FIRST +CONFIG.Output_Reset_Value_A string false 0 +CONFIG.Output_Reset_Value_B string false 0 +CONFIG.PRIM_type_to_Implement string false BRAM +CONFIG.Pipeline_Stages string false 0 +CONFIG.Port_A_Clock string false 100 +CONFIG.Port_A_Enable_Rate string false 100 +CONFIG.Port_A_Write_Rate string false 50 +CONFIG.Port_B_Clock string false 100 +CONFIG.Port_B_Enable_Rate string false 100 +CONFIG.Port_B_Write_Rate string false 50 +CONFIG.Primitive string false 8kx2 +CONFIG.RD_ADDR_CHNG_A string false false +CONFIG.RD_ADDR_CHNG_B string false false +CONFIG.READ_LATENCY_A string false 1 +CONFIG.READ_LATENCY_B string false 1 +CONFIG.RST.ARESETN.INSERT_VIP string false 0 +CONFIG.Read_Width_A string false 32 +CONFIG.Read_Width_B string false 32 +CONFIG.Register_PortA_Output_of_Memory_Core string false false +CONFIG.Register_PortA_Output_of_Memory_Primitives string false false +CONFIG.Register_PortB_Output_of_Memory_Core string false false +CONFIG.Register_PortB_Output_of_Memory_Primitives string false false +CONFIG.Remaining_Memory_Locations string false 0 +CONFIG.Reset_Memory_Latch_A string false false +CONFIG.Reset_Memory_Latch_B string false false +CONFIG.Reset_Priority_A string false CE +CONFIG.Reset_Priority_B string false CE +CONFIG.Reset_Type string false SYNC +CONFIG.Use_AXI_ID string false false +CONFIG.Use_Byte_Write_Enable string false false +CONFIG.Use_Error_Injection_Pins string false false +CONFIG.Use_REGCEA_Pin string false false +CONFIG.Use_REGCEB_Pin string false false +CONFIG.Use_RSTA_Pin string false false +CONFIG.Use_RSTB_Pin string false false +CONFIG.Write_Depth_A string false 4096 +CONFIG.Write_Width_A string false 32 +CONFIG.Write_Width_B string false 32 +CONFIG.ecctype string false No_ECC +CONFIG.register_porta_input_of_softecc string false false +CONFIG.register_portb_output_of_softecc string false false +CONFIG.softecc string false false +CONFIG.use_bram_block string false Stand_Alone +IPDEF string true xilinx.com:ip:blk_mem_gen:8.4 diff --git a/firmware/FT0/TCM_v1/make.tcl b/firmware/FT0/TCM_v1/make.tcl index 8af3eeb..f690d7a 100644 --- a/firmware/FT0/TCM_v1/make.tcl +++ b/firmware/FT0/TCM_v1/make.tcl @@ -128,6 +128,7 @@ set files [list \ [file normalize "${origin_dir}/../TCM/hdl/trigger_out.vhd" ]\ [file normalize "${origin_dir}/../TCM/hdl/tcm_side.vhd" ]\ [file normalize "${origin_dir}/../TCM/hdl/HDMIRX.vhd" ]\ + [file normalize "${origin_dir}/../TCM/hdl/BC_correlator.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_dualportram.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_build_arp.vhd" ]\ [file normalize "${origin_dir}/../../common/ipbus/hdl/ipbus_core/udp_txtransactor_if_simple.vhd" ]\ diff --git a/firmware/FT0/TCM_v1/xdc/timing.xdc b/firmware/FT0/TCM_v1/xdc/timing.xdc index d2cb676..47b6d4d 100644 --- a/firmware/FT0/TCM_v1/xdc/timing.xdc +++ b/firmware/FT0/TCM_v1/xdc/timing.xdc @@ -19,13 +19,13 @@ set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {Fi FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/RX_DATA_O_reg[*] FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/feedbackRegister_reg[*]}] 2 -#set_false_path -hold -from [get_clocks RXDataCLK] -to [get_pins {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D}] -#et_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_pins {FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D}] 1.000 +#set_false_path -hold -from [get_clocks RXDataCLK] -to [get_pins {FitGbtPrg/gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D}] +#et_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_pins {FitGbtPrg/gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D}] 1.000 set_max_delay -datapath_only -from [get_clocks CLKsys40] -to [get_pins readout_laser_out_ff0_reg/D] 3.000 -set_multicycle_path -setup -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]}}] 2 -set_multicycle_path -hold -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]}}] 1 +set_multicycle_path -setup -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]} V_str_reg}] 2 +set_multicycle_path -hold -from [get_clocks CLKA320] -to [get_cells {{C_vertex/T_?_reg} {Rd_word_reg[*]} V_str_reg}] 1 set_multicycle_path -setup -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks CLKA320] 2 @@ -33,9 +33,11 @@ set_multicycle_path -hold -from [get_cells {tcma/NC_reg[?][?]}] -to [get_clocks set_multicycle_path -setup -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 2 set_multicycle_path -hold -from [get_cells {tcmc/NC_reg[?][?]}] -to [get_clocks CLKC320] 1 -set_multicycle_path -setup -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg}] 2 -set_multicycle_path -hold -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg}] 1 +set_multicycle_path -setup -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg SC_str_reg CC_str_reg}] 2 +set_multicycle_path -hold -from [get_cells {{tcma/Ampl_o_reg[*]} {AmplC_reg[*]}}] -to [get_cells {C_FC/T_?_reg C_SC/T_?_reg {Rd_word_reg[*]} gbt_wr_reg SC_str_reg CC_str_reg}] 1 +set_multicycle_path -setup -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 2 +set_multicycle_path -hold -from [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* && NAME =~ "m_cr*/m0/*"}] -to [get_clocks CLKA320] 1 set_max_delay -datapath_only -from [get_clocks CLKC320] -to [get_clocks CLKA320] 3.000 diff --git a/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd b/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd index a6906d2..ec3bbe2 100644 --- a/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd +++ b/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd @@ -117,7 +117,7 @@ begin TRG_Orbit <= func_CNTPCKword_trgorbit(CNTPTFIFO_data_word_I); TRG_BC <= func_CNTPCKword_trgbc(CNTPTFIFO_data_word_I); TRG_Type <= func_CNTPCKword_trigger(CNTPTFIFO_data_word_I); - Link_ID <= x"00"; + Link_ID <= x"20"; System_ID <= x"00"; Memory_size <= x"0000";