diff --git a/firmware/FT0/PM/hdl/PM12_pkg.vhd b/firmware/FT0/PM/hdl/PM12_pkg.vhd new file mode 100644 index 0000000..6f0160d --- /dev/null +++ b/firmware/FT0/PM/hdl/PM12_pkg.vhd @@ -0,0 +1,9 @@ +library ieee; +use ieee.std_logic_1164.all; + + +package PM12_pkg is +type trig_time is array (0 to 11) of STD_LOGIC_VECTOR (9 downto 0); +type trig_ampl0 is array (0 to 11) of STD_LOGIC_VECTOR(12 downto 0); +type hyst_vector is array (0 to 11) of STD_LOGIC_VECTOR(25 downto 0); +end package; diff --git a/firmware/FT0/PM/hdl/autophase.vhd b/firmware/FT0/PM/hdl/autophase.vhd index 2a9b86c..86a5f45 100644 --- a/firmware/FT0/PM/hdl/autophase.vhd +++ b/firmware/FT0/PM/hdl/autophase.vhd @@ -77,16 +77,20 @@ if (lock_i='0') then ms_cou <=(others=>'0'); state <=(others=>'0'); j_cou <=(oth if (t1ms='1') then ms_cou <=(others=>'0'); j_cou <=(others=>'0'); case to_integer(unsigned(state)) is - when 0 => if (j_cou>=10) then state<="001"; dir<='1'; end if; - if (m0="100100") then state<="110"; dir<='1'; end if; + when 0 => if (j_cou>=10) then state<="001"; dir<='1'; + else + if (m0="100000") then state<="110"; dir<='1'; end if; + end if; when 1 => if (j_cou=0) then state<="010"; ml<= m0; end if; when 2 => if (m0=(ml+"000111")) then state<="011"; end if; - when 3 => if (j_cou>=10) then state<="100"; dir<='0'; end if; - if (m0="011100") then state<="110"; dir<='0'; end if; + when 3 => if (j_cou>=10) then state<="100"; dir<='0'; + else + if (m0="011111") then state<="111"; dir<='0'; end if; + end if; when 4 => if (j_cou=0) then state<="101"; ml<= mh0(5) & mh0(5 downto 1); end if; when 5 => if (m0=ml) then done_i<='1'; end if; - when 6 => if (m0=0) then state<="000"; dir<='0'; end if; - when others=> null; + when 6 => if (signed(m0)=10) then state<="000"; dir<='0'; end if; + when 7 => if (signed(m0)=-10) then state<="000"; end if; end case; else diff --git a/firmware/FT0/PM/hdl/fit.vhd b/firmware/FT0/PM/hdl/fit.vhd index 877d08c..4418710 100644 --- a/firmware/FT0/PM/hdl/fit.vhd +++ b/firmware/FT0/PM/hdl/fit.vhd @@ -20,11 +20,6 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; -package PM12_pkg is -type trig_time is array (0 to 11) of STD_LOGIC_VECTOR (9 downto 0); -type trig_ampl0 is array (0 to 11) of STD_LOGIC_VECTOR(12 downto 0); -end package; - library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; @@ -207,12 +202,11 @@ end fit; architecture RTL of fit is -attribute mark_debug : string; type data_vector is array (0 to 11) of STD_LOGIC_VECTOR (32 downto 0); type trig_ampl is array (0 to 11) of STD_LOGIC_VECTOR(10 downto 0); -signal RESET, lock320, lock300_1, lock300_2, lock300_3, sreset, rsti, SPI_CS, spi_rd, spi_rden, spi_lock320, spi_lock320_0, cnt_rst, cnt_rd, spi_wr_rdy, spi_wr0, spi_wr1, spi_wr2, spi_wr_req : STD_LOGIC; +signal RESET, lock320, lock300_1, lock300_2, lock300_3, sreset, rsti, SPI_CS, spi_rd, spi_rden, spi_lock320, spi_lock320_0, hspi_lock320, hspi_lock320_0, cnt_rst, cnt_rd, spi_wr_rdy, spi_wr0, spi_wr1, spi_wr2, spi_wr_req : STD_LOGIC; signal spi_lock_1, spi_lock0_1, spi_lock_2, spi_lock0_2, spi_lock_3, spi_lock0_3, rd_lock_spi, rd_lock_hspi, rd_lock, dcs_irq : STD_LOGIC; signal rstcount : STD_LOGIC_VECTOR (3 downto 0); signal irq_cnt : STD_LOGIC_VECTOR (1 downto 0); @@ -226,7 +220,7 @@ signal SPI_DATA, spi_wr_data, HSPI_DATA, hspi_wr_data, hspi_wr_data_l, reg_wr_da signal spi_addr, hspi_addr, reg_wr_addr : STD_LOGIC_VECTOR (8 downto 0); signal spi_bit_count, hspi_bit_count : STD_LOGIC_VECTOR (4 downto 0); signal gate_time_low, gate_time_high : STD_LOGIC_VECTOR (7 downto 0); -signal reg32_wr, reg32_wr0, reg32_wr1, reg32_wr2, reg32_rd, reg32_rd0, reg32_rd1, reg32_rd2, reg32_str : STD_LOGIC; +signal reg32_wr, reg32_wr0, reg32_wr1, reg32_wr2, reg32_rd, reg32_rd0, reg32_rd1, reg32_rd2, reg32_str, reg32_str0, reg32_str1, reg32_str2, str_reg32, reg32_320_wr, reg32_320_wr0, reg32_320_wr1, reg32_320_wr2, reg32_320_str, reg32_320_str0, reg32_320_str1, reg32_320_str2 : STD_LOGIC; signal CH1A_shift, CH1B_shift, CH1C_shift, CH1D_shift, CH2A_shift, CH2B_shift, CH2C_shift, CH2D_shift, CH3A_shift, CH3B_shift, CH3C_shift, CH3D_shift : STD_LOGIC_VECTOR (11 downto 0); signal CH1_0_zero, CH1_1_zero, CH2_0_zero, CH2_1_zero, CH3_0_zero, CH3_1_zero, CH4_0_zero, CH4_1_zero, CH5_0_zero, CH5_1_zero, CH6_0_zero, CH6_1_zero, CH7_0_zero, CH7_1_zero, CH8_0_zero, CH8_1_zero, CH9_0_zero, CH9_1_zero, CH10_0_zero, CH10_1_zero, CH11_0_zero, CH11_1_zero, CH12_0_zero, CH12_1_zero : STD_LOGIC_VECTOR (11 downto 0); signal CH1_0_rg, CH1_1_rg, CH2_0_rg, CH2_1_rg, CH3_0_rg, CH3_1_rg, CH4_0_rg, CH4_1_rg, CH5_0_rg, CH5_1_rg, CH6_0_rg, CH6_1_rg, CH7_0_rg, CH7_1_rg, CH8_0_rg, CH8_1_rg, CH9_0_rg, CH9_1_rg, CH10_0_rg, CH10_1_rg, CH11_0_rg, CH11_1_rg, CH12_0_rg, CH12_1_rg : STD_LOGIC_VECTOR (12 downto 0); @@ -248,7 +242,7 @@ signal BCOLD1, BCOLD2, BCOLD3 : STD_LOGIC_VECTOR (1 downto 0); signal BC_PER1, BC_PER2, BC_PER3 : STD_LOGIC_VECTOR (6 downto 0); signal BC_JUMP1, BC_JUMP2, BC_JUMP3, ALM_CLR, almclr10, almclr11, alm_clr1, almclr20, almclr21, alm_clr2, almclr30, almclr31, alm_clr3, IRQI : STD_LOGIC; -signal HBC_JUMP1, HBC_JUMP2, HBC_JUMP3, hclr10, hclr11, h_clr1, hclr20, hclr21, h_clr2, hclr30, hclr31, h_clr3, Hs_rd, HGBTRXerr, hstat_clr, hstat_clr0, hstat_clr1 : STD_LOGIC; +signal HBC_JUMP1, HBC_JUMP2, HBC_JUMP3, hclr10, hclr11, h_clr1, hclr20, hclr21, h_clr2, hclr30, hclr31, h_clr3, Hs_rd, HGBTRXerr, hstat_clr, hstat_clr0, hstat_clr1, Hs_clr : STD_LOGIC; signal TDC_COU1, TDC_COU2, TDC_COU3 : STD_LOGIC_VECTOR (3 downto 0); @@ -277,7 +271,7 @@ signal tt,ta,tto,tao : STD_LOGIC_VECTOR (1 downto 0); signal GBT_is_RXD, GBT_is_TXD, RX_CLK, TX_CLK, GBTRX_ready, GBTRX_ready0, GBT_chg, HGBT_chg, GBT_rdy, GBT_rdy0, t100ms, RX_err, RX_err1, RX_err_LED, rxerr0, TXact, RXact, RXLED, TXLED, txled0, rxled0, LNKLED, IsRXData0, GBTRXerr, stat_clr, stat_clr0, stat_clr1 : STD_LOGIC; signal cou_100ms : STD_LOGIC_VECTOR (21 downto 0); -signal alm_rst0, alm_rst, chans_block : STD_LOGIC; +signal alm_rst0, alm_rst, chans_block, is_rst : STD_LOGIC; signal chans_ena, chans_ena_r : STD_LOGIC_VECTOR (11 downto 0); @@ -287,7 +281,7 @@ signal N1_chans, N2_chans : STD_LOGIC_VECTOR (2 downto 0); signal TT_mode : STD_LOGIC; signal ampl_sat : STD_LOGIC_VECTOR (11 downto 0); -signal Event_in, DATA_rd, DATA_rdy, inp_cou, CH_trig, CH_triga, CH_do, Z_alarm, trig_bgnd : STD_LOGIC_VECTOR (11 downto 0); +signal Event_in, DATA_rd, DATA_rdy, inp_cou, CH_trig, CH_triga, CH_do, Z_alarm, trig_bgnd, cnt_trig : STD_LOGIC_VECTOR (11 downto 0); signal inp_event, EV_ID_wr, EV_ID_rd, EV_ID_empty, Event_ready, Event_ready_0, Event_free, wr_out_id, New_BCID, DATA80_rd, DATA_empty, FIFO_dis, wr_nch, ev_tout, ev_tout0 : STD_LOGIC; signal ev_tout_cnt : STD_LOGIC_VECTOR (7 downto 0); @@ -300,7 +294,7 @@ signal xadc_a: STD_LOGIC_VECTOR (6 downto 0); signal EV_ID_in, EV_ID_out : STD_LOGIC_VECTOR (55 downto 0); signal EV_DATA80, DATA80_in : STD_LOGIC_VECTOR (79 downto 0); --signal mux_out, str_la : STD_LOGIC; -signal WR_fifo_out, wr_hspi32, rd_hspi32, flsh_sel, TCM_req, TCM_reqh, TCM_req0, TCM_req1, TCM_req2, fl_rst, rd_xadc, xadc_rq0, xadc_rq1, xadc_rq2, xadc_en, xadc_rdy, gs0, gs1 : STD_LOGIC; +signal WR_fifo_out, wr_hspi32, rd_hspi32, flsh_sel, TCM_req, TCM_reqh, TCM_req0, TCM_req1, TCM_req2, fl_rst, rd_xadc, xadc_en, xadc_rdy, gs0, gs1, rdo_sel : STD_LOGIC; signal DATA_out : data_vector; @@ -311,7 +305,16 @@ signal cnt_out, hcnt_out : STD_LOGIC_VECTOR (15 downto 0); signal psen1, psincdec1, jumpa1, flock1, fdone1, psen2, psincdec2, jumpa2, flock2, fdone2, psen3, psincdec3, jumpa3, flock3, fdone3, all_locked : STD_LOGIC; signal pshift1, pshift2, pshift3 : STD_LOGIC_VECTOR (5 downto 0); -signal rx_phase_status : std_logic_vector(3 downto 0); +signal rx_phase_status : std_logic_vector(3 downto 0); + +signal hyst_md : std_logic_vector(15 downto 0); +signal start_hyst, h_busy, wr_hyst_a, rd_hyst_d, hysta_sel, hystd_sel, hyst_stp : std_logic; +signal cnt_md : std_logic := '0'; +signal hyst_data : hyst_vector; +signal hyst_a, hyst_t : std_logic_vector(11 downto 0); +signal hyst_addr : std_logic_vector(16 downto 0); +signal hyst_r_data : std_logic_vector(31 downto 0); + component PLL320 port ( mclk_in : in std_logic; @@ -425,9 +428,7 @@ component TDCCHAN is -- ############################################### signal FIT_GBT_status : FIT_GBT_status_type; signal FIT_GBT_control : CONTROL_REGISTER_type; - -attribute mark_debug of FIT_GBT_control : signal is "true"; -attribute mark_debug of FIT_GBT_status : signal is "true"; + signal Data_from_FITrd : std_logic_vector(GBT_data_word_bitdepth-1 downto 0); signal IsData_from_FITrd : STD_LOGIC; @@ -587,7 +588,26 @@ Port ( clk : in STD_LOGIC; done : out STD_LOGIC; shift : out STD_LOGIC_VECTOR (5 downto 0) ); -END COMPONENT; +END COMPONENT; + +component hyst + Port ( + clk320 : in std_logic; + hyst_inp_data : in hyst_vector; + hyst_a : in std_logic_vector(11 downto 0); + hyst_t : in std_logic_vector(11 downto 0); + hyst_st : in std_logic; + cnt_clr : in std_logic; + busy : out std_logic; + hyst_addr_i : in std_logic_vector(16 downto 0); + hyst_addr_o : out std_logic_vector(16 downto 0); + wr_addr : in std_logic; + hyst_data_o : out std_logic_vector(31 downto 0); + n_addr : in std_logic; + lock320 : in std_logic; + stp : out std_logic + ); +end component; begin @@ -861,7 +881,7 @@ IMGTCLK1: IBUFDS_GTE2 port map (O => MGTCLK, I => MGTCLK_P, IB => MGTCLK_N, CEB=>'0'); fl_upg: FLASH generic map (clk_freq => 40000 ) - port map (rst=>fl_rst, clk => TX_CLK, data_in =>hspid_w32, data_out =>hspid_r32, A =>hspi_addr(1 downto 0), wr_flshreg =>wr_hspi32, rd_flshreg =>rd_hspi32, flshreg_sel=>flsh_sel, FSEL =>FSEL, FMOSI =>FMOSI, FMISO =>FMISO); + port map (rst=>fl_rst, clk => TX_CLK, data_in =>hspid_w32, data_out =>hspid_r32, A =>hspi_addr(1 downto 0), wr_flshreg =>wr_hspi32, rd_flshreg =>str_reg32, flshreg_sel=>flsh_sel, FSEL =>FSEL, FMOSI =>FMOSI, FMISO =>FMISO); IRQI<= BC_JUMP1 or BC_JUMP2 or BC_JUMP3 or GBTRXerr or GBT_chg or dcs_irq when (irq_cnt="11") else '0'; @@ -957,7 +977,10 @@ begin else gbt_global_status(2) <= '1'; end if; + if (cnt_md='0') then cnt_trig<= CH_trig; else cnt_trig<= CH_triga; end if; + end if; + end process; --gbt_global_status <= x"0"; @@ -976,8 +999,6 @@ process (TX_CLK) begin if (TX_CLK'event and TX_CLK='1') then -xadc_rq2 <=xadc_rq1; xadc_rq1<= xadc_rq0; xadc_rq0 <=rd_xadc; - if (xadc_rdy='1') then xadc_r<=xadc_out; end if; fl_rst <=sreset; @@ -1000,7 +1021,6 @@ hstat_clr0<=Hs_rd; hstat_clr1<=hstat_clr0; hstat_clr<=hstat_clr1; if (hstat_clr1='1') and (hstat_clr='0') then HGBT_chg<='0'; end if; end if; - if (GBTRX_ready='1') and (GBT_rdy='1') and (RX_err='1') then GBTRXerr<='1'; HGBTRXerr<='1'; else if (stat_clr1='1') and (stat_clr='0') then GBTRXerr<='0'; end if; @@ -1124,8 +1144,8 @@ CHANNEL2C : channel port map (CGE =>CGE7, clk320 =>clk320, reset =>sreset, tdc_r gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH7_0_zero, CH1_zero =>CH7_1_zero, CH_trig_outt =>CH_trig(6), CH_trig_outa =>CH_triga(6), CH_trig_bgnd=> trig_bgnd(6), CH_TIME =>CH_TIME_T(6), CH_ampl =>CH_ampl0(6), DATA_out=>DATA_out(6), DATA_ready=>DATA_rdy(6), DATA_rd=>DATA_rd(6), FIFO_dis=>FIFO_dis, Event_in=>Event_in(6), Z0_cal=>CH7_Z0, Z1_cal=>CH7_Z1, Z_alarm=>Z_alarm(6), spi_lock=>spi_lock320, R0_cal=>CH7_0_rg, R1_cal=>CH7_1_rg, R0_corr=>CH7_0_rc, R1_corr=>CH7_1_rc, pulse_in=>inp_cou(6), chan_ena=>chans_ena(6)); - -CHANNEL2D : channel port map (CGE =>CGE8, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC2D_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC2D, CSTR =>CSTR8, CH =>CH8, CH_shift => CH2D_shift, + CHANNEL2D : channel port map (CGE =>CGE8, clk320 =>clk320, reset =>sreset, tdc_rdy_in=> TDC2D_rdy0, mt_cou =>mt_cou, bc_cou =>BC_COU(5 downto 0), TR_bc =>TR_to, TDC =>TDC2D, CSTR =>CSTR8, CH =>CH8, CH_shift => CH2D_shift, + gate_time_low => gate_time_low, gate_time_high =>gate_time_high, Ampl_sat =>Ampl_sat, CH0_zero =>CH8_0_zero, CH1_zero =>CH8_1_zero, CH_trig_outt =>CH_trig(7), CH_trig_outa =>CH_triga(7), CH_trig_bgnd=> trig_bgnd(7), CH_TIME =>CH_TIME_T(7), CH_ampl =>CH_ampl0(7), DATA_out=>DATA_out(7), DATA_ready=>DATA_rdy(7), DATA_rd=>DATA_rd(7), FIFO_dis=>FIFO_dis, Event_in=>Event_in(7), Z0_cal=>CH8_Z0, Z1_cal=>CH8_Z1, Z_alarm=>Z_alarm(7), spi_lock=>spi_lock320, R0_cal=>CH8_0_rg, R1_cal=>CH8_1_rg, R0_corr=>CH8_0_rc, R1_corr=>CH8_1_rc, pulse_in=>inp_cou(7), chan_ena=>chans_ena(7)); @@ -1162,8 +1182,7 @@ EV_ID_rd<= '1' when (EV_ID_empty='0') and ((Event_free='1') or ((Event_ready='1' --DATA80_rd<= not DATA_empty; - -count1: counters port map (clk=>clk320, evnt=>inp_cou, trig=>CH_trig, reset=>cnt_rst, dout=>cnt_out, hdout=>hcnt_out, raddr=>spi_addr(5 downto 0), hraddr=>hspi_addr(4 downto 0), hl=>hspi_h, rd_en=>cnt_rd, hrd_en=>hcnt_rd); +count1: counters port map (clk=>clk320, evnt=>inp_cou, trig=>cnt_trig, reset=>cnt_rst, dout=>cnt_out, hdout=>hcnt_out, raddr=>spi_addr(5 downto 0), hraddr=>hspi_addr(4 downto 0), hl=>hspi_h, rd_en=>cnt_rd, hrd_en=>hcnt_rd); @@ -1185,16 +1204,19 @@ end process; alm_rst<=not sreset and alm_rst0; rd_lock_hspi <= '1' when (hspi_bit_count(3 downto 0)=x"F") and (hspi_rd='1') and (hspi_addr(8)='0') else '0'; -Hs_rd <= '1' when (hspi_bit_count="10000") and (hspi_rd='1') and (hspi_addr='0' & x"80") else alm_rst; -reg32_str <= '1' when ((hspi_bit_count="01010") or (hspi_bit_count="10000")) and (hspi_rd='1') and (hspi_addr(8)='0') else '0'; -rd_xadc <= reg32_str when (hspi_addr(7 downto 2) = "111111") and (hspi_addr(1 downto 0) /= "11") else '0'; -reg32_rd <=reg32_str when (hspi_addr(7 downto 3)>="11101") and (hspi_addr(7 downto 2)<"111111") else '0'; +Hs_rd <= alm_rst or Hs_clr; + flsh_sel<='1' when (hspi_addr(7 downto 2)="111110") else '0'; +rdo_sel<= '1' when (hspi_addr>=16#E8#) and (hspi_addr<=16#F4#) else '0'; +rd_xadc <='1' when (hspi_addr>=16#FC#) and (hspi_addr<=16#FE#) else '0'; +hysta_sel <='1' when (hspi_addr=16#F5#) else '0'; +hystd_sel <='1' when (hspi_addr=16#F6#) else '0'; process (HSCKI, HSELI, RESET) begin -if (HSELI='0') then hspi_bit_count<="00000"; hcnt_rd<='0'; hspibuf_wr<='0'; hspibuf_rd<='0'; hspi_na<='0'; reg32_wr<='0'; +if (HSELI='0') then hspi_bit_count<="00000"; hcnt_rd<='0'; hspibuf_wr<='0'; hspibuf_rd<='0'; hspi_na<='0'; reg32_wr<='0'; Hs_clr <='0'; reg32_rd <= '0'; reg32_str<= '0'; else + if (HSCKI'event and HSCKI='0') then if (hspi_bit_count="11111") then hspi_bit_count<="10000"; hspi_na<='1'; @@ -1203,8 +1225,8 @@ if (HSCKI'event and HSCKI='0') then else hspi_wr_data_l<=HSPI_DATA(14 downto 0) & HMOSII; end if; if (hspi_addr(7)='0') then hspi_wr_rdy<='1'; end if; - if (hspi_addr(7 downto 6)="10") then hspibuf_wr<='1'; end if; - if (hspi_addr(7 downto 3)>="11011") and (hspi_h='1') then reg32_wr<='1'; end if; + if (hspi_addr(7 downto 6)="10") and (hspi_addr(5 downto 2)/="1111") then hspibuf_wr<='1'; end if; + if (hspi_addr(7 downto 3)>="11011") and (hspi_h='1') then reg32_wr<='1'; end if; end if; else @@ -1216,8 +1238,13 @@ if (HSCKI'event and HSCKI='0') then if (hspi_addr(7 downto 4)="11011") then hspi_h<= not hspi_h; end if; end if; - end if; + + if ((hspi_bit_count="01010") or ((hspi_bit_count="10001") and (hspi_h='0'))) and (hspi_rd='1') then reg32_rd <= '1'; else reg32_rd <= '0'; end if; + + if (hspi_bit_count="10001") and (hspi_h='1') and (hspi_rd='1') then reg32_str<= '1'; else reg32_str<= '0'; end if; + if (hspi_bit_count="10001") and (hspi_rd='1') and (hspi_addr=16#80#) then Hs_clr <='1'; else Hs_clr <='0'; end if; + if (hspi_bit_count="00000") then hspi_rd <= HMOSII; end if; if (hspi_bit_count="01001") then hspi_addr <= HSPI_DATA(7 downto 0) & HMOSII; hspi_h<='0'; end if; if (hspi_bit_count="01110") and (hspi_rd='1') and (hspi_addr(7 downto 0)=x"C0") then hcnt_rd<='1'; end if; @@ -1228,8 +1255,8 @@ if (HSCKI'event and HSCKI='0') then hspibuf_rd<='0'; if (hspi_addr(7 downto 4)>=x"C") then hspi_h<= not hspi_h; end if; - if (hspi_addr(7 downto 4)="11101") and (hspi_h='1') then HSPI_DATA<=hspi_32l; + if ((hspi_addr(7 downto 4)="11011") and (hspi_h='1') then HSPI_DATA<=hspi_32l; else @@ -1368,17 +1395,21 @@ if (HSCKI'event and HSCKI='0') then when 16#7C# => HSPI_DATA<=x"0" & chans_ena_r; when 16#7D# => HSPI_DATA<=x"0" & Z_alarm; - - when 16#7F# => HSPI_DATA<= gbt_global_status & "000" & HBC_JUMP3 & HBC_JUMP2 & HBC_JUMP1 & HGBTRXerr & GBTRX_ready & lock300_3 & lock300_2 & lock300_1 & lock320; + when 16#7E# => HSPI_DATA<= hyst_md; + when 16#7F# => HSPI_DATA<= gbt_global_status & is_rst & cnt_md & h_busy & HBC_JUMP3 & HBC_JUMP2 & HBC_JUMP1 & HGBTRXerr & GBTRX_ready & lock300_3 & lock300_2 & lock300_1 & lock320; when 16#80# to 16#BF# => HSPI_DATA<=hspi_buf_out; when 16#C0# to 16#D7# => HSPI_DATA<=hcnt_out; -- gbt status ipbus_control_reg - when 16#D8# to 16#e7# => if (hspi_h='0') then HSPI_DATA<=ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)(31 downto 16); - else HSPI_DATA<=ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)(15 downto 0); end if; + when 16#D8# to 16#e7# => HSPI_DATA <=ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)(31 downto 16); + hspi_32l <=ipbus_control_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#D8#)(15 downto 0); - when 16#E8# to 16#F6# => HSPI_DATA<=hspib_32(31 downto 16); hspi_32l <=hspib_32(15 downto 0); + when 16#E8# to 16#F4# => HSPI_DATA<=hspib_32(31 downto 16); hspi_32l <=hspib_32(15 downto 0); + + when 16#F5# => HSPI_DATA<= x"000" & "000" & hyst_addr(16); hspi_32l <=hyst_addr(15 downto 0); + + when 16#F6# => HSPI_DATA<= hyst_r_data(31 downto 16); hspi_32l <=hyst_r_data(15 downto 0); when 16#F7# => HSPI_DATA<=mcu_tstamp(31 downto 16); hspi_32l <=mcu_tstamp(15 downto 0); @@ -1401,12 +1432,24 @@ end if; end if; end process; +h0: hyst Port map(clk320 =>clk320, hyst_inp_data =>hyst_data, hyst_a =>hyst_a, hyst_t =>hyst_t, hyst_st =>start_hyst, cnt_clr =>cnt_rst, busy =>h_busy, hyst_addr_i =>hspid_w32(16 downto 0), hyst_addr_o =>hyst_addr, + wr_addr =>wr_hyst_a, hyst_data_o =>hyst_r_data, n_addr =>rd_hyst_d, lock320 =>hspi_lock320, stp=> hyst_stp); + +wr_hyst_a <= reg32_320_wr and hysta_sel; rd_hyst_d<= reg32_320_str and hystd_sel; + +h1: for i in 0 to 11 generate + hyst_data(i) <= DATA_out(i)(25 downto 0); + hyst_a(i) <= EV_ID_out(i) and DATA_out(i)(28); + hyst_t(i) <= EV_ID_out(i) and not (DATA_out(i)(27) or DATA_out(i)(32)); + end generate; + + UA2 : USR_ACCESSE2 port map (CFGCLK => open, DATA => tstamp, DATAVALID => open ); SNS : SENSOR PORT MAP ( di_in => (others=>'0'), daddr_in => xadc_a, den_in => xadc_en, dwe_in => '0', drdy_out => xadc_rdy, do_out => xadc_out, dclk_in => TX_CLK, reset_in => sreset, vp_in => '0', vn_in => '0', channel_out => open, eoc_out => open, alarm_out => open, eos_out => open, busy_out => open); -xadc_a<="00000" & hspi_addr(1 downto 0); xadc_en <= xadc_rq1 and not xadc_rq2; +xadc_a<="00000" & hspi_addr(1 downto 0); xadc_en <= rd_hspi32 and rd_xadc; TCM_reqh <= HBC_JUMP3 or HBC_JUMP2 or HBC_JUMP1 or HGBTRXerr or HGBT_chg; @@ -1598,6 +1641,7 @@ hspid_w32 <= hspi_wr_data & hspi_wr_data_l; wr_hspi32 <= '1' when (reg32_wr2='0') and (reg32_wr1='1') else '0'; rd_hspi32 <= '1' when (reg32_rd2='0') and (reg32_rd1='1') else '0'; +str_reg32 <= '1' when (reg32_str2='0') and (reg32_str1='1') else '0'; reg_wr_data<= spi_wr_data when (spi_wr_req='1') else hspi_wr_data; reg_wr_addr<= spi_addr when (spi_wr_req='1') else hspi_addr; @@ -1608,7 +1652,7 @@ if sreset='1' then buf_vector<=x"000000000000000"; buf_cou<=x"A0"; dcs_irq<='0'; else if (TX_CLK'event and TX_CLK='1') then -reg32_wr2<=reg32_wr1; reg32_wr1<=reg32_wr0; reg32_wr0<=reg32_wr; reg32_rd2<=reg32_rd1; reg32_rd1<=reg32_rd0; reg32_rd0<=reg32_rd; +reg32_wr2<=reg32_wr1; reg32_wr1<=reg32_wr0; reg32_wr0<=reg32_wr; reg32_rd2<=reg32_rd1; reg32_rd1<=reg32_rd0; reg32_rd0<=reg32_rd; reg32_str2<=reg32_str1; reg32_str1<=reg32_str0; reg32_str0<=reg32_str; spibuf_wr2<=spibuf_wr1; spibuf_wr1<=spibuf_wr0; spibuf_wr0<=spibuf_wr; hspibuf_wr2<=hspibuf_wr1; hspibuf_wr1<=hspibuf_wr0; hspibuf_wr0<=hspibuf_wr; spibuf_rd2<=spibuf_rd1; spibuf_rd1<=spibuf_rd0; spibuf_rd0<=spibuf_rd; hspibuf_rd2<=hspibuf_rd1; hspibuf_rd1<=hspibuf_rd0; hspibuf_rd0<=hspibuf_rd; @@ -1617,8 +1661,8 @@ buf_lock2<=buf_lock1; buf_lock1<=buf_lock0; buf_lock0<=buf_lock; hbuf_req <= (not hspibuf_wr2) and hspibuf_wr1 and sbuf_wrena; if (rd_hspi32='1') then - if (flsh_sel='0') then hspib_32 <=ipbus_status_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#E8#); - else hspib_32 <=hspid_r32; + if (rdo_sel='1') then hspib_32 <=ipbus_status_reg(to_integer(unsigned(hspi_addr(7 downto 0)))-16#E8#); + else if (flsh_sel='1') then hspib_32 <=hspid_r32; end if; end if; end if; @@ -1662,10 +1706,14 @@ Xmegamem : Xmega_buf PORT MAP (clka => TX_CLK, ena => hbuf_ena, wea(0) => hbuf_w tcm_req <= ((not tcm_req2) and tcm_req1) or ((not gs0) and gbt_global_status(0)) or ((not gs1) and gbt_global_status(1)); +reg32_320_wr<= reg32_320_wr1 and (not reg32_320_wr2); reg32_320_str<= reg32_320_str1 and (not reg32_320_str2); + process(clk320) begin if (clk320'event and clk320='1') then +reg32_320_wr2 <=reg32_320_wr1; reg32_320_wr1 <=reg32_320_wr0; reg32_320_wr0 <=reg32_wr; reg32_320_str2 <=reg32_320_str1; reg32_320_str1 <=reg32_320_str0; reg32_320_str0 <=reg32_str; + gs0<=gbt_global_status(0); gs1<=gbt_global_status(1); spi_wr2<=spi_wr1; spi_wr1<=spi_wr0; spi_wr0<=spi_wr_rdy; hspi_wr2<=hspi_wr1; hspi_wr1<=hspi_wr0; hspi_wr0<=hspi_wr_rdy; @@ -1677,7 +1725,7 @@ if (hspi_wr2='0') and (hspi_wr1='1') then hspi_wr_req<='1'; end if; if (cnt_rst='1') then cnt_rst<='0'; end if; - if (sreset='1') then chans_block <= '0'; + if (sreset='1') then chans_block <= '0'; hyst_md(15)<='0'; is_rst<='1'; else if (spi_wr_req='1') or (hspi_wr_req='1') then case reg_wr_addr(7 downto 0) is @@ -1723,8 +1771,12 @@ if (cnt_rst='1') then cnt_rst<='0'; end if; when x"3D" => Ampl_sat <=reg_wr_data(11 downto 0); when x"7C" => chans_ena_r <=reg_wr_data(11 downto 0); + + when x"7E" => hyst_md(14 downto 0) <=reg_wr_data(14 downto 0); when x"7F" => if (cnt_rst='0') and (reg_wr_data(9)='1') then cnt_rst<='1'; end if; + if (hspi_wr_req='1') and (spi_wr_req='0') then cnt_md <= reg_wr_data(10); end if; + if (hspi_wr_req='1') and (spi_wr_req='0') and (reg_wr_data(11)='1') then is_rst <= '0'; end if; if (spi_wr_req='1') and (reg_wr_data(11)='1') then chans_block <= '1'; end if; when others => null; @@ -1733,6 +1785,10 @@ if (cnt_rst='1') then cnt_rst<='0'; end if; if (hspi_wr_req='1') and (spi_wr_req='0') then hspi_wr_req<='0'; end if; end if; + if ((spi_wr_req='1') or (hspi_wr_req='1')) and (reg_wr_addr(7 downto 0)=x"7E") then hyst_md(15) <=reg_wr_data(15); + else + if (hyst_stp='1') then hyst_md(15)<='0'; end if; + end if; end if; end if; end process; @@ -1855,7 +1911,7 @@ begin if (clk320'event and clk320='1') then spi_lock320<=spi_lock320_0; spi_lock320_0<= rd_lock; - +hspi_lock320<=hspi_lock320_0; hspi_lock320_0<= rd_lock_hspi; tto<=tt; tao<=ta; MCLK40_0<=MCLK40T; MCLK40_1<=MCLK40_0; if (MCLK40_0/=MCLK40_1) then mt_cou<="000"; else mt_cou<=mt_cou+1; end if; @@ -1939,6 +1995,10 @@ if (mt_cou="001") then if (BC_COU>x"003") then TR_to<=BC_COU(5 downto 0)-"000100"; else TR_to<="1010" & BC_COU(1 downto 0); end if; end if; end if; + + if ((EV_ID_out(23 downto 12) = hyst_md(11 downto 0)) or (hyst_md(12)='0') ) and (hyst_md(15)='1') then start_hyst<= Event_ready_0 and (not Event_ready); else start_hyst<= '0'; end if; + + end if; end process; @@ -2026,22 +2086,6 @@ end generate; FIFO_dis<=EV_ID_empty and EVENT_free; wr_out_id<= (Event_ready_0 and (not Event_ready)) or ev_tout; ---process (TX_CLK) ---begin ---if (TX_CLK'event and TX_CLK='1') then - --- if (DATA_empty='0') then mux_out<= not mux_out; else mux_out<='1'; end if; --- str_la<=(not DATA_empty) or (not mux_out); - ---end if; ---end process; - ---la0i <= DATA80_out(15 downto 0) when (mux_out='0') else DATA80_out(55 downto 40); ---la1i <= DATA80_out(31 downto 16) when (mux_out='0') else DATA80_out(71 downto 56); ---la2i(8 downto 0) <= '0' & DATA80_out(39 downto 32) when (mux_out='0') else '1' & DATA80_out(79 downto 72); - - - --la2i(0)<=EVNTI; la2i(1)<=Zcal_done; la2i(2)<=inp_cou(1); la2i(3)<=CSTR2; la2i(4)<=inp_cou(2); la2i(5)<=CSTR3; la2i(6)<=inp_cou(3); la2i(7)<=CSTR4; la2i(8)<=inp_cou(4); la2i(9)<=CSTR5; la2i(10)<=inp_cou(5); la2i(11)<=CSTR6; --la2i(12)<=inp_cou(6); la2i(13)<=CSTR7; la2i(14)<=inp_cou(7); la2i(15)<=CSTR8; lack2i<=inp_cou(8); lack3i<=CSTR9; la3i(14)<=inp_cou(9); la3i(15)<=CSTR10; la3i(12)<=inp_cou(10); la3i(13)<=CSTR11; la3i(10)<=inp_cou(11); la3i(11)<=CSTR12; @@ -2053,13 +2097,13 @@ wr_out_id<= (Event_ready_0 and (not Event_ready)) or ev_tout; --la0i(0)<=MCLK40_IN1; la0i(1)<=MCLK40_IN2; la0i(2)<=MCLK40_IN3; la0i(3)<=CSTR1; la0i(4)<=CGE1; la0i(5)<=lTDCCLK1; la0i(6)<=RSA1; --la3i(15)<=inp_event; ---la0i<=LA_vector(15 downto 0); la1i<=LA_vector(31 downto 16); la2i<=LA_vector(47 downto 32); la3i(7 downto 0)<=LA_vector(55 downto 48); + --la1i(15 downto 14) <= ttla; --la2i(15 downto 14) <= tala; ---la2i(0)<=HSELI; la2i(1)<=HSCKI; la2i(2)<=HMOSII; la2i(3)<=HMISOI; la2i(4)<=hspi_h; la2i(5)<=dcs_irq; la2i(6)<=hbuf_ena; la2i(7)<=hbuf_wrena; la2i(8)<=reg32_wr; +--la2i(0)<=HSELI; la2i(1)<=HSCKI; la2i(2)<=HMOSII; la2i(3)<=HMISOI; la2i(4)<=hspi_h; la2i(5)<=rd_hyst_d0; la2i(6)<=hbuf_ena; la2i(7)<=hbuf_wrena; la2i(8)<=reg32_wr; --la3i(0)<=gs0; la3i(1)<=gs1; diff --git a/firmware/FT0/PM/hdl/hyst.vhd b/firmware/FT0/PM/hdl/hyst.vhd new file mode 100644 index 0000000..781d935 --- /dev/null +++ b/firmware/FT0/PM/hdl/hyst.vhd @@ -0,0 +1,214 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01/22/2021 07:40:08 PM +-- Design Name: +-- Module Name: hyst - RTL +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +library work; +use work.PM12_pkg.all; + + +entity hyst is + Port ( + clk320 : in std_logic; + hyst_inp_data : in hyst_vector; + hyst_a : in std_logic_vector(11 downto 0); + hyst_t : in std_logic_vector(11 downto 0); + hyst_st : in std_logic; + cnt_clr : in std_logic; + busy : out std_logic; + hyst_addr_i : in std_logic_vector(16 downto 0); + hyst_addr_o : out std_logic_vector(16 downto 0); + wr_addr : in std_logic; + hyst_data_o : out std_logic_vector(31 downto 0); + n_addr : in std_logic; + lock320 : in std_logic; + stp : out std_logic + ); +end hyst; + +architecture RTL of hyst is + +type data1_vect is array (0 to 11) of STD_LOGIC_VECTOR (0 downto 0); +type data9_vect is array (0 to 11) of STD_LOGIC_VECTOR (8 downto 0); +type data13_vect is array (0 to 11) of STD_LOGIC_VECTOR (12 downto 0); +type data16_vect is array (0 to 11) of STD_LOGIC_VECTOR (15 downto 0); +type data32_vect is array (0 to 11) of STD_LOGIC_VECTOR (31 downto 0); + +signal wr_mem_t, wr_mem_a, wr_mem_an : data1_vect; +signal t_in, t_out, a_in, a_out, an_in, an_out : data16_vect; +signal loc_addr : std_logic_vector (16 downto 0); +signal t_rd, a_rd, an_rd : data32_vect; +signal ampln_addr : data9_vect; +signal ampl_addr : data13_vect; +signal clr, lock : std_logic; +signal wr_b : std_logic_vector (0 downto 0); +signal hyst_a0, hyst_a1, hyst_a2, hyst_t0, hyst_t1, hyst_t2, ovf : std_logic_vector (11 downto 0); +signal hyst_data : hyst_vector; + +COMPONENT hyst_mem4k + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + clkb : IN STD_LOGIC; + regceb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT hyst_mem8k + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + clkb : IN STD_LOGIC; + regceb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT hyst_mem512 + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + clkb : IN STD_LOGIC; + regceb : IN STD_LOGIC; + web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +begin + +busy<= clr; hyst_addr_o <= loc_addr; lock<= not lock320; + +hyst_data_o<= a_rd(to_integer(unsigned(loc_addr(16 downto 13)))) when (loc_addr(12) = '0') else + t_rd(to_integer(unsigned(loc_addr(16 downto 13)))) when (loc_addr(12 downto 11) = "10") else + an_rd(to_integer(unsigned(loc_addr(16 downto 13)))); + + stp<='1' when (ovf/=0) else '0'; + +mem: for i in 0 to 11 generate + +mem4k: hyst_mem4k port map (clka =>clk320, wea=>wr_mem_t(i), addra => hyst_data(i)(11 downto 0), dina =>t_in(i), douta => t_out(i), clkb =>clk320, regceb =>lock, web =>wr_b, addrb=> loc_addr(10 downto 0), dinb=> (others=>'0'), doutb => t_rd(i)); +mem8k: hyst_mem8k port map (clka =>clk320, wea=>wr_mem_a(i), addra => ampl_addr(i), dina =>a_in(i), douta => a_out(i), clkb =>clk320, regceb =>lock, web => wr_b, addrb=> loc_addr(11 downto 0), dinb=> (others=>'0'), doutb => a_rd(i)); +mem512: hyst_mem512 port map (clka =>clk320, wea=>wr_mem_an(i), addra => ampln_addr(i), dina =>an_in(i), douta => an_out(i), clkb =>clk320, regceb =>lock, web => wr_b, addrb=> loc_addr(7 downto 0), dinb=> (others=>'0'), doutb => an_rd(i)); + +ampln_addr(i) <= hyst_data(i)(25) & (not hyst_data(i)(19 downto 12)); +ampl_addr(i) <= hyst_data(i)(25) & hyst_data(i)(23 downto 12); +wr_b(0)<=clr; + + +t_in(i)<= x"FFFF" when (t_out(i)=x"FFFF") else + t_out(i)+1; + +a_in(i)<= x"FFFF" when (a_out(i)=x"FFFF") else + a_out(i)+1; + +an_in(i)<= x"FFFF" when (an_out(i)=x"FFFF") else + an_out(i)+1; + + +wr_mem_t(i)(0)<= hyst_t2(i); +wr_mem_a(i)(0)<= hyst_a2(i) and (not hyst_data(i)(24)); +wr_mem_an(i)(0)<=hyst_a2(i) and hyst_data(i)(24); + +end generate; + + +process (clk320) +begin +if (clk320'event and clk320='1') then + +if (hyst_st='1') then hyst_t0<= hyst_t and (not hyst_t1); + else hyst_t0<=(others=>'0'); +end if; + +hyst_t2<= hyst_t1; hyst_t1<= hyst_t0; + +if (hyst_st='1') then hyst_a0<= hyst_a and (not hyst_a1); + else hyst_a0<=(others=>'0'); +end if; + +hyst_a2<= hyst_a1; hyst_a1<= hyst_a0; + +for i in 0 to 11 loop + +if (hyst_st='1') and (hyst_t1(i)='0') then hyst_data(i)(11 downto 0) <= hyst_inp_data(i)(11 downto 0); end if; +if (hyst_st='1') and (hyst_a1(i)='0') then hyst_data(i)(25 downto 12) <= hyst_inp_data(i)(25 downto 12); end if; +if ((t_out(i)>=x"FFFE") and (wr_mem_t(i)(0)='1')) or ((a_out(i)>=x"FFFE") and (wr_mem_a(i)(0)='1')) or ((an_out(i)>=x"FFFE") and (wr_mem_an(i)(0)='1')) then ovf(i)<= '1' ; else ovf(i)<= '0'; end if; +end loop; + +if (cnt_clr='1') then clr <='1'; + else + if (loc_addr(11 downto 0) = x"FFF") then clr<='0'; end if; +end if; + +if (cnt_clr='1') then loc_addr(11 downto 0)<= (others=>'0'); + else + if (clr='1') then loc_addr(11 downto 0)<= loc_addr(11 downto 0)+1; + else + if (wr_addr='1') then loc_addr<=hyst_addr_i; + else + if (n_addr='1') then + if (loc_addr(12 downto 0)>='1' & x"8ff") then + loc_addr(12 downto 0)<=(others=>'0'); + if (loc_addr(16 downto 13)<11) then loc_addr(16 downto 13)<= loc_addr(16 downto 13)+1; + else loc_addr(16 downto 13)<=x"0"; + end if; + else + loc_addr(12 downto 0)<=loc_addr(12 downto 0)+1; + end if; + end if; + end if; + end if; +end if; + +end if; +end process; + +end RTL; diff --git a/firmware/FT0/PM/hdl/trigger.vhd b/firmware/FT0/PM/hdl/trigger.vhd index 02c1acd..64b3679 100644 --- a/firmware/FT0/PM/hdl/trigger.vhd +++ b/firmware/FT0/PM/hdl/trigger.vhd @@ -17,15 +17,6 @@ -- Additional Comments: -- ---------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -package PM12_pkg is -type trig_time is array (0 to 11) of STD_LOGIC_VECTOR (9 downto 0); -type trig_ampl0 is array (0 to 11) of STD_LOGIC_VECTOR(12 downto 0); -end package; - - library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; diff --git a/firmware/FT0/PM/ipcore_properties/hyst_mem4k.txt b/firmware/FT0/PM/ipcore_properties/hyst_mem4k.txt new file mode 100644 index 0000000..5c39b26 --- /dev/null +++ b/firmware/FT0/PM/ipcore_properties/hyst_mem4k.txt @@ -0,0 +1,78 @@ +Property Type Read-only Value +CONFIG.AXILITE_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_ID_Width string false 4 +CONFIG.AXI_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_Slave_Type string false Memory_Slave +CONFIG.AXI_Type string false AXI4_Full +CONFIG.Additional_Inputs_for_Power_Estimation string false false +CONFIG.Algorithm string false Minimum_Area +CONFIG.Assume_Synchronous_Clk string false true +CONFIG.Byte_Size string false 9 +CONFIG.CLK.ACLK.INSERT_VIP string false 0 +CONFIG.CTRL_ECC_ALGO string false NONE +CONFIG.Coe_File string false no_coe_file_loaded +CONFIG.Collision_Warnings string false ALL +CONFIG.Component_Name string false hyst_mem4k +CONFIG.Disable_Collision_Warnings string false false +CONFIG.Disable_Out_of_Range_Warnings string false false +CONFIG.ECC string false false +CONFIG.EN_DEEPSLEEP_PIN string false false +CONFIG.EN_ECC_PIPE string false false +CONFIG.EN_SAFETY_CKT string false false +CONFIG.EN_SHUTDOWN_PIN string false false +CONFIG.EN_SLEEP_PIN string false false +CONFIG.Enable_32bit_Address string false false +CONFIG.Enable_A string false Always_Enabled +CONFIG.Enable_B string false Always_Enabled +CONFIG.Error_Injection_Type string false Single_Bit_Error_Injection +CONFIG.Fill_Remaining_Memory_Locations string false false +CONFIG.Interface_Type string false Native +CONFIG.Load_Init_File string false false +CONFIG.MEM_FILE string false no_mem_loaded +CONFIG.Memory_Type string false True_Dual_Port_RAM +CONFIG.Operating_Mode_A string false READ_FIRST +CONFIG.Operating_Mode_B string false READ_FIRST +CONFIG.Output_Reset_Value_A string false 0 +CONFIG.Output_Reset_Value_B string false 0 +CONFIG.PRIM_type_to_Implement string false BRAM +CONFIG.Pipeline_Stages string false 0 +CONFIG.Port_A_Clock string false 100 +CONFIG.Port_A_Enable_Rate string false 100 +CONFIG.Port_A_Write_Rate string false 50 +CONFIG.Port_B_Clock string false 100 +CONFIG.Port_B_Enable_Rate string false 100 +CONFIG.Port_B_Write_Rate string false 50 +CONFIG.Primitive string false 8kx2 +CONFIG.RD_ADDR_CHNG_A string false false +CONFIG.RD_ADDR_CHNG_B string false false +CONFIG.READ_LATENCY_A string false 1 +CONFIG.READ_LATENCY_B string false 1 +CONFIG.RST.ARESETN.INSERT_VIP string false 0 +CONFIG.Read_Width_A string false 16 +CONFIG.Read_Width_B string false 32 +CONFIG.Register_PortA_Output_of_Memory_Core string false false +CONFIG.Register_PortA_Output_of_Memory_Primitives string false true +CONFIG.Register_PortB_Output_of_Memory_Core string false false +CONFIG.Register_PortB_Output_of_Memory_Primitives string false true +CONFIG.Remaining_Memory_Locations string false 0 +CONFIG.Reset_Memory_Latch_A string false false +CONFIG.Reset_Memory_Latch_B string false false +CONFIG.Reset_Priority_A string false CE +CONFIG.Reset_Priority_B string false CE +CONFIG.Reset_Type string false SYNC +CONFIG.Use_AXI_ID string false false +CONFIG.Use_Byte_Write_Enable string false false +CONFIG.Use_Error_Injection_Pins string false false +CONFIG.Use_REGCEA_Pin string false false +CONFIG.Use_REGCEB_Pin string false true +CONFIG.Use_RSTA_Pin string false false +CONFIG.Use_RSTB_Pin string false false +CONFIG.Write_Depth_A string false 4096 +CONFIG.Write_Width_A string false 16 +CONFIG.Write_Width_B string false 32 +CONFIG.ecctype string false No_ECC +CONFIG.register_porta_input_of_softecc string false false +CONFIG.register_portb_output_of_softecc string false false +CONFIG.softecc string false false +CONFIG.use_bram_block string false Stand_Alone +IPDEF string true xilinx.com:ip:blk_mem_gen:8.4 diff --git a/firmware/FT0/PM/ipcore_properties/hyst_mem512.txt b/firmware/FT0/PM/ipcore_properties/hyst_mem512.txt new file mode 100644 index 0000000..f1dd2e3 --- /dev/null +++ b/firmware/FT0/PM/ipcore_properties/hyst_mem512.txt @@ -0,0 +1,78 @@ +Property Type Read-only Value +CONFIG.AXILITE_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_ID_Width string false 4 +CONFIG.AXI_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_Slave_Type string false Memory_Slave +CONFIG.AXI_Type string false AXI4_Full +CONFIG.Additional_Inputs_for_Power_Estimation string false false +CONFIG.Algorithm string false Minimum_Area +CONFIG.Assume_Synchronous_Clk string false true +CONFIG.Byte_Size string false 9 +CONFIG.CLK.ACLK.INSERT_VIP string false 0 +CONFIG.CTRL_ECC_ALGO string false NONE +CONFIG.Coe_File string false no_coe_file_loaded +CONFIG.Collision_Warnings string false ALL +CONFIG.Component_Name string false hyst_mem512 +CONFIG.Disable_Collision_Warnings string false false +CONFIG.Disable_Out_of_Range_Warnings string false false +CONFIG.ECC string false false +CONFIG.EN_DEEPSLEEP_PIN string false false +CONFIG.EN_ECC_PIPE string false false +CONFIG.EN_SAFETY_CKT string false false +CONFIG.EN_SHUTDOWN_PIN string false false +CONFIG.EN_SLEEP_PIN string false false +CONFIG.Enable_32bit_Address string false false +CONFIG.Enable_A string false Always_Enabled +CONFIG.Enable_B string false Always_Enabled +CONFIG.Error_Injection_Type string false Single_Bit_Error_Injection +CONFIG.Fill_Remaining_Memory_Locations string false false +CONFIG.Interface_Type string false Native +CONFIG.Load_Init_File string false false +CONFIG.MEM_FILE string false no_mem_loaded +CONFIG.Memory_Type string false True_Dual_Port_RAM +CONFIG.Operating_Mode_A string false READ_FIRST +CONFIG.Operating_Mode_B string false READ_FIRST +CONFIG.Output_Reset_Value_A string false 0 +CONFIG.Output_Reset_Value_B string false 0 +CONFIG.PRIM_type_to_Implement string false BRAM +CONFIG.Pipeline_Stages string false 0 +CONFIG.Port_A_Clock string false 100 +CONFIG.Port_A_Enable_Rate string false 100 +CONFIG.Port_A_Write_Rate string false 50 +CONFIG.Port_B_Clock string false 100 +CONFIG.Port_B_Enable_Rate string false 100 +CONFIG.Port_B_Write_Rate string false 50 +CONFIG.Primitive string false 8kx2 +CONFIG.RD_ADDR_CHNG_A string false false +CONFIG.RD_ADDR_CHNG_B string false false +CONFIG.READ_LATENCY_A string false 1 +CONFIG.READ_LATENCY_B string false 1 +CONFIG.RST.ARESETN.INSERT_VIP string false 0 +CONFIG.Read_Width_A string false 16 +CONFIG.Read_Width_B string false 32 +CONFIG.Register_PortA_Output_of_Memory_Core string false false +CONFIG.Register_PortA_Output_of_Memory_Primitives string false true +CONFIG.Register_PortB_Output_of_Memory_Core string false false +CONFIG.Register_PortB_Output_of_Memory_Primitives string false true +CONFIG.Remaining_Memory_Locations string false 0 +CONFIG.Reset_Memory_Latch_A string false false +CONFIG.Reset_Memory_Latch_B string false false +CONFIG.Reset_Priority_A string false CE +CONFIG.Reset_Priority_B string false CE +CONFIG.Reset_Type string false SYNC +CONFIG.Use_AXI_ID string false false +CONFIG.Use_Byte_Write_Enable string false false +CONFIG.Use_Error_Injection_Pins string false false +CONFIG.Use_REGCEA_Pin string false false +CONFIG.Use_REGCEB_Pin string false true +CONFIG.Use_RSTA_Pin string false false +CONFIG.Use_RSTB_Pin string false false +CONFIG.Write_Depth_A string false 512 +CONFIG.Write_Width_A string false 16 +CONFIG.Write_Width_B string false 32 +CONFIG.ecctype string false No_ECC +CONFIG.register_porta_input_of_softecc string false false +CONFIG.register_portb_output_of_softecc string false false +CONFIG.softecc string false false +CONFIG.use_bram_block string false Stand_Alone +IPDEF string true xilinx.com:ip:blk_mem_gen:8.4 diff --git a/firmware/FT0/PM/ipcore_properties/hyst_mem8k.txt b/firmware/FT0/PM/ipcore_properties/hyst_mem8k.txt new file mode 100644 index 0000000..811a1d9 --- /dev/null +++ b/firmware/FT0/PM/ipcore_properties/hyst_mem8k.txt @@ -0,0 +1,78 @@ +Property Type Read-only Value +CONFIG.AXILITE_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_ID_Width string false 4 +CONFIG.AXI_SLAVE_S_AXI.INSERT_VIP string false 0 +CONFIG.AXI_Slave_Type string false Memory_Slave +CONFIG.AXI_Type string false AXI4_Full +CONFIG.Additional_Inputs_for_Power_Estimation string false false +CONFIG.Algorithm string false Minimum_Area +CONFIG.Assume_Synchronous_Clk string false true +CONFIG.Byte_Size string false 9 +CONFIG.CLK.ACLK.INSERT_VIP string false 0 +CONFIG.CTRL_ECC_ALGO string false NONE +CONFIG.Coe_File string false no_coe_file_loaded +CONFIG.Collision_Warnings string false ALL +CONFIG.Component_Name string false hyst_mem8k +CONFIG.Disable_Collision_Warnings string false false +CONFIG.Disable_Out_of_Range_Warnings string false false +CONFIG.ECC string false false +CONFIG.EN_DEEPSLEEP_PIN string false false +CONFIG.EN_ECC_PIPE string false false +CONFIG.EN_SAFETY_CKT string false false +CONFIG.EN_SHUTDOWN_PIN string false false +CONFIG.EN_SLEEP_PIN string false false +CONFIG.Enable_32bit_Address string false false +CONFIG.Enable_A string false Always_Enabled +CONFIG.Enable_B string false Always_Enabled +CONFIG.Error_Injection_Type string false Single_Bit_Error_Injection +CONFIG.Fill_Remaining_Memory_Locations string false false +CONFIG.Interface_Type string false Native +CONFIG.Load_Init_File string false false +CONFIG.MEM_FILE string false no_mem_loaded +CONFIG.Memory_Type string false True_Dual_Port_RAM +CONFIG.Operating_Mode_A string false READ_FIRST +CONFIG.Operating_Mode_B string false READ_FIRST +CONFIG.Output_Reset_Value_A string false 0 +CONFIG.Output_Reset_Value_B string false 0 +CONFIG.PRIM_type_to_Implement string false BRAM +CONFIG.Pipeline_Stages string false 0 +CONFIG.Port_A_Clock string false 100 +CONFIG.Port_A_Enable_Rate string false 100 +CONFIG.Port_A_Write_Rate string false 50 +CONFIG.Port_B_Clock string false 100 +CONFIG.Port_B_Enable_Rate string false 100 +CONFIG.Port_B_Write_Rate string false 50 +CONFIG.Primitive string false 8kx2 +CONFIG.RD_ADDR_CHNG_A string false false +CONFIG.RD_ADDR_CHNG_B string false false +CONFIG.READ_LATENCY_A string false 1 +CONFIG.READ_LATENCY_B string false 1 +CONFIG.RST.ARESETN.INSERT_VIP string false 0 +CONFIG.Read_Width_A string false 16 +CONFIG.Read_Width_B string false 32 +CONFIG.Register_PortA_Output_of_Memory_Core string false false +CONFIG.Register_PortA_Output_of_Memory_Primitives string false true +CONFIG.Register_PortB_Output_of_Memory_Core string false false +CONFIG.Register_PortB_Output_of_Memory_Primitives string false true +CONFIG.Remaining_Memory_Locations string false 0 +CONFIG.Reset_Memory_Latch_A string false false +CONFIG.Reset_Memory_Latch_B string false false +CONFIG.Reset_Priority_A string false CE +CONFIG.Reset_Priority_B string false CE +CONFIG.Reset_Type string false SYNC +CONFIG.Use_AXI_ID string false false +CONFIG.Use_Byte_Write_Enable string false false +CONFIG.Use_Error_Injection_Pins string false false +CONFIG.Use_REGCEA_Pin string false false +CONFIG.Use_REGCEB_Pin string false true +CONFIG.Use_RSTA_Pin string false false +CONFIG.Use_RSTB_Pin string false false +CONFIG.Write_Depth_A string false 8192 +CONFIG.Write_Width_A string false 16 +CONFIG.Write_Width_B string false 32 +CONFIG.ecctype string false No_ECC +CONFIG.register_porta_input_of_softecc string false false +CONFIG.register_portb_output_of_softecc string false false +CONFIG.softecc string false false +CONFIG.use_bram_block string false Stand_Alone +IPDEF string true xilinx.com:ip:blk_mem_gen:8.4 diff --git a/firmware/FT0/PM/make.tcl b/firmware/FT0/PM/make.tcl index a05ffab..ba7982a 100644 --- a/firmware/FT0/PM/make.tcl +++ b/firmware/FT0/PM/make.tcl @@ -127,6 +127,8 @@ set files [list \ [file normalize "${origin_dir}/hdl/autophase.vhd" ]\ [file normalize "${origin_dir}/hdl/Flash_prog.vhd" ]\ [file normalize "${origin_dir}/hdl/fit.vhd" ]\ + [file normalize "${origin_dir}/hdl/hyst.vhd" ]\ + [file normalize "${origin_dir}/hdl/PM12_pkg.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/xilinx_k7v7/xlx_k7v7_gbt_bank_package.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/xilinx_k7v7/xlx_k7v7_gbt_banks_user_setup.vhd" ]\ [file normalize "${origin_dir}/../../common/gbt-fpga/hdl/gbt_bank/core_sources/gbt_bank_package.vhd" ]\ diff --git a/firmware/FT0/PM/xdc/Timing.xdc b/firmware/FT0/PM/xdc/Timing.xdc index 6db9083..3da8154 100644 --- a/firmware/FT0/PM/xdc/Timing.xdc +++ b/firmware/FT0/PM/xdc/Timing.xdc @@ -84,8 +84,8 @@ set_multicycle_path -hold -start -from [get_clocks RxWordCLK] -to [get_cells {Fi FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank/gbtRx_param_package_src_gen.gbtRx_gen[1].gbtRx/descrambler/gbtFrameOrWideBus_gen.gbtRxDescrambler84bit_gen[?].gbtRxDescrambler21bit/feedbackRegister_reg[*]}] 2 -#set_false_path -hold -from [get_clocks RXDataCLK] -to [get_pins FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D] -#set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_pins FitGbtPrg/gbt_bank_gen.gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D] 1.000 +#set_false_path -hold -from [get_clocks RXDataCLK] -to [get_pins FitGbtPrg/gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D] +#set_max_delay -datapath_only -from [get_clocks RXDataCLK] -to [get_pins FitGbtPrg/gbtBankDsgn/gbtBank_rxFrmClkPhAlgnr/latOpt_phalgnr_gen.phase_computing_inst/serialToParallel_reg[0]/D] 1.000 # GBT readout diff --git a/firmware/FT0/PM/xdc/fit.xdc b/firmware/FT0/PM/xdc/fit.xdc index 7e0fd70..c7753aa 100644 --- a/firmware/FT0/PM/xdc/fit.xdc +++ b/firmware/FT0/PM/xdc/fit.xdc @@ -54,8 +54,8 @@ set_property ASYNC_REG true [get_cells spi_lock0_?_reg] set_property ASYNC_REG true [get_cells almclr??_reg] set_property ASYNC_REG true [get_cells stat_clr?_reg] -set_property ASYNC_REG true [get_cells spi_lock320_reg] -set_property ASYNC_REG true [get_cells spi_lock320_0_reg] +set_property ASYNC_REG true [get_cells {spi_lock320_reg spi_lock320_0_reg}] +set_property ASYNC_REG true [get_cells {hspi_lock320_reg hspi_lock320_0_reg}] set_property ASYNC_REG true [get_cells hclr??_reg] set_property ASYNC_REG true [get_cells hstat_clr?_reg] @@ -94,7 +94,9 @@ set_property ASYNC_REG true [get_cells count1/rd_en1_reg] set_property ASYNC_REG true [get_cells count1/hrd_en0_reg] set_property ASYNC_REG true [get_cells count1/hrd_en1_reg] -set_property ASYNC_REG true [get_cells {xadc_rq0_reg xadc_rq1_reg}] +set_property ASYNC_REG true [get_cells {reg32_320_wr0_reg reg32_320_wr1_reg reg32_320_str0_reg reg32_320_str1_reg}] + +set_property ASYNC_REG true [get_cells {reg32_str0_reg reg32_str1_reg}] set_property IOB TRUE [get_cells {{tto_reg[?]} {tao_reg[?]}}] diff --git a/firmware/FT0/TCM/hdl/HDMIRX.vhd b/firmware/FT0/TCM/hdl/HDMIRX.vhd index 1d74593..8b034da 100644 --- a/firmware/FT0/TCM/hdl/HDMIRX.vhd +++ b/firmware/FT0/TCM/hdl/HDMIRX.vhd @@ -185,12 +185,16 @@ if (dvalue(i)="11111") then dl_high_i(i)<= '1'; else dl_high_i(i)<='0'; end if; if (rst='1') or (sig_lost(i)='1') or (ena='0') or (dly_ctrl_ena='0') then ph_cnt(i)<="01111"; else - if (edge(i)='1') then - if ((ph_cnt(i)="11111") and (el(i)='1') and (dl_high_i(i)='0')) or ((ph_cnt(i)="00000") and (el(i)='0') and (dl_low_i(i)='0')) then dl_ce(i)<='1'; dl_inc(i)<=el(i); ph_cnt(i)<="01111"; - else - if (el(i)='1') then ph_cnt(i)<=ph_cnt(i)+1; else ph_cnt(i)<=ph_cnt(i)-1; end if; - end if; - end if; + if ( mast_stable_i='1') then + if (edge(i)='1') then + if ((ph_cnt(i)="11111") and (el(i)='1') and (dl_high_i(i)='0')) or ((ph_cnt(i)="00000") and (el(i)='0') and (dl_low_i(i)='0')) then dl_ce(i)<='1'; dl_inc(i)<=el(i); ph_cnt(i)<="01111"; + else + if (el(i)='1') then ph_cnt(i)<=ph_cnt(i)+1; else ph_cnt(i)<=ph_cnt(i)-1; end if; + end if; + end if; + else + dl_ce(i)<=dl_ce0; dl_inc(i)<=dl_inc0; + end if; end if; if (dl_ce(i)='1') then dl_ce(i)<='0'; end if; @@ -203,7 +207,7 @@ if (dvalue(i)="11111") then dl_high_i(i)<= '1'; else dl_high_i(i)<='0'; end if; mast_stable_i<=sig_stable(0); - if (rst='1') or (sig_lost(0)='1') or (ena='0') then ph_cnt(0)<="01111"; + if (rst='1') or (sig_lost(0)='1') or (ena='0') or ((master='0') and (dly_ctrl_ena='0')) then ph_cnt(0)<="01111"; else if (edge(0)='1') then if ((ph_cnt(0)="11111") and (el(0)='1') and (dl_high_i(0)='0')) or ((ph_cnt(0)="00000") and (el(0)='0') and (dl_low_i(0)='0')) then dl_ce0<='1'; diff --git a/firmware/FT0/TCM/hdl/pm-spi.vhd b/firmware/FT0/TCM/hdl/pm-spi.vhd index cf18f66..cb192f8 100644 --- a/firmware/FT0/TCM/hdl/pm-spi.vhd +++ b/firmware/FT0/TCM/hdl/pm-spi.vhd @@ -86,7 +86,7 @@ rdy<= '1' when ((cs='1') and (eoc='1') and (smode='0')and (cmd_rst='0')) or (fif -cs_spi <='1' when (cs='1') and ((A(8)='0') or (A='1' & x"02")) else '0'; +cs_spi <= ena when (cs='1') and ((A(8)='0') or (A='1' & x"02")) else '0'; DO <= fifo_out when (fifo_rd='1') else x"00000" & "00" & fifo_cou when (reg_rd='1') else @@ -96,20 +96,18 @@ DO <= fifo_out when (fifo_rd='1') else reg_rd<='1' when (cs='1') and (rd='1') and (A='1' & x"01") else '0'; -xmg_sel<='1' when (cs='1') and (A='1' & x"02") else '0'; +xmg_sel<= ena when (cs='1') and (A='1' & x"02") else '0'; xmg_md<= (xmg_sel and not smode) or cmd_rst; -spi_mosi<=Dreg(47) and ena; -spi_sel<= spi_sel_i and ena; +spi_mosi<=Dreg(47) and (ena or cmd_rst); +spi_sel<= spi_sel_i and (ena or cmd_rst); spi_inp<=xmg_smpl when (xmg_md='1') else not spi_miso; A_spi<=A(7 downto 0) when (smode='0') else "110" & A_cou; rd_spi<= rd when (smode='0') else '1'; -spi_clk <= count(1) when (((count(7 downto 2)/="000000") and (xmg_md='0')) or (x_wait='0')) and (ena='1') else '0'; - mode16<= '1' when A_spi(7 downto 4)TD_P(i), TD_N=>TD_N(i), RST=>SRST, ena=>link_ena(i), link_rdy=>link_OK_in(i), trig_ena=>done, clk320=>clk320, clk320_90=>clk320_90, TDO=>HDMI_in(i), rd_lock=>rd_lock1, DATA_OUT=> TDD(i), status => HDMI_status(i), master=> master_sel(i), mt_cou=>mt_cou, bitpos=>bitpos(i), bitpos_ok=>bitpos_ok_in(i), ena_dly=>ena_dly, inc_dly=>inc_dly, ena_ph=>psen_o(i), inc_ph=>ph_inc_o(i), is_idle=>is_idle(i), bp_stable=>bp_stable(i), dl_low=> dl_low(i), dl_high=> dl_high(i), mast_dl_err=>mast_dlerr(i), mast_stable=>mast_stable(i), dly_ctrl_ena=>dly_ctrl_ena, syn_err=>sync_err(i), PM_req=>req(i)); @@ -239,6 +237,9 @@ mdl_err<= mast_dlerr(to_integer(unsigned(master_n))) when (side_on='1') else '0' end if; for i in 0 to 9 loop + +link_ena(i)<=config(i) and not stat_chg ; + if sync_err(i)='1' then sync_err_s(i)<='1'; else if (stat_clr2='1') and (stat_clr1='0') then sync_err_s(i)<='0'; end if; end if; diff --git a/firmware/FT0/TCM_v1/hdl/tcm.vhd b/firmware/FT0/TCM_v1/hdl/tcm.vhd index 61b51a7..0fcce6c 100644 --- a/firmware/FT0/TCM_v1/hdl/tcm.vhd +++ b/firmware/FT0/TCM_v1/hdl/tcm.vhd @@ -205,7 +205,8 @@ signal TimeC, TimeC0, TimeC1, TimeC2, TimeA : STD_LOGIC_VECTOR (8 downto 0); signal TimeA_o, TimeC_o : STD_LOGIC_VECTOR (15 downto 0); signal AvgA, AvgC : STD_LOGIC_VECTOR (13 downto 0); signal TresbM, TdiffM : STD_LOGIC_VECTOR (23 downto 0); -signal hdmiac_select, hdmicc_select, hdmias_select, hdmics_select, pll_lock_a, pll_lock_c, hdmis_ack, mul_ena, mul_enc, sideA_OK, sideC_OK, stat_clrA, stat_clrC, as_chg, cs_chg, rst_fl : STD_LOGIC; +signal hdmiac_select, hdmicc_select, hdmias_select, hdmics_select, pll_lock_a, pll_lock_c, hdmis_ack, mul_ena, mul_enc, sideA_OK, sideC_OK, stat_clrA, stat_clrC, as_chg, cs_chg, rst_fl, as_blk, cs_blk, hdmi_to0, hdmi_to : STD_LOGIC; +signal PM_tcou : STD_LOGIC_VECTOR (23 downto 0); signal dly_rst, cnt_rd, pm_adr_sel, pm_rdy, cnt_ctrl_sel, cnt_ctrl_rdy, ipb_locked, cnt_clr, cnt_lock, Tcnt_sel, Tcnt_0_rd, cnt_lock0, cnt_lock1, cnt_lock2, Tcnt_clr, cnt_clr0, cnt_clr1, cnt_clr2, Tcnt_ack, Tcnt_err : STD_LOGIC; signal fifo_sel, fifo_csel, f_rd, f_empty, f_wr, f_full, lclk160, lmode_sel, lpatt0_sel, lpatt1_sel, l_on, l_on0, l_on1, l_tg1, l_tg, l_fbin, l_fbout, a_t, a0_t, an_t : STD_LOGIC; signal l_cnt : STD_LOGIC_VECTOR (1 downto 0); @@ -1095,10 +1096,10 @@ lasi<=las_o; end if; end process; -tcma: tcm_side port map(CLKA=>CLKA, RST=>reset, SRST=>sreset, TD_P=>TDA_P, TD_N=>TDA_N, Config=>hdmia_config, Status=>Status_a, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrA, stat_chg=>as_chg, side_OK=>sideA_OK, TDD=>TDA, rd_lock=> rd_lock_a, +tcma: tcm_side port map(CLKA=>CLKA, RST=>reset, SRST=>sreset, TD_P=>TDA_P, TD_N=>TDA_N, Config=>hdmia_config, Status=>Status_a, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrA, stat_chg=>as_blk, side_OK=>sideA_OK, TDD=>TDA, rd_lock=> rd_lock_a, Or_o=>OrA_i, CLK320_o=>CLK320A, clksys40_o => clksys40, pll_lock=> pll_lock_a, mt_cou_o=>bitcnt_A, Time_o=>TimeA_o, Avg_o=>AvgA, Ampl_O=>AmplA, Nchan=> Nchan_A, req=> reqA, bkgnd=> bkgndA); -tcmc: tcm_side port map(CLKA=>CLKC, RST=>reset, SRST=>sreset, TD_P=>TDC_P, TD_N=>TDC_N, Config=>hdmic_config, Status=>Status_C, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrC, stat_chg=>cs_chg, side_OK=>sideC_OK, TDD=>TDC0, rd_lock=> rd_lock_c, +tcmc: tcm_side port map(CLKA=>CLKC, RST=>reset, SRST=>sreset, TD_P=>TDC_P, TD_N=>TDC_N, Config=>hdmic_config, Status=>Status_C, stat_adr=> ipb_addr(3 downto 0), stat_clr=>stat_clrC, stat_chg=>cs_blk, side_OK=>sideC_OK, TDD=>TDC0, rd_lock=> rd_lock_c, Or_o=>OrC_B, CLK320_o=>CLK320C, clksys40_o=> open, pll_lock=> pll_lock_c, mt_cou_o=>bitcnt_c, Time_o=>TimeC_o, Avg_o=>AvgC, Ampl_o=>AmplC0, Nchan=> Nchan_C0, req=> reqC, bkgnd=> bkgndC0); TresbM<=TimeC(8) & TimeC & "00000000000000"; @@ -1190,6 +1191,9 @@ PM_rst <= rst_spi2 and (not rst_spi1); bccorr_rd<= bccorr_sel or bccorrA_sel or bccorrC_sel; bccorr_ack<=bccorr_ack0 and bccorr_rd; +hdmi_to0<='1' when (PM_tcou/=15625000) else '0'; +as_blk<=as_chg or hdmi_to; cs_blk<=cs_chg or hdmi_to; + process(ipb_clk) begin if (ipb_clk'event and ipb_clk='1') then @@ -1226,8 +1230,16 @@ if (rst_spi1='1') then RST_req<='0'; clk_frs<='0'; end if; end if; -if (hdmiac_select='1') and (ipb_iswr='1') then hdmia_config<=ipb_data_out; as_chg<='1'; end if; -if (hdmicc_select='1') and (ipb_iswr='1') then hdmic_config<=ipb_data_out; cs_chg<='1'; end if; +if (ipb_rst='1') then hdmia_config<=(others=>'0'); hdmic_config<=(others=>'0'); + else + hdmi_to<=hdmi_to0; + if (PM_rst='1') then PM_tcou<=(others=>'0'); + else + if (hdmi_to0='1') then PM_tcou<=PM_tcou+1; end if; + end if; + if (hdmiac_select='1') and (ipb_iswr='1') then hdmia_config<=ipb_data_out; as_chg<='1'; end if; + if (hdmicc_select='1') and (ipb_iswr='1') then hdmic_config<=ipb_data_out; cs_chg<='1'; end if; +end if; if (as_chg='1') then as_chg<='0'; end if; if (cs_chg='1') then cs_chg<='0'; end if; diff --git a/firmware/FT0/bits/FIT_TESTMODULE_v2.bin b/firmware/FT0/bits/FIT_TESTMODULE_v2.bin new file mode 100644 index 0000000..f5bfbd3 Binary files /dev/null and b/firmware/FT0/bits/FIT_TESTMODULE_v2.bin differ diff --git a/firmware/FT0/bits/FIT_TESTMODULE_v2.bit b/firmware/FT0/bits/FIT_TESTMODULE_v2.bit new file mode 100644 index 0000000..4b9e596 Binary files /dev/null and b/firmware/FT0/bits/FIT_TESTMODULE_v2.bit differ diff --git a/firmware/FT0/bits/PM.bin b/firmware/FT0/bits/PM.bin new file mode 100644 index 0000000..cd4aca2 Binary files /dev/null and b/firmware/FT0/bits/PM.bin differ diff --git a/firmware/FT0/bits/PM.bit b/firmware/FT0/bits/PM.bit new file mode 100644 index 0000000..aa3e5d5 Binary files /dev/null and b/firmware/FT0/bits/PM.bit differ diff --git a/firmware/FT0/bits/tcm.bin b/firmware/FT0/bits/tcm.bin new file mode 100644 index 0000000..08e3d33 Binary files /dev/null and b/firmware/FT0/bits/tcm.bin differ diff --git a/firmware/FT0/bits/tcm.bit b/firmware/FT0/bits/tcm.bit new file mode 100644 index 0000000..57fa309 Binary files /dev/null and b/firmware/FT0/bits/tcm.bit differ diff --git a/firmware/common/ftm/hdl/FIT_TESTMODULE_v2.vhd b/firmware/common/ftm/hdl/FIT_TESTMODULE_v2.vhd index 2bd09c1..c8c4528 100644 --- a/firmware/common/ftm/hdl/FIT_TESTMODULE_v2.vhd +++ b/firmware/common/ftm/hdl/FIT_TESTMODULE_v2.vhd @@ -662,7 +662,7 @@ HDMI0: tcm_sync -- IP-BUS module =============================================== sfp_rate_sel(1 downto 0) <= B"00"; -mac_addr <= X"020ddba11504"; -- Careful here, arbitrary addresses do not always work +mac_addr <= X"020ddba11503"; -- Careful here, arbitrary addresses do not always work --ip_addr <= X"ac144baf"; -- 172.20.75.175 --ip_addr <= X"ac144b5f"; -- 172.20.75.95 ip_addr <= X"c0a80029" when (addr_sw='1') else -- 192.168.0.41 diff --git a/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd b/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd index ec3bbe2..2a06533 100644 --- a/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd +++ b/firmware/common/gbt-readout/hdl/CRU_packet_Builder.vhd @@ -51,7 +51,7 @@ end CRU_packet_Builder; architecture Behavioral of CRU_packet_Builder is constant nwords_in_SOP : integer := 5; - constant nwords_in_EOP : integer := 2; + constant nwords_in_EOP : integer := 1; type SOP_format_type is array (0 to nwords_in_SOP-1) of std_logic_vector(GBT_data_word_bitdepth downto 0); type EOP_format_type is array (0 to nwords_in_EOP-1) of std_logic_vector(GBT_data_word_bitdepth downto 0); @@ -103,7 +103,7 @@ begin dwords_payload <= func_CNTPCKword_npwords(CNTPTFIFO_data_word_I); trailer_payload <= std_logic_vector(to_unsigned((nwords_in_EOP-1), GEN_count_bitdepth)); - data_payload_bytes <= (to_integer(unsigned(dwords_payload)) + 5) * 16; + data_payload_bytes <= (to_integer(unsigned(dwords_payload)) + 4) * 16; -- Data format *************************************** is_close_frame <= func_CNTPCKword_isclf(CNTPTFIFO_data_word_I); @@ -153,11 +153,8 @@ begin - EOP_format(0) <= '1' & x"ffff" & cont_packet_count; -- test trailer - - EOP_format(1) <= '0' & x"20000000000000000000"; -- eop CRU - --EOP_format(1) <= '0' & x"00000000000000000002"; -- eop G-RORC - --EOP_format(1) <= '0' & data_word_cnst_EOP + --EOP_format(0) <= '1' & x"ffff" & cont_packet_count; -- test trailer + EOP_format(0) <= '0' & x"20000000000000000000"; -- eop CRU -- ***************************************************