vitis_hls.log

INFO: [HLS 200-10] Running 'C:/Xilinx/Vitis/2020.1/bin/unwrapped/win64.o/vitis_hls.exe'
INFO: [HLS 200-10] For user 'RicNid' on host 'desktop-t43kdvg' (Windows NT_amd64 version 6.2) on Wed Oct 14 18:20:15 +0800 2020
INFO: [HLS 200-10] In directory 'E:/LtrProjects/SharedProjects/HLS'
Sourcing Tcl script 'E:/LtrProjects/SharedProjects/HLS/CONV_LAYER/original/csim.tcl'
INFO: [HLS 200-10] Opening project 'E:/LtrProjects/SharedProjects/HLS/CONV_LAYER'.
INFO: [HLS 200-10] Adding design file 'CONV_LAYER/buf2pe.cpp' to the project
INFO: [HLS 200-10] Adding test bench file 'CONV_LAYER/test_buf2pe.cpp' to the project
INFO: [HLS 200-10] Opening solution 'E:/LtrProjects/SharedProjects/HLS/CONV_LAYER/original'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
WARNING: [HLS 200-40] Cannot find library 'C:/Xilinx/Vitis/2020.1/common/technology/xilinx/Virtex-7/Virtex-7.lib'.
WARNING: [HLS 200-40] Cannot find library 'xilinx/Virtex-7/Virtex-7'.
WARNING: [HLS 200-40] Cannot find library 'C:/Xilinx/Vitis/2020.1/common/technology/xilinx/Virtex-7/Virtex-7_fpv7.lib'.
WARNING: [HLS 200-40] Cannot find library 'xilinx/Virtex-7/Virtex-7_fpv7'.
INFO: [HLS 200-10] Setting target device to 'xcvu11p-flga2577-1-e'
INFO: [HLS 200-1505] Using flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/html_docs/xilinx2020_1/hls-guidance/200-1505.html
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
   Compiling ../../../buf2pe.cpp in debug mode
   Generating csim.exe
In file included from C:/Xilinx/Vitis/2020.1/include/floating_point_v7_0_bitacc_cmodel.h:144:0,
                 from C:/Xilinx/Vitis/2020.1/include/hls_fpo.h:189,
                 from C:/Xilinx/Vitis/2020.1/include/hls_half_fpo.h:64,
                 from C:/Xilinx/Vitis/2020.1/include/hls_half.h:71,
                 from C:/Xilinx/Vitis/2020.1/include/etc/ap_private.h:91,
                 from C:/Xilinx/Vitis/2020.1/include/ap_common.h:646,
                 from C:/Xilinx/Vitis/2020.1/include/ap_int.h:55,
                 from ../../../conv.h:4,
                 from ../../../buf2pe.cpp:1:
C:/Xilinx/Vitis/2020.1/include/gmp.h:63:0: warning: "__GMP_LIBGMP_DLL" redefined
 #define __GMP_LIBGMP_DLL  0
 
In file included from C:/Xilinx/Vitis/2020.1/include/hls_fpo.h:189:0,
                 from C:/Xilinx/Vitis/2020.1/include/hls_half_fpo.h:64,
                 from C:/Xilinx/Vitis/2020.1/include/hls_half.h:71,
                 from C:/Xilinx/Vitis/2020.1/include/etc/ap_private.h:91,
                 from C:/Xilinx/Vitis/2020.1/include/ap_common.h:646,
                 from C:/Xilinx/Vitis/2020.1/include/ap_int.h:55,
                 from ../../../conv.h:4,
                 from ../../../buf2pe.cpp:1:
C:/Xilinx/Vitis/2020.1/include/floating_point_v7_0_bitacc_cmodel.h:136:0: note: this is the location of the previous definition
 #define __GMP_LIBGMP_DLL 1
 
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WARNING: Hls::stream 'hls::stream<ap_ufixed<10, 1, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>.7' contains leftover data, which may result in RTL simulation hanging.
WARNING: Hls::stream 'hls::stream<ap_ufixed<10, 1, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>.6' contains leftover data, which may result in RTL simulation hanging.
WARNING: Hls::stream 'hls::stream<ap_ufixed<10, 1, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>.4' contains leftover data, which may result in RTL simulation hanging.
WARNING: Hls::stream 'hls::stream<ap_ufixed<10, 1, (ap_q_mode)5, (ap_o_mode)3, 0>, 0>.3' contains leftover data, which may result in RTL simulation hanging.
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************