From a51a79f39c8994967f15b91531df6d69d27f4fc2 Mon Sep 17 00:00:00 2001 From: z277zhu Date: Thu, 7 Dec 2023 17:24:10 -0500 Subject: [PATCH] fixed liveinfo parser bug && Added options in impor_from_mir (perBB, perFunc) --- gematria/datasets/bhive_importer.cc | 105 +- gematria/datasets/bhive_importer.h | 23 +- gematria/datasets/bhive_importer_test.cc | 2 +- gematria/datasets/python/bhive_importer.cc | 14 +- gematria/datasets/python/import_from_mir.py | 23 +- mir_input/test_mir_input/Activation.mir | 7932 +++++++++++++++++ .../test_mir_input/Activation.mir.liveinfo | 1077 +++ mir_input/test_mir_input/Activation.perf | 81 + ...info => AdaptiveMaxPooling2d.mir.liveinfo} | 3 +- mir_input/test_mir_input/aligneval_O2.bc.mir | 5639 ++++++++++++ .../aligneval_O2.bc.mir.liveinfo | 1293 +++ mir_input/test_mir_input/aligneval_O2.bc.perf | 36 + 12 files changed, 16153 insertions(+), 75 deletions(-) create mode 100644 mir_input/test_mir_input/Activation.mir create mode 100644 mir_input/test_mir_input/Activation.mir.liveinfo create mode 100644 mir_input/test_mir_input/Activation.perf rename mir_input/test_mir_input/{AdaptiveMaxPooling2d.liveinfo => AdaptiveMaxPooling2d.mir.liveinfo} (99%) create mode 100644 mir_input/test_mir_input/aligneval_O2.bc.mir create mode 100644 mir_input/test_mir_input/aligneval_O2.bc.mir.liveinfo create mode 100644 mir_input/test_mir_input/aligneval_O2.bc.perf diff --git a/gematria/datasets/bhive_importer.cc b/gematria/datasets/bhive_importer.cc index 90ca3f3c..48b1ccc5 100644 --- a/gematria/datasets/bhive_importer.cc +++ b/gematria/datasets/bhive_importer.cc @@ -67,7 +67,7 @@ constexpr int kDefaultSyntax = 0; } // namespace -BHiveImporter::BHiveImporter(const Canonicalizer* canonicalizer) +BHiveImporter::BHiveImporter(const Canonicalizer* canonicalizer, const std::string& model_type) : canonicalizer_(*ABSL_DIE_IF_NULL(canonicalizer)), target_machine_(canonicalizer->target_machine()), context_(std::make_unique( @@ -81,11 +81,11 @@ BHiveImporter::BHiveImporter(const Canonicalizer* canonicalizer) *target_machine_.getMCAsmInfo(), *target_machine_.getMCInstrInfo(), *target_machine_.getMCRegisterInfo())), MMI_(dynamic_cast(&target_machine_)) { + // setup super register to sub register mapping const llvm::MCRegisterInfo& MRI = *target_machine_.getMCRegisterInfo(); for (llvm::MCPhysReg I = 1, E = MRI.getNumRegs(); I != E; ++I) { // Append register definition line. llvm::StringRef reg_name = MRI.getName(I); - name_to_reg_[reg_name.str()] = I; // push itself to its own superreg2subreg_ list superreg2subreg_[reg_name.str()].push_back(reg_name.str()); for (auto SuperReg : MRI.superregs(I)) { @@ -95,6 +95,15 @@ BHiveImporter::BHiveImporter(const Canonicalizer* canonicalizer) } } } + // set up model type + if (model_type == "PER_BB_LIVE_INFO") { + model_type_ = MODEL_TYPE::PER_BB_LIVE_INFO; + } else if (model_type == "PER_FUNC_LIVE_INFO") { + model_type_ = MODEL_TYPE::PER_FUNC_LIVE_INFO; + } else { + model_type_ = MODEL_TYPE::NO_LIVE_INFO; + } + LOG("model type is " << model_type_ << " raw string is " << model_type); // prettyPrintName2Reg(); // prettyPrintSuperReg2SubReg(); } @@ -180,19 +189,9 @@ absl::StatusOr BHiveImporter::ParseBHiveCsvLine( return proto; } -absl::StatusOr BHiveImporter::BasicBlockProtoFromMBBName( - std::string_view MBB_name, uint64_t base_address /*= 0*/) { +absl::StatusOr BHiveImporter::BasicBlockProtoFromMBB( + llvm::MachineBasicBlock* MBB, uint64_t base_address /*= 0*/) { BasicBlockProto basic_block_proto; - // convert MBB_name to llvm::StringRef - llvm::StringRef MBB_name_ref(MBB_name.data(), MBB_name.size()); - - // lookup the MBB in the map, if not, return error - if (name_to_mbb_.find(MBB_name_ref) == name_to_mbb_.end()) { - return absl::InvalidArgumentError( - absl::StrCat("Could not find MBB with name ", MBB_name)); - } - - llvm::MachineBasicBlock* MBB = name_to_mbb_[MBB_name_ref]; LOG("MBB is " << *MBB); for (llvm::MachineInstr& MI : *MBB) { // if MI is a control instruction(ret,branch,jmp), skip it @@ -241,12 +240,9 @@ absl::StatusOr BHiveImporter::ParseMIRCsvLine( const std::string_view throughput_str = columns[throughput_column_index]; BasicBlockWithThroughputProto proto; - - absl::StatusOr block_proto_or_status = - BasicBlockProtoFromMBBName(BB_unique_name, base_address); - if (!block_proto_or_status.ok()) return block_proto_or_status.status(); - + // convert MBB_name to llvm::StringRef llvm::StringRef MBB_name_ref(BB_unique_name.data(), BB_unique_name.size()); + // lookup the MBB in the map, if not, return error if (name_to_mbb_.find(MBB_name_ref) == name_to_mbb_.end()) { return absl::InvalidArgumentError( @@ -254,18 +250,27 @@ absl::StatusOr BHiveImporter::ParseMIRCsvLine( } llvm::MachineBasicBlock* MBB = name_to_mbb_[MBB_name_ref]; - std::string func_name = MBB->getParent()->getName().str(); - assert(func_to_live_intervals_.find(func_name) != - func_to_live_intervals_.end() && - "Function not found in map"); - auto instrument_result = addInterferenceGraph( - *block_proto_or_status, func_to_live_intervals_[func_name], - func_to_live_intervals_[func_name] - .BBRangeList[std::string(BB_unique_name)]); - if (!instrument_result.ok()) { - return absl::InvalidArgumentError(absl::StrCat( - "Could not instrument interference graph for BB ", BB_unique_name)); + + absl::StatusOr block_proto_or_status = + BasicBlockProtoFromMBB(MBB, base_address); + if (!block_proto_or_status.ok()) return block_proto_or_status.status(); + + // Add inteference graph based on model type + if (model_type_ != MODEL_TYPE::NO_LIVE_INFO){ + std::string func_name = MBB->getParent()->getName().str(); + assert(func_to_live_intervals_.find(func_name) != + func_to_live_intervals_.end() && + "Function not found in map"); + auto instrument_result = addInterferenceGraph( + *block_proto_or_status, func_to_live_intervals_[func_name], + func_to_live_intervals_[func_name] + .BBRangeList[std::string(BB_unique_name)]); + if (!instrument_result.ok()) { + return absl::InvalidArgumentError(absl::StrCat( + "Could not instrument interference graph for BB ", BB_unique_name)); + } } + *proto.mutable_basic_block() = std::move(block_proto_or_status).value(); double throughput_cycles = 0.0; @@ -444,10 +449,6 @@ absl::StatusOr BHiveImporter::InteferenceGraphParser( lineStream >> dummy >> start >> dummy >> dummy >> end >> dummy >> dummy >> discard >> dummy; - // Print out information for debug - // std::cerr << "Register: " << currentRegister << ", " << start << ", " - // << end << "\n"; - // Since LLVM do not support [] operator we need to find it first auto resultRegLiveIntervals = (is_virtual) @@ -506,11 +507,12 @@ absl::StatusOr BHiveImporter::InteferenceGraphParser( lineStream >> start >> dummy >> end; info->BBRangeList[currentBB] = {start, end}; + isParsingRegister = false; } // In this case, we arrived at the definition of a new function // In this case we need to - else if (line[0] == '_') { + else { // We reached the end of a function, add info to the Map // If this is the beginning of a new function, just add // a dummy value and delete it at the end @@ -635,13 +637,6 @@ absl::StatusOr BHiveImporter::addInterferenceGraph( subReg) == func_live_infos.physical_register_live_range_func.end()) continue; - // pretty print live range of subRegs - // LOG("Live range of subReg: " << subReg); - // for (auto& range : - // func_live_infos.physical_register_live_range_func[subReg] - // .rangeList) { - // LOG(" " << range.first << ", " << range.second); - // } auto check_result = checkRegIntersectionsWithBBRange( func_live_infos.virtual_register_live_range_func[name], func_live_infos.physical_register_live_range_func[subReg], @@ -654,6 +649,23 @@ absl::StatusOr BHiveImporter::addInterferenceGraph( } } } + // if model_type is PER_FUNCTION_LIVE_INFO, then we need to add + // interference from the whole function + if (model_type_ == MODEL_TYPE::PER_FUNC_LIVE_INFO) { + for (auto& [vReg, liveInterval] : + func_live_infos.virtual_register_live_range_func) { + if (live_virtual_registers.count(vReg)) continue; + // LOG("Adding interference from function " << vReg); + auto check_result = checkRegIntersectionsWithBBRange( + func_live_infos.virtual_register_live_range_func[name], + liveInterval, bb_range); + if (!check_result.ok()) return check_result; + if (*check_result) { + mutable_intefered_register->Add(std::string(vReg)); + mutable_intefered_register_size->Add(32); + } + } // for + } return absl::StatusOr(true); }; @@ -712,12 +724,6 @@ absl::StatusOr BHiveImporter::addInterferenceGraph( } } - // pretty print physical registers - // LOG("Physical Registers: "); - // for (auto& reg : live_physical_registers) { - // LOG("Physical Register: " << reg); - // } - // Iterate over all operands in bb_proto, add interference registers to each // operand for (auto& instruction : *bb_proto.mutable_canonicalized_instructions()) { @@ -732,7 +738,8 @@ absl::StatusOr BHiveImporter::addInterferenceGraph( } // LOG("after: " << instruction.DebugString()); } + // printMap(func_to_live_intervals_); return true; -} +} // addInterferenceGraph } // namespace gematria diff --git a/gematria/datasets/bhive_importer.h b/gematria/datasets/bhive_importer.h index d4f52e1e..0c098521 100644 --- a/gematria/datasets/bhive_importer.h +++ b/gematria/datasets/bhive_importer.h @@ -70,10 +70,15 @@ namespace gematria { // Parser for BHive CSV files. class BHiveImporter { public: + enum MODEL_TYPE{ + NO_LIVE_INFO, + PER_BB_LIVE_INFO, + PER_FUNC_LIVE_INFO, + }; // Creates a new BHive importer from a given canonicalizer. The canonicalizer // must be for the architecture/microarchitecture of the data set. // Does not take ownership of the canonicalizer. - explicit BHiveImporter(const Canonicalizer* canonicalizer); + explicit BHiveImporter(const Canonicalizer* canonicalizer, const std::string& model_type = "NO_LIVE_INFO"); // Creates a basic block from the given block of machine code. `machine_code` // must contain machine code of the instructions to include in the basic @@ -94,8 +99,8 @@ class BHiveImporter { absl::StatusOr BasicBlockProtoFromMachineCodeHex( std::string_view machine_code_hex, uint64_t base_address = 0); - absl::StatusOr BasicBlockProtoFromMBBName( - std::string_view MBB_name, uint64_t base_address = 0); + absl::StatusOr BasicBlockProtoFromMBB( + llvm:: MachineBasicBlock* MBB, uint64_t base_address = 0); // Parses a basic block with throughput from one BHive CSV line. Expects that // the line has the format "{machine_code},{throughput}" where {machine_code} @@ -146,12 +151,6 @@ class BHiveImporter { std::unordered_map BBRangeList; }; - void prettyPrintName2Reg() { - for (auto& [name, reg] : name_to_reg_) { - LOG(name << " " << reg); - } - } - // pretty print superreg2subreg_ void prettyPrintSuperReg2SubReg() { LOG("SuperReg2SubReg: "); @@ -185,16 +184,12 @@ class BHiveImporter { llvm::DenseMap name_to_mbb_; std::unordered_map func_to_live_intervals_; - std::unordered_map name_to_reg_; std::unordered_map> superreg2subreg_; llvm::LLVMContext llvm_context_; std::unique_ptr mir_module_; llvm::MachineModuleInfo MMI_; std::unique_ptr mir_parser_; - - // Author: Zhan Shi - // Add one data strcture to the bhiveimporter storing interference graph - llvm::DenseMap name_to_graph_; + MODEL_TYPE model_type_; }; } // namespace gematria diff --git a/gematria/datasets/bhive_importer_test.cc b/gematria/datasets/bhive_importer_test.cc index 803242ff..70e67c54 100644 --- a/gematria/datasets/bhive_importer_test.cc +++ b/gematria/datasets/bhive_importer_test.cc @@ -37,7 +37,7 @@ class BHiveImporterTest : public ::testing::Test { x86_canonicalizer_ = std::make_unique(&x86_llvm_->target_machine()); x86_bhive_importer_ = - std::make_unique(x86_canonicalizer_.get()); + std::make_unique(x86_canonicalizer_.get(), "PER_FUNC_LIVE_INFO"); } std::unique_ptr x86_llvm_; diff --git a/gematria/datasets/python/bhive_importer.cc b/gematria/datasets/python/bhive_importer.cc index 1ba2c324..76a4aec0 100644 --- a/gematria/datasets/python/bhive_importer.cc +++ b/gematria/datasets/python/bhive_importer.cc @@ -37,8 +37,9 @@ PYBIND11_MODULE(bhive_importer, m) { py::class_(m, "BHiveImporter") .def( // - py::init(), + py::init(), py::arg("canonicalizer"), + py::arg("model_type") = std::string("NO_LIVE_INFO"), R"(Initializes a new BHive importer for a given architecture. Args: @@ -145,13 +146,12 @@ PYBIND11_MODULE(bhive_importer, m) { py::arg("source_name"), py::arg("line"),py::arg("BB_name_index"), py::arg("throughput_column_index"), py::arg("throughput_scaling") = 1.0, py::arg("base_address") = uint64_t{0}, R"(Creates a BasicBlockWithThroughputProto from a MIR CSV line.)" + ).def( + "parse_interference_graph", + &BHiveImporter::InteferenceGraphParser, py::arg("file_name"), + R"(Parse the interference graph from a file)" ) - .def( - "BasicBlockProtoFromMBBName", - &BHiveImporter::BasicBlockProtoFromMBBName, - py::arg("MBB_name"), py::arg("base_address") = uint64_t{0}, - R"(Creates a BasicBlockProto from a MIR CSV line.)" - ); + ; } } // namespace gematria diff --git a/gematria/datasets/python/import_from_mir.py b/gematria/datasets/python/import_from_mir.py index aa97b2a8..9d4d5b14 100644 --- a/gematria/datasets/python/import_from_mir.py +++ b/gematria/datasets/python/import_from_mir.py @@ -49,6 +49,12 @@ 'The name of directory containing all raw MIR files with performance throughput', ) +_MODEL_TYPE = flags.DEFINE_string( + 'gematria_model_format', + None, + 'The format of dataset to be imported. [NO_LIVE_INFO, PER_BB_LIVE_INFO, PER_FUNC_LIVE_INFO]', +) + _OUTPUT_TFRECORD_FILE = flags.DEFINE_string( 'gematria_output_tfrecord', None, @@ -111,6 +117,9 @@ def _validate_input_columns(flags_dict): from pybind11_abseil import status import tensorflow as tf +def is_mode_interference_graph(model_type): + return model_type == "PER_BB_LIVE_INFO" or model_type == "PER_FUNC_LIVE_INFO" + def main(argv: Sequence[str]) -> None: if len(argv) > 1: @@ -129,7 +138,11 @@ def main(argv: Sequence[str]) -> None: # LLVM triple. As of 2023-05, this is OK, because we support only x86-64 # anyway. canonicalizer_obj = canonicalizer.Canonicalizer.x86_64(llvm) - importer = bhive_importer.BHiveImporter(canonicalizer_obj) + if is_mode_interference_graph(_MODEL_TYPE.value): + logging.info('Creating BHiveImporter with interference graph %s', _MODEL_TYPE.value) + importer = bhive_importer.BHiveImporter(canonicalizer_obj, _MODEL_TYPE.value) + else: + importer = bhive_importer.BHiveImporter(canonicalizer_obj) with ( tf.io.TFRecordWriter(_OUTPUT_TFRECORD_FILE.value) as writer, @@ -153,11 +166,15 @@ def main(argv: Sequence[str]) -> None: mir_file = os.path.join(input_dir, filename) print("mir file is " + mir_file) perf_file = os.path.join(input_dir, filename.replace(".mir", ".perf")) + liveinfo_file = os.path.join(input_dir, filename + ".liveinfo") try: # load the MIR file - module = importer.LoadMIRModule(mir_file) - num_input_files += 1 logging.info('Procssing %s file', mir_file) + importer.LoadMIRModule(mir_file) + logging.info('Loading live info %s file', liveinfo_file) + # if is interference graph, then we need to load the liveinfo file + importer.parse_interference_graph(liveinfo_file) + num_input_files += 1 # iterate over each line in the corresponding .perf file with tf.io.gfile.GFile(perf_file, 'r') as bhive_csv_file: for line in bhive_csv_file: diff --git a/mir_input/test_mir_input/Activation.mir b/mir_input/test_mir_input/Activation.mir new file mode 100644 index 00000000..3c915be5 --- /dev/null +++ b/mir_input/test_mir_input/Activation.mir @@ -0,0 +1,7932 @@ +--- | + ; ModuleID = 'Activation.ll' + source_filename = "pytorch/aten/src/ATen/native/quantized/cuda/Activation.cpp" + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-pc-linux-gnu" + + %"struct.c10::UndefinedTensorImpl" = type { %"struct.c10::TensorImpl" } + %"struct.c10::TensorImpl" = type { %"class.c10::intrusive_ptr_target", %"struct.c10::Storage", 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= comdat any + + $_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2EPS1_NS_3raw20DontIncreaseRefcountE = comdat any + + $_ZN3c1017basic_string_viewIcE7strlen_EPKc = comdat any + + $_ZN3c1017basic_string_viewIcEC2EPKcm = comdat any + + $_ZNK3c1010TensorImpl5dtypeEv = comdat any + + $_ZN6caffe28TypeMeta12toScalarTypeEv = comdat any + + $_ZNK6caffe28TypeMeta12isScalarTypeEv = comdat any + + $_ZN2at10TensorBaseD2Ev = comdat any + + $_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEED2Ev = comdat any + + $_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEE6reset_Ev = comdat any + + $_ZN3c106detail25atomic_refcount_decrementERSt6atomicImE = comdat any + + $_ZN3c106detail26atomic_weakcount_decrementERSt6atomicImE = comdat any + + $_ZStanSt12memory_orderSt23__memory_order_modifier = comdat any + + $_ZNK2at6Tensor2gtERKN3c106ScalarE = comdat any + + $_ZN3c106ScalarC2IlLPb0EEET_b = comdat any + + $_ZN3c106Scalar3v_tC2Ev = comdat any + + $_ZN3c107convertIllEET_T0_ = comdat any + + $_ZN3c1027static_cast_with_inter_typeIllE5applyEl = comdat any + + $_ZN3c1010maybe_realILb0ElE5applyEl = comdat any + + $_ZN3c106Scalar7destroyEv = comdat any + + $_ZN3c103raw13intrusive_ptr6decrefEPNS_20intrusive_ptr_targetE = comdat any + + $_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_ = comdat any + + $_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEED2Ev = comdat any + + $_ZN3c106detail34intrusive_target_default_null_typeINS_20intrusive_ptr_targetEE9singletonEv = comdat any + + $_ZN3c103strIJA68_cEEEDcDpRKT_ = comdat any + + $_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEEC2EPS1_NS_3raw20DontIncreaseRefcountE = comdat any + + $_ZN3c106detail12_str_wrapperIJPKcEE4callES3_ = comdat any + + $_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE6reset_Ev = comdat any + + @.str = private unnamed_addr constant [5 x i8] c"none\00", align 1 + @_ZN3c1019UndefinedTensorImpl10_singletonE = external global %"struct.c10::UndefinedTensorImpl", align 8 + @__func__._ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_ = private unnamed_addr constant [8 x i8] c"reclaim\00", align 1 + @.str.1 = private unnamed_addr constant [53 x i8] c"/u9/z277zhu/granLte/pytorch/c10/util/intrusive_ptr.h\00", align 1 + @.str.2 = private unnamed_addr constant [225 x i8] c"owning_ptr == NullType::singleton() || owning_ptr->refcount_.load() == 0 || owning_ptr->weakcount_.load() INTERNAL ASSERT FAILED at \22/u9/z277zhu/granLte/pytorch/c10/util/intrusive_ptr.h\22:475, please report a bug to PyTorch. \00", align 1 + @.str.3 = private unnamed_addr constant [68 x i8] c"TTarget violates the invariant that refcount > 0 => weakcount > 0\00", align 1 + + ; Function Attrs: mustprogress noinline optnone uwtable + define dso_local void @_ZN2at6native19gelu_quantized_cudaERKNS_6TensorEN3c1017basic_string_viewIcEE(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1, ptr %2, i64 %3) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 { + BB_0: + call void asm sideeffect "# LLVM BB: BB_0", ""() + %4 = alloca ptr, align 8 + %5 = alloca %"class.c10::basic_string_view", align 8 + %6 = alloca ptr, align 8 + %7 = alloca %"class.at::Tensor", align 8 + %8 = alloca %"class.at::Tensor", align 8 + %9 = alloca %"class.c10::basic_string_view", align 8 + %10 = alloca ptr, align 8 + %11 = alloca i32, align 4 + %12 = bitcast ptr %0 to ptr + store ptr %12, ptr %4, align 8 + %13 = bitcast ptr %5 to ptr + %14 = getelementptr inbounds { ptr, i64 }, ptr %13, i32 0, i32 0 + store ptr %2, ptr %14, align 8 + %15 = getelementptr inbounds { ptr, i64 }, ptr %13, i32 0, i32 1 + store i64 %3, ptr %15, align 8 + store ptr %1, ptr %6, align 8 + %16 = load ptr, ptr %6, align 8 + %17 = bitcast ptr %16 to ptr + %18 = call noundef i64 @_ZNK2at10TensorBase5numelEv(ptr noundef nonnull align 8 dereferenceable(8) %17) + %19 = icmp eq i64 %18, 0 + br i1 %19, label %BB_1, label %BB_2 + + BB_1: ; preds = %BB_0 + call void asm sideeffect "# LLVM BB: BB_1", ""() + %20 = bitcast ptr %0 to ptr + call void @llvm.memset.p0.i64(ptr align 8 %20, i8 0, i64 8, i1 false) + call void @_ZN2at6TensorC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) #9 + br label %BB_12 + + BB_2: ; preds = %BB_0 + call void asm sideeffect "# LLVM BB: BB_2", ""() + %21 = load ptr, ptr %6, align 8 + call void @_ZN2at10dequantizeERKNS_6TensorE(ptr sret(%"class.at::Tensor") align 8 %7, ptr noundef nonnull align 8 dereferenceable(8) %21) + invoke void @_ZN3c1017basic_string_viewIcEC2EPKc(ptr noundef nonnull align 8 dereferenceable(16) %9, ptr noundef @.str) + to label %BB_3 unwind label %BB_9 + + BB_3: ; preds = %BB_2 + call void asm sideeffect "# LLVM BB: BB_3", ""() + %22 = bitcast ptr %9 to ptr + %23 = getelementptr inbounds { ptr, i64 }, ptr %22, i32 0, i32 0 + %24 = load ptr, ptr %23, align 8 + %25 = getelementptr inbounds { ptr, i64 }, ptr %22, i32 0, i32 1 + %26 = load i64, ptr %25, align 8 + invoke void @_ZN2at4geluERKNS_6TensorEN3c1017basic_string_viewIcEE(ptr sret(%"class.at::Tensor") align 8 %8, ptr noundef nonnull align 8 dereferenceable(8) %7, ptr %24, i64 %26) + to label %BB_4 unwind label %BB_9 + + BB_4: ; preds = %BB_3 + call void asm sideeffect "# LLVM BB: BB_4", ""() + %27 = load ptr, ptr %6, align 8 + %28 = invoke noundef double @_ZNK2at6Tensor7q_scaleEv(ptr noundef nonnull align 8 dereferenceable(8) %27) + to label %BB_5 unwind label %BB_10 + + BB_5: ; preds = %BB_4 + call void asm sideeffect "# LLVM BB: BB_5", ""() + %29 = load ptr, ptr %6, align 8 + %30 = invoke noundef i64 @_ZNK2at6Tensor12q_zero_pointEv(ptr noundef nonnull align 8 dereferenceable(8) %29) + to label %BB_6 unwind label %BB_10 + + BB_6: ; preds = %BB_5 + call void asm sideeffect "# LLVM BB: BB_6", ""() + %31 = load ptr, ptr %6, align 8 + %32 = bitcast ptr %31 to ptr + %33 = invoke noundef signext i8 @_ZNK2at10TensorBase11scalar_typeEv(ptr noundef nonnull align 8 dereferenceable(8) %32) + to label %BB_7 unwind label %BB_10 + + BB_7: ; preds = %BB_6 + call void asm sideeffect "# LLVM BB: BB_7", ""() + invoke void @_ZN2at19quantize_per_tensorERKNS_6TensorEdlN3c1010ScalarTypeE(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %8, double noundef %28, i64 noundef %30, i8 noundef signext %33) + to label %BB_8 unwind label %BB_10 + + BB_8: ; preds = %BB_7 + call void asm sideeffect "# LLVM BB: BB_8", ""() + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %8) #9 + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %7) #9 + br label %BB_12 + + BB_9: ; preds = %BB_3, %BB_2 + %34 = landingpad { ptr, i32 } + cleanup + call void asm sideeffect "# LLVM BB: BB_9", ""() + %35 = extractvalue { ptr, i32 } %34, 0 + store ptr %35, ptr %10, align 8 + %36 = extractvalue { ptr, i32 } %34, 1 + store i32 %36, ptr %11, align 4 + br label %BB_11 + + BB_10: ; preds = %BB_7, %BB_6, %BB_5, %BB_4 + %37 = landingpad { ptr, i32 } + cleanup + call void asm sideeffect "# LLVM BB: BB_10", ""() + %38 = extractvalue { ptr, i32 } %37, 0 + store ptr %38, ptr %10, align 8 + %39 = extractvalue { ptr, i32 } %37, 1 + store i32 %39, ptr %11, align 4 + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %8) #9 + br label %BB_11 + + BB_11: ; preds = %BB_10, %BB_9 + call void asm sideeffect "# LLVM BB: BB_11", ""() + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %7) #9 + br label %BB_13 + + BB_12: ; preds = %BB_8, %BB_1 + call void asm sideeffect "# LLVM BB: BB_12", ""() + ret void + + BB_13: ; preds = %BB_11 + call void asm sideeffect "# LLVM BB: BB_13", ""() + %40 = load ptr, ptr %10, align 8 + call void @_Unwind_Resume(ptr %40) #10 + unreachable + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZNK2at10TensorBase5numelEv(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #0 comdat align 2 { + BB_14: + call void asm sideeffect "# LLVM BB: BB_14", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = getelementptr inbounds %"class.at::TensorBase", ptr %2, i32 0, i32 0 + %4 = call noundef ptr @_ZNK3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEptEv(ptr noundef nonnull align 8 dereferenceable(8) %3) #9 + %5 = call noundef i64 @_ZNK3c1010TensorImpl5numelEv(ptr noundef nonnull align 8 dereferenceable(192) %4) + ret i64 %5 + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN2at6TensorC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) unnamed_addr #1 comdat align 2 { + BB_15: + call void asm sideeffect "# LLVM BB: BB_15", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = bitcast ptr %2 to ptr + call void @_ZN2at10TensorBaseC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %3) #9 + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZN2at10dequantizeERKNS_6TensorE(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1) local_unnamed_addr #0 comdat { + BB_16: + call void asm sideeffect "# LLVM BB: BB_16", ""() + %2 = alloca ptr, align 8 + %3 = alloca ptr, align 8 + %4 = bitcast ptr %0 to ptr + store ptr %4, ptr %2, align 8 + store ptr %1, ptr %3, align 8 + %5 = load ptr, ptr %3, align 8 + call void @_ZN2at4_ops15dequantize_self4callERKNS_6TensorE(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %5) + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZN2at4geluERKNS_6TensorEN3c1017basic_string_viewIcEE(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1, ptr %2, i64 %3) local_unnamed_addr #0 comdat { + BB_17: + call void asm sideeffect "# LLVM BB: BB_17", ""() + %4 = alloca ptr, align 8 + %5 = alloca %"class.c10::basic_string_view", align 8 + %6 = alloca ptr, align 8 + %7 = alloca %"class.c10::basic_string_view", align 8 + %8 = bitcast ptr %0 to ptr + store ptr %8, ptr %4, align 8 + %9 = bitcast ptr %5 to ptr + %10 = getelementptr inbounds { ptr, i64 }, ptr %9, i32 0, i32 0 + store ptr %2, ptr %10, align 8 + %11 = getelementptr inbounds { ptr, i64 }, ptr %9, i32 0, i32 1 + store i64 %3, ptr %11, align 8 + store ptr %1, ptr %6, align 8 + %12 = load ptr, ptr %6, align 8 + %13 = bitcast ptr %7 to ptr + %14 = bitcast ptr %5 to ptr + call void @llvm.memcpy.p0.p0.i64(ptr align 8 %13, ptr align 8 %14, i64 16, i1 false) + %15 = bitcast ptr %7 to ptr + %16 = getelementptr inbounds { ptr, i64 }, ptr %15, i32 0, i32 0 + %17 = load ptr, ptr %16, align 8 + %18 = getelementptr inbounds { ptr, i64 }, ptr %15, i32 0, i32 1 + %19 = load i64, ptr %18, align 8 + call void @_ZN2at4_ops4gelu4callERKNS_6TensorEN3c1017basic_string_viewIcEE(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %12, ptr %17, i64 %19) + ret void + } + + ; Function Attrs: noinline optnone uwtable + define linkonce_odr dso_local void @_ZN3c1017basic_string_viewIcEC2EPKc(ptr noundef nonnull align 8 dereferenceable(16) %0, ptr noundef %1) unnamed_addr #2 comdat align 2 { + BB_18: + call void asm sideeffect "# LLVM BB: BB_18", ""() + %2 = alloca ptr, align 8 + %3 = alloca ptr, align 8 + store ptr %0, ptr %2, align 8 + store ptr %1, ptr %3, align 8 + %4 = load ptr, ptr %2, align 8 + %5 = load ptr, ptr %3, align 8 + %6 = load ptr, ptr %3, align 8 + %7 = call noundef i64 @_ZN3c1017basic_string_viewIcE7strlen_EPKc(ptr noundef %6) #9 + call void @_ZN3c1017basic_string_viewIcEC2EPKcm(ptr noundef nonnull align 8 dereferenceable(16) %4, ptr noundef %5, i64 noundef %7) + ret void + } + + declare i32 @__gxx_personality_v0(...) + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZN2at19quantize_per_tensorERKNS_6TensorEdlN3c1010ScalarTypeE(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1, double noundef %2, i64 noundef %3, i8 noundef signext %4) local_unnamed_addr #0 comdat { + BB_19: + call void asm sideeffect "# LLVM BB: BB_19", ""() + %5 = alloca ptr, align 8 + %6 = alloca ptr, align 8 + %7 = alloca double, align 8 + %8 = alloca i64, align 8 + %9 = alloca i8, align 1 + %10 = bitcast ptr %0 to ptr + store ptr %10, ptr %5, align 8 + store ptr %1, ptr %6, align 8 + store double %2, ptr %7, align 8 + store i64 %3, ptr %8, align 8 + store i8 %4, ptr %9, align 1 + %11 = load ptr, ptr %6, align 8 + %12 = load double, ptr %7, align 8 + %13 = load i64, ptr %8, align 8 + %14 = load i8, ptr %9, align 1 + call void @_ZN2at4_ops19quantize_per_tensor4callERKNS_6TensorEdlN3c1010ScalarTypeE(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %11, double noundef %12, i64 noundef %13, i8 noundef signext %14) + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef double @_ZNK2at6Tensor7q_scaleEv(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #0 comdat align 2 { + BB_20: + call void asm sideeffect "# LLVM BB: BB_20", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = call noundef double @_ZN2at4_ops7q_scale4callERKNS_6TensorE(ptr noundef nonnull align 8 dereferenceable(8) %2) + ret double %3 + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZNK2at6Tensor12q_zero_pointEv(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #0 comdat align 2 { + BB_21: + call void asm sideeffect "# LLVM BB: BB_21", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = call noundef i64 @_ZN2at4_ops12q_zero_point4callERKNS_6TensorE(ptr noundef nonnull align 8 dereferenceable(8) %2) + ret i64 %3 + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef signext i8 @_ZNK2at10TensorBase11scalar_typeEv(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #0 comdat align 2 { + BB_22: + call void asm sideeffect "# LLVM BB: BB_22", ""() + %1 = alloca ptr, align 8 + %2 = alloca %"class.caffe2::TypeMeta", align 2 + store ptr %0, ptr %1, align 8 + %3 = load ptr, ptr %1, align 8 + %4 = getelementptr inbounds %"class.at::TensorBase", ptr %3, i32 0, i32 0 + %5 = call noundef ptr @_ZNK3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEptEv(ptr noundef nonnull align 8 dereferenceable(8) %4) #9 + %6 = call i16 @_ZNK3c1010TensorImpl5dtypeEv(ptr noundef nonnull align 8 dereferenceable(192) %5) + %7 = getelementptr inbounds %"class.caffe2::TypeMeta", ptr %2, i32 0, i32 0 + store i16 %6, ptr %7, align 2 + %8 = getelementptr inbounds %"class.caffe2::TypeMeta", ptr %2, i32 0, i32 0 + %9 = load i16, ptr %8, align 2 + %10 = call fastcc noundef signext i8 @_ZN3c10L20typeMetaToScalarTypeEN6caffe28TypeMetaE(i16 %9) + ret i8 %10 + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) unnamed_addr #1 comdat align 2 { + BB_23: + call void asm sideeffect "# LLVM BB: BB_23", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = bitcast ptr %2 to ptr + call void @_ZN2at10TensorBaseD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %3) #9 + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define dso_local void @_ZN2at6native19relu_quantized_cudaERKNS_6TensorE(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1) local_unnamed_addr #0 personality ptr @__gxx_personality_v0 { + BB_24: + call void asm sideeffect "# LLVM BB: BB_24", ""() + %2 = alloca ptr, align 8 + %3 = alloca ptr, align 8 + %4 = alloca i64, align 8 + %5 = alloca %"class.at::Tensor", align 8 + %6 = alloca %"class.at::Tensor", align 8 + %7 = alloca %"class.c10::Scalar", align 16 + %8 = alloca ptr, align 8 + %9 = alloca i32, align 4 + %10 = alloca %"class.at::Tensor", align 8 + %11 = alloca %"class.c10::Scalar", align 16 + %12 = bitcast ptr %0 to ptr + store ptr %12, ptr %2, align 8 + store ptr %1, ptr %3, align 8 + %13 = load ptr, ptr %3, align 8 + %14 = call noundef i64 @_ZNK2at6Tensor12q_zero_pointEv(ptr noundef nonnull align 8 dereferenceable(8) %13) + store i64 %14, ptr %4, align 8 + %15 = load ptr, ptr %3, align 8 + call void @_ZNK2at6Tensor8int_reprEv(ptr sret(%"class.at::Tensor") align 8 %5, ptr noundef nonnull align 8 dereferenceable(8) %15) + %16 = load i64, ptr %4, align 8 + invoke void @_ZN3c106ScalarC2El(ptr noundef nonnull align 16 dereferenceable(32) %7, i64 noundef %16) + to label %BB_25 unwind label %BB_31 + + BB_25: ; preds = %BB_24 + call void asm sideeffect "# LLVM BB: BB_25", ""() + invoke fastcc void @_ZN2atgtERKNS_6TensorERKN3c106ScalarE(ptr noalias align 8 %6, ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 16 dereferenceable(32) %7) + to label %BB_26 unwind label %BB_32 + + BB_26: ; preds = %BB_25 + call void asm sideeffect "# LLVM BB: BB_26", ""() + call void @_ZN3c106ScalarD2Ev(ptr noundef nonnull align 16 dereferenceable(32) %7) #9 + %17 = load i64, ptr %4, align 8 + invoke void @_ZN3c106ScalarC2El(ptr noundef nonnull align 16 dereferenceable(32) %11, i64 noundef %17) + to label %BB_27 unwind label %BB_33 + + BB_27: ; preds = %BB_26 + call void asm sideeffect "# LLVM BB: BB_27", ""() + invoke void @_ZN2at5whereERKNS_6TensorES2_RKN3c106ScalarE(ptr sret(%"class.at::Tensor") align 8 %10, ptr noundef nonnull align 8 dereferenceable(8) %6, ptr noundef nonnull align 8 dereferenceable(8) %5, ptr noundef nonnull align 16 dereferenceable(32) %11) + to label %BB_28 unwind label %BB_34 + + BB_28: ; preds = %BB_27 + call void asm sideeffect "# LLVM BB: BB_28", ""() + call void @_ZN3c106ScalarD2Ev(ptr noundef nonnull align 16 dereferenceable(32) %11) #9 + %18 = load ptr, ptr %3, align 8 + %19 = invoke noundef double @_ZNK2at6Tensor7q_scaleEv(ptr noundef nonnull align 8 dereferenceable(8) %18) + to label %BB_29 unwind label %BB_35 + + BB_29: ; preds = %BB_28 + call void asm sideeffect "# LLVM BB: BB_29", ""() + %20 = load i64, ptr %4, align 8 + invoke void @_ZN2at33_make_per_tensor_quantized_tensorERKNS_6TensorEdl(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %10, double noundef %19, i64 noundef %20) + to label %BB_30 unwind label %BB_35 + + BB_30: ; preds = %BB_29 + call void asm sideeffect "# LLVM BB: BB_30", ""() + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %10) #9 + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %6) #9 + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %5) #9 + ret void + + BB_31: ; preds = %BB_24 + %21 = landingpad { ptr, i32 } + cleanup + call void asm sideeffect "# LLVM BB: BB_31", ""() + %22 = extractvalue { ptr, i32 } %21, 0 + store ptr %22, ptr %8, align 8 + %23 = extractvalue { ptr, i32 } %21, 1 + store i32 %23, ptr %9, align 4 + br label %BB_37 + + BB_32: ; preds = %BB_25 + %24 = landingpad { ptr, i32 } + cleanup + call void asm sideeffect "# LLVM BB: BB_32", ""() + %25 = extractvalue { ptr, i32 } %24, 0 + store ptr %25, ptr %8, align 8 + %26 = extractvalue { ptr, i32 } %24, 1 + store i32 %26, ptr %9, align 4 + call void @_ZN3c106ScalarD2Ev(ptr noundef nonnull align 16 dereferenceable(32) %7) #9 + br label %BB_37 + + BB_33: ; preds = %BB_26 + %27 = landingpad { ptr, i32 } + cleanup + call void asm sideeffect "# LLVM BB: BB_33", ""() + %28 = extractvalue { ptr, i32 } %27, 0 + store ptr %28, ptr %8, align 8 + %29 = extractvalue { ptr, i32 } %27, 1 + store i32 %29, ptr %9, align 4 + br label %BB_36 + + BB_34: ; preds = %BB_27 + %30 = landingpad { ptr, i32 } + cleanup + call void asm sideeffect "# LLVM BB: BB_34", ""() + %31 = extractvalue { ptr, i32 } %30, 0 + store ptr %31, ptr %8, align 8 + %32 = extractvalue { ptr, i32 } %30, 1 + store i32 %32, ptr %9, align 4 + call void @_ZN3c106ScalarD2Ev(ptr noundef nonnull align 16 dereferenceable(32) %11) #9 + br label %BB_36 + + BB_35: ; preds = %BB_29, %BB_28 + %33 = landingpad { ptr, i32 } + cleanup + call void asm sideeffect "# LLVM BB: BB_35", ""() + %34 = extractvalue { ptr, i32 } %33, 0 + store ptr %34, ptr %8, align 8 + %35 = extractvalue { ptr, i32 } %33, 1 + store i32 %35, ptr %9, align 4 + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %10) #9 + br label %BB_36 + + BB_36: ; preds = %BB_35, %BB_34, %BB_33 + call void asm sideeffect "# LLVM BB: BB_36", ""() + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %6) #9 + br label %BB_37 + + BB_37: ; preds = %BB_36, %BB_32, %BB_31 + call void asm sideeffect "# LLVM BB: BB_37", ""() + call void @_ZN2at6TensorD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %5) #9 + br label %BB_38 + + BB_38: ; preds = %BB_37 + call void asm sideeffect "# LLVM BB: BB_38", ""() + %36 = load ptr, ptr %8, align 8 + call void @_Unwind_Resume(ptr %36) #10 + unreachable + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZNK2at6Tensor8int_reprEv(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1) local_unnamed_addr #0 comdat align 2 { + BB_39: + call void asm sideeffect "# LLVM BB: BB_39", ""() + %2 = alloca ptr, align 8 + %3 = alloca ptr, align 8 + %4 = bitcast ptr %0 to ptr + store ptr %4, ptr %2, align 8 + store ptr %1, ptr %3, align 8 + %5 = load ptr, ptr %3, align 8 + call void @_ZN2at4_ops8int_repr4callERKNS_6TensorE(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %5) + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define internal fastcc void @_ZN2atgtERKNS_6TensorERKN3c106ScalarE(ptr noalias align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 16 dereferenceable(32) %2) unnamed_addr #0 { + BB_40: + call void asm sideeffect "# LLVM BB: BB_40", ""() + %3 = alloca ptr, align 8 + %4 = alloca ptr, align 8 + %5 = alloca ptr, align 8 + %6 = bitcast ptr %0 to ptr + store ptr %6, ptr %3, align 8 + store ptr %1, ptr %4, align 8 + store ptr %2, ptr %5, align 8 + %7 = load ptr, ptr %4, align 8 + %8 = load ptr, ptr %5, align 8 + call void @_ZNK2at6Tensor2gtERKN3c106ScalarE(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %7, ptr noundef nonnull align 16 dereferenceable(32) %8) + ret void + } + + ; Function Attrs: noinline optnone uwtable + define linkonce_odr dso_local void @_ZN3c106ScalarC2El(ptr noundef nonnull align 16 dereferenceable(32) %0, i64 noundef %1) unnamed_addr #2 comdat align 2 { + BB_41: + call void asm sideeffect "# LLVM BB: BB_41", ""() + %2 = alloca ptr, align 8 + %3 = alloca i64, align 8 + store ptr %0, ptr %2, align 8 + store i64 %1, ptr %3, align 8 + %4 = load ptr, ptr %2, align 8 + %5 = load i64, ptr %3, align 8 + call void @_ZN3c106ScalarC2IlLPb0EEET_b(ptr noundef nonnull align 16 dereferenceable(32) %4, i64 noundef %5, i1 noundef zeroext true) + ret void + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c106ScalarD2Ev(ptr noundef nonnull align 16 dereferenceable(32) %0) unnamed_addr #1 comdat align 2 personality ptr @__gxx_personality_v0 { + BB_42: + call void asm sideeffect "# LLVM BB: BB_42", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + invoke void @_ZN3c106Scalar7destroyEv(ptr noundef nonnull align 16 dereferenceable(32) %2) + to label %BB_43 unwind label %BB_44 + + BB_43: ; preds = %BB_42 + call void asm sideeffect "# LLVM BB: BB_43", ""() + ret void + + BB_44: ; preds = %BB_42 + %3 = landingpad { ptr, i32 } + catch ptr null + call void asm sideeffect "# LLVM BB: BB_44", ""() + %4 = extractvalue { ptr, i32 } %3, 0 + call void @__clang_call_terminate(ptr %4) #11 + unreachable + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZN2at5whereERKNS_6TensorES2_RKN3c106ScalarE(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 8 dereferenceable(8) %2, ptr noundef nonnull align 16 dereferenceable(32) %3) local_unnamed_addr #0 comdat { + BB_45: + call void asm sideeffect "# LLVM BB: BB_45", ""() + %4 = alloca ptr, align 8 + %5 = alloca ptr, align 8 + %6 = alloca ptr, align 8 + %7 = alloca ptr, align 8 + %8 = bitcast ptr %0 to ptr + store ptr %8, ptr %4, align 8 + store ptr %1, ptr %5, align 8 + store ptr %2, ptr %6, align 8 + store ptr %3, ptr %7, align 8 + %9 = load ptr, ptr %5, align 8 + %10 = load ptr, ptr %6, align 8 + %11 = load ptr, ptr %7, align 8 + call void @_ZN2at4_ops17where_ScalarOther4callERKNS_6TensorES4_RKN3c106ScalarE(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %9, ptr noundef nonnull align 8 dereferenceable(8) %10, ptr noundef nonnull align 16 dereferenceable(32) %11) + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZN2at33_make_per_tensor_quantized_tensorERKNS_6TensorEdl(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1, double noundef %2, i64 noundef %3) local_unnamed_addr #0 comdat { + BB_46: + call void asm sideeffect "# LLVM BB: BB_46", ""() + %4 = alloca ptr, align 8 + %5 = alloca ptr, align 8 + %6 = alloca double, align 8 + %7 = alloca i64, align 8 + %8 = bitcast ptr %0 to ptr + store ptr %8, ptr %4, align 8 + store ptr %1, ptr %5, align 8 + store double %2, ptr %6, align 8 + store i64 %3, ptr %7, align 8 + %9 = load ptr, ptr %5, align 8 + %10 = load double, ptr %6, align 8 + %11 = load i64, ptr %7, align 8 + call void @_ZN2at4_ops33_make_per_tensor_quantized_tensor4callERKNS_6TensorEdl(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %9, double noundef %10, i64 noundef %11) + ret void + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef ptr @_ZNK3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEptEv(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #3 comdat align 2 { + BB_47: + call void asm sideeffect "# LLVM BB: BB_47", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = getelementptr inbounds %"class.c10::intrusive_ptr", ptr %2, i32 0, i32 0 + %4 = load ptr, ptr %3, align 8 + ret ptr %4 + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZNK3c1010TensorImpl5numelEv(ptr noundef nonnull align 8 dereferenceable(192) %0) local_unnamed_addr #0 comdat align 2 { + BB_48: + call void asm sideeffect "# LLVM BB: BB_48", ""() + %1 = alloca i64, align 8 + %2 = alloca ptr, align 8 + store ptr %0, ptr %2, align 8 + %3 = load ptr, ptr %2, align 8 + %4 = call noundef zeroext i1 @_ZNK3c1010TensorImpl14matches_policyENS0_18SizesStridesPolicyE(ptr noundef nonnull align 8 dereferenceable(192) %3, i8 noundef zeroext 2) + br i1 %4, label %BB_49, label %BB_50 + + BB_49: ; preds = %BB_48 + call void asm sideeffect "# LLVM BB: BB_49", ""() + %5 = bitcast ptr %3 to ptr + %6 = load ptr, ptr %5, align 8 + %7 = getelementptr inbounds ptr, ptr %6, i64 10 + %8 = load ptr, ptr %7, align 8 + %9 = call noundef i64 %8(ptr noundef nonnull align 8 dereferenceable(192) %3) + store i64 %9, ptr %1, align 8 + br label %BB_51 + + BB_50: ; preds = %BB_48 + call void asm sideeffect "# LLVM BB: BB_50", ""() + %10 = getelementptr inbounds %"struct.c10::TensorImpl", ptr %3, i32 0, i32 8 + %11 = load i64, ptr %10, align 8 + store i64 %11, ptr %1, align 8 + br label %BB_51 + + BB_51: ; preds = %BB_50, %BB_49 + call void asm sideeffect "# LLVM BB: BB_51", ""() + %12 = load i64, ptr %1, align 8 + ret i64 %12 + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef zeroext i1 @_ZNK3c1010TensorImpl14matches_policyENS0_18SizesStridesPolicyE(ptr noundef nonnull align 8 dereferenceable(192) %0, i8 noundef zeroext %1) local_unnamed_addr #3 comdat align 2 { + BB_52: + call void asm sideeffect "# LLVM BB: BB_52", ""() + %2 = alloca ptr, align 8 + %3 = alloca i8, align 1 + store ptr %0, ptr %2, align 8 + store i8 %1, ptr %3, align 1 + %4 = load ptr, ptr %2, align 8 + %5 = getelementptr inbounds %"struct.c10::TensorImpl", ptr %4, i32 0, i32 11 + %6 = bitcast ptr %5 to ptr + %7 = load i24, ptr %6, align 1 + %8 = lshr i24 %7, 10 + %9 = and i24 %8, 3 + %10 = trunc i24 %9 to i8 + %11 = zext i8 %10 to i32 + %12 = load i8, ptr %3, align 1 + %13 = zext i8 %12 to i32 + %14 = icmp sge i32 %11, %13 + ret i1 %14 + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN2at10TensorBaseC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) unnamed_addr #1 comdat align 2 { + BB_53: + call void asm sideeffect "# LLVM BB: BB_53", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = getelementptr inbounds %"class.at::TensorBase", ptr %2, i32 0, i32 0 + call void @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %3) #9 + ret void + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) unnamed_addr #1 comdat align 2 personality ptr @__gxx_personality_v0 { + BB_54: + call void asm sideeffect "# LLVM BB: BB_54", ""() + %1 = alloca ptr, align 8 + %2 = alloca %"struct.c10::raw::DontIncreaseRefcount", align 1 + store ptr %0, ptr %1, align 8 + %3 = load ptr, ptr %1, align 8 + %4 = call noundef ptr @_ZN3c1019UndefinedTensorImpl9singletonEv() + br label %BB_55 + + BB_55: ; preds = %BB_54 + call void asm sideeffect "# LLVM BB: BB_55", ""() + call void @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2EPS1_NS_3raw20DontIncreaseRefcountE(ptr noundef nonnull align 8 dereferenceable(8) %3, ptr noundef %4) #9 + ret void + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef ptr @_ZN3c1019UndefinedTensorImpl9singletonEv() local_unnamed_addr #3 comdat align 2 { + BB_56: + call void asm sideeffect "# LLVM BB: BB_56", ""() + ret ptr @_ZN3c1019UndefinedTensorImpl10_singletonE + } + + ; Function Attrs: noinline noreturn nounwind + define linkonce_odr hidden void @__clang_call_terminate(ptr %0) local_unnamed_addr #4 comdat { + BB_57: + call void asm sideeffect "# LLVM BB: BB_57", ""() + %1 = tail call ptr @__cxa_begin_catch(ptr %0) #9 + tail call void @_ZSt9terminatev() #11 + unreachable + } + + declare ptr @__cxa_begin_catch(ptr) local_unnamed_addr + + declare void @_ZSt9terminatev() local_unnamed_addr + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2EPS1_NS_3raw20DontIncreaseRefcountE(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef %1) unnamed_addr #1 comdat align 2 { + BB_58: + call void asm sideeffect "# LLVM BB: BB_58", ""() + %2 = alloca %"struct.c10::raw::DontIncreaseRefcount", align 1 + %3 = alloca ptr, align 8 + %4 = alloca ptr, align 8 + store ptr %0, ptr %3, align 8 + store ptr %1, ptr %4, align 8 + %5 = load ptr, ptr %3, align 8 + %6 = getelementptr inbounds %"class.c10::intrusive_ptr", ptr %5, i32 0, i32 0 + %7 = load ptr, ptr %4, align 8 + store ptr %7, ptr %6, align 8 + ret void + } + + declare void @_ZN2at4_ops15dequantize_self4callERKNS_6TensorE(ptr sret(%"class.at::Tensor") align 8, ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #5 + + declare void @_ZN2at4_ops4gelu4callERKNS_6TensorEN3c1017basic_string_viewIcEE(ptr sret(%"class.at::Tensor") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr, i64) local_unnamed_addr #5 + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZN3c1017basic_string_viewIcE7strlen_EPKc(ptr noundef %0) local_unnamed_addr #3 comdat align 2 { + BB_59: + call void asm sideeffect "# LLVM BB: BB_59", ""() + %1 = alloca ptr, align 8 + %2 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %3 = load ptr, ptr %1, align 8 + store ptr %3, ptr %2, align 8 + br label %BB_60 + + BB_60: ; preds = %BB_61, %BB_59 + call void asm sideeffect "# LLVM BB: BB_60", ""() + %4 = load ptr, ptr %2, align 8 + %5 = load i8, ptr %4, align 1 + %6 = sext i8 %5 to i32 + %7 = icmp ne i32 %6, 0 + br i1 %7, label %BB_61, label %BB_62 + + BB_61: ; preds = %BB_60 + call void asm sideeffect "# LLVM BB: BB_61", ""() + %8 = load ptr, ptr %2, align 8 + %9 = getelementptr inbounds i8, ptr %8, i32 1 + store ptr %9, ptr %2, align 8 + br label %BB_60, !llvm.loop !6 + + BB_62: ; preds = %BB_60 + call void asm sideeffect "# LLVM BB: BB_62", ""() + %10 = load ptr, ptr %2, align 8 + %11 = load ptr, ptr %1, align 8 + %12 = ptrtoint ptr %10 to i64 + %13 = ptrtoint ptr %11 to i64 + %14 = sub i64 %12, %13 + ret i64 %14 + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c1017basic_string_viewIcEC2EPKcm(ptr noundef nonnull align 8 dereferenceable(16) %0, ptr noundef %1, i64 noundef %2) unnamed_addr #1 comdat align 2 { + BB_63: + call void asm sideeffect "# LLVM BB: BB_63", ""() + %3 = alloca ptr, align 8 + %4 = alloca ptr, align 8 + %5 = alloca i64, align 8 + store ptr %0, ptr %3, align 8 + store ptr %1, ptr %4, align 8 + store i64 %2, ptr %5, align 8 + %6 = load ptr, ptr %3, align 8 + %7 = getelementptr inbounds %"class.c10::basic_string_view", ptr %6, i32 0, i32 0 + %8 = load ptr, ptr %4, align 8 + store ptr %8, ptr %7, align 8 + %9 = getelementptr inbounds %"class.c10::basic_string_view", ptr %6, i32 0, i32 1 + %10 = load i64, ptr %5, align 8 + store i64 %10, ptr %9, align 8 + ret void + } + + declare void @_ZN2at4_ops19quantize_per_tensor4callERKNS_6TensorEdlN3c1010ScalarTypeE(ptr sret(%"class.at::Tensor") align 8, ptr noundef nonnull align 8 dereferenceable(8), double noundef, i64 noundef, i8 noundef signext) local_unnamed_addr #5 + + declare noundef double @_ZN2at4_ops7q_scale4callERKNS_6TensorE(ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #5 + + declare noundef i64 @_ZN2at4_ops12q_zero_point4callERKNS_6TensorE(ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #5 + + ; Function Attrs: mustprogress noinline optnone uwtable + define internal fastcc noundef signext i8 @_ZN3c10L20typeMetaToScalarTypeEN6caffe28TypeMetaE(i16 %0) unnamed_addr #0 { + BB_64: + call void asm sideeffect "# LLVM BB: BB_64", ""() + %1 = alloca %"class.caffe2::TypeMeta", align 2 + %2 = getelementptr inbounds %"class.caffe2::TypeMeta", ptr %1, i32 0, i32 0 + store i16 %0, ptr %2, align 2 + %3 = call noundef signext i8 @_ZN6caffe28TypeMeta12toScalarTypeEv(ptr noundef nonnull align 2 dereferenceable(2) %1) + ret i8 %3 + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local i16 @_ZNK3c1010TensorImpl5dtypeEv(ptr noundef nonnull align 8 dereferenceable(192) %0) local_unnamed_addr #3 comdat align 2 { + BB_65: + call void asm sideeffect "# LLVM BB: BB_65", ""() + %1 = alloca %"class.caffe2::TypeMeta", align 2 + %2 = alloca ptr, align 8 + store ptr %0, ptr %2, align 8 + %3 = load ptr, ptr %2, align 8 + %4 = getelementptr inbounds %"struct.c10::TensorImpl", ptr %3, i32 0, i32 9 + %5 = bitcast ptr %1 to ptr + %6 = bitcast ptr %4 to ptr + call void @llvm.memcpy.p0.p0.i64(ptr align 2 %5, ptr align 8 %6, i64 2, i1 false) + %7 = getelementptr inbounds %"class.caffe2::TypeMeta", ptr %1, i32 0, i32 0 + %8 = load i16, ptr %7, align 2 + ret i16 %8 + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef signext i8 @_ZN6caffe28TypeMeta12toScalarTypeEv(ptr noundef nonnull align 2 dereferenceable(2) %0) local_unnamed_addr #0 comdat align 2 { + BB_66: + call void asm sideeffect "# LLVM BB: BB_66", ""() + %1 = alloca ptr, align 8 + %2 = alloca %"class.caffe2::TypeMeta", align 2 + store ptr %0, ptr %1, align 8 + %3 = load ptr, ptr %1, align 8 + %4 = call noundef zeroext i1 @_ZNK6caffe28TypeMeta12isScalarTypeEv(ptr noundef nonnull align 2 dereferenceable(2) %3) #9 + br i1 %4, label %BB_67, label %BB_68 + + BB_67: ; preds = %BB_66 + call void asm sideeffect "# LLVM BB: BB_67", ""() + %5 = getelementptr inbounds %"class.caffe2::TypeMeta", ptr %3, i32 0, i32 0 + %6 = load i16, ptr %5, align 2 + %7 = trunc i16 %6 to i8 + ret i8 %7 + + BB_68: ; preds = %BB_66 + call void asm sideeffect "# LLVM BB: BB_68", ""() + %8 = bitcast ptr %2 to ptr + %9 = bitcast ptr %3 to ptr + call void @llvm.memcpy.p0.p0.i64(ptr align 2 %8, ptr align 2 %9, i64 2, i1 false) + %10 = getelementptr inbounds %"class.caffe2::TypeMeta", ptr %2, i32 0, i32 0 + %11 = load i16, ptr %10, align 2 + call void @_ZN6caffe28TypeMeta26error_unsupported_typemetaES0_(i16 %11) #10 + unreachable + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef zeroext i1 @_ZNK6caffe28TypeMeta12isScalarTypeEv(ptr noundef nonnull align 2 dereferenceable(2) %0) local_unnamed_addr #3 comdat align 2 { + BB_69: + call void asm sideeffect "# LLVM BB: BB_69", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = getelementptr inbounds %"class.caffe2::TypeMeta", ptr %2, i32 0, i32 0 + %4 = load i16, ptr %3, align 2 + %5 = zext i16 %4 to i32 + %6 = icmp slt i32 %5, 26 + ret i1 %6 + } + + ; Function Attrs: noreturn + declare void @_ZN6caffe28TypeMeta26error_unsupported_typemetaES0_(i16) local_unnamed_addr #6 + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN2at10TensorBaseD2Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) unnamed_addr #1 comdat align 2 { + BB_70: + call void asm sideeffect "# LLVM BB: BB_70", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = getelementptr inbounds %"class.at::TensorBase", ptr %2, i32 0, i32 0 + call void @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEED2Ev(ptr noundef nonnull align 8 dereferenceable(8) %3) #9 + ret void + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEED2Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) unnamed_addr #1 comdat align 2 { + BB_71: + call void asm sideeffect "# LLVM BB: BB_71", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + call void @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEE6reset_Ev(ptr noundef nonnull align 8 dereferenceable(8) %2) #9 + ret void + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEE6reset_Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #3 comdat align 2 personality ptr @__gxx_personality_v0 { + BB_72: + call void asm sideeffect "# LLVM BB: BB_72", ""() + %1 = alloca ptr, align 8 + %2 = alloca i32, align 4 + %3 = alloca i32, align 4 + %4 = alloca i64, align 8 + %5 = alloca ptr, align 8 + %6 = alloca i8, align 1 + store ptr %0, ptr %5, align 8 + %7 = load ptr, ptr %5, align 8 + %8 = getelementptr inbounds %"class.c10::intrusive_ptr", ptr %7, i32 0, i32 0 + %9 = load ptr, ptr %8, align 8 + %10 = call noundef ptr @_ZN3c1019UndefinedTensorImpl9singletonEv() + %11 = icmp ne ptr %9, %10 + br i1 %11, label %BB_73, label %BB_89 + + BB_73: ; preds = %BB_72 + call void asm sideeffect "# LLVM BB: BB_73", ""() + %12 = getelementptr inbounds %"class.c10::intrusive_ptr", ptr %7, i32 0, i32 0 + %13 = load ptr, ptr %12, align 8 + %14 = bitcast ptr %13 to ptr + %15 = getelementptr inbounds %"class.c10::intrusive_ptr_target", ptr %14, i32 0, i32 1 + %16 = call noundef i64 @_ZN3c106detail25atomic_refcount_decrementERSt6atomicImE(ptr noundef nonnull align 8 dereferenceable(8) %15) + br label %BB_74 + + BB_74: ; preds = %BB_73 + call void asm sideeffect "# LLVM BB: BB_74", ""() + %17 = icmp eq i64 %16, 0 + br i1 %17, label %BB_75, label %BB_89 + + BB_75: ; preds = %BB_74 + call void asm sideeffect "# LLVM BB: BB_75", ""() + %18 = getelementptr inbounds %"class.c10::intrusive_ptr", ptr %7, i32 0, i32 0 + %19 = load ptr, ptr %18, align 8 + %20 = bitcast ptr %19 to ptr + %21 = getelementptr inbounds %"class.c10::intrusive_ptr_target", ptr %20, i32 0, i32 2 + %22 = bitcast ptr %21 to ptr + store ptr %22, ptr %1, align 8 + store i32 2, ptr %2, align 4 + %23 = load ptr, ptr %1, align 8 + %24 = load i32, ptr %2, align 4 + %25 = call noundef i32 @_ZStanSt12memory_orderSt23__memory_order_modifier(i32 noundef %24, i32 noundef 65535) + br label %BB_76 + + BB_76: ; preds = %BB_75 + call void asm sideeffect "# LLVM BB: BB_76", ""() + store i32 %25, ptr %3, align 4 + %26 = getelementptr inbounds %"struct.std::__atomic_base", ptr %23, i32 0, i32 0 + %27 = load i32, ptr %2, align 4 + switch i32 %27, label %BB_77 [ + i32 1, label %BB_78 + i32 2, label %BB_78 + i32 5, label %BB_79 + ] + + BB_77: ; preds = %BB_76 + call void asm sideeffect "# LLVM BB: BB_77", ""() + %28 = load atomic i64, ptr %26 monotonic, align 8 + store i64 %28, ptr %4, align 8 + br label %BB_80 + + BB_78: ; preds = %BB_76, %BB_76 + call void asm sideeffect "# LLVM BB: BB_78", ""() + %29 = load atomic i64, ptr %26 acquire, align 8 + store i64 %29, ptr %4, align 8 + br label %BB_80 + + BB_79: ; preds = %BB_76 + call void asm sideeffect "# LLVM BB: BB_79", ""() + %30 = load atomic i64, ptr %26 seq_cst, align 8 + store i64 %30, ptr %4, align 8 + br label %BB_80 + + BB_80: ; preds = %BB_79, %BB_78, %BB_77 + call void asm sideeffect "# LLVM BB: BB_80", ""() + %31 = load i64, ptr %4, align 8 + %32 = icmp eq i64 %31, 1 + %33 = zext i1 %32 to i8 + store i8 %33, ptr %6, align 1 + %34 = load i8, ptr %6, align 1 + %35 = trunc i8 %34 to i1 + br i1 %35, label %BB_84, label %BB_81 + + BB_81: ; preds = %BB_80 + call void asm sideeffect "# LLVM BB: BB_81", ""() + %36 = getelementptr inbounds %"class.c10::intrusive_ptr", ptr %7, i32 0, i32 0 + %37 = load ptr, ptr %36, align 8 + %38 = bitcast ptr %37 to ptr + %39 = load ptr, ptr %38, align 8 + %40 = getelementptr inbounds ptr, ptr %39, i64 2 + %41 = load ptr, ptr %40, align 8 + invoke void %41(ptr noundef nonnull align 8 dereferenceable(192) %37) + to label %BB_82 unwind label %BB_90 + + BB_82: ; preds = %BB_81 + call void asm sideeffect "# LLVM BB: BB_82", ""() + %42 = getelementptr inbounds %"class.c10::intrusive_ptr", ptr %7, i32 0, i32 0 + %43 = load ptr, ptr %42, align 8 + %44 = bitcast ptr %43 to ptr + %45 = getelementptr inbounds %"class.c10::intrusive_ptr_target", ptr %44, i32 0, i32 2 + %46 = call noundef i64 @_ZN3c106detail26atomic_weakcount_decrementERSt6atomicImE(ptr noundef nonnull align 8 dereferenceable(8) %45) + br label %BB_83 + + BB_83: ; preds = %BB_82 + call void asm sideeffect "# LLVM BB: BB_83", ""() + %47 = icmp eq i64 %46, 0 + %48 = zext i1 %47 to i8 + store i8 %48, ptr %6, align 1 + br label %BB_84 + + BB_84: ; preds = %BB_83, %BB_80 + call void asm sideeffect "# LLVM BB: BB_84", ""() + %49 = load i8, ptr %6, align 1 + %50 = trunc i8 %49 to i1 + br i1 %50, label %BB_85, label %BB_88 + + BB_85: ; preds = %BB_84 + call void asm sideeffect "# LLVM BB: BB_85", ""() + %51 = getelementptr inbounds %"class.c10::intrusive_ptr", ptr %7, i32 0, i32 0 + %52 = load ptr, ptr %51, align 8 + %53 = icmp eq ptr %52, null + br i1 %53, label %BB_87, label %BB_86 + + BB_86: ; preds = %BB_85 + call void asm sideeffect "# LLVM BB: BB_86", ""() + %54 = bitcast ptr %52 to ptr + %55 = load ptr, ptr %54, align 8 + %56 = getelementptr inbounds ptr, ptr %55, i64 1 + %57 = load ptr, ptr %56, align 8 + call void %57(ptr noundef nonnull align 8 dereferenceable(192) %52) #9 + br label %BB_87 + + BB_87: ; preds = %BB_86, %BB_85 + call void asm sideeffect "# LLVM BB: BB_87", ""() + br label %BB_88 + + BB_88: ; preds = %BB_87, %BB_84 + call void asm sideeffect "# LLVM BB: BB_88", ""() + br label %BB_89 + + BB_89: ; preds = %BB_88, %BB_74, %BB_72 + call void asm sideeffect "# LLVM BB: BB_89", ""() + ret void + + BB_90: ; preds = %BB_81 + %58 = landingpad { ptr, i32 } + catch ptr null + call void asm sideeffect "# LLVM BB: BB_90", ""() + %59 = extractvalue { ptr, i32 } %58, 0 + call void @__clang_call_terminate(ptr %59) #11 + unreachable + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZN3c106detail25atomic_refcount_decrementERSt6atomicImE(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #3 comdat { + BB_91: + call void asm sideeffect "# LLVM BB: BB_91", ""() + %1 = alloca ptr, align 8 + %2 = alloca i64, align 8 + %3 = alloca i32, align 4 + %4 = alloca i64, align 8 + %5 = alloca i64, align 8 + %6 = alloca ptr, align 8 + store ptr %0, ptr %6, align 8 + %7 = load ptr, ptr %6, align 8 + %8 = bitcast ptr %7 to ptr + store ptr %8, ptr %1, align 8 + store i64 1, ptr %2, align 8 + store i32 4, ptr %3, align 4 + %9 = load ptr, ptr %1, align 8 + %10 = getelementptr inbounds %"struct.std::__atomic_base", ptr %9, i32 0, i32 0 + %11 = load i32, ptr %3, align 4 + %12 = load i64, ptr %2, align 8 + store i64 %12, ptr %4, align 8 + switch i32 %11, label %BB_92 [ + i32 1, label %BB_93 + i32 2, label %BB_93 + i32 3, label %BB_94 + i32 4, label %BB_95 + i32 5, label %BB_96 + ] + + BB_92: ; preds = %BB_91 + call void asm sideeffect "# LLVM BB: BB_92", ""() + %13 = load i64, ptr %4, align 8 + %14 = atomicrmw sub ptr %10, i64 %13 monotonic, align 8 + store i64 %14, ptr %5, align 8 + br label %BB_97 + + BB_93: ; preds = %BB_91, %BB_91 + call void asm sideeffect "# LLVM BB: BB_93", ""() + %15 = load i64, ptr %4, align 8 + %16 = atomicrmw sub ptr %10, i64 %15 acquire, align 8 + store i64 %16, ptr %5, align 8 + br label %BB_97 + + BB_94: ; preds = %BB_91 + call void asm sideeffect "# LLVM BB: BB_94", ""() + %17 = load i64, ptr %4, align 8 + %18 = atomicrmw sub ptr %10, i64 %17 release, align 8 + store i64 %18, ptr %5, align 8 + br label %BB_97 + + BB_95: ; preds = %BB_91 + call void asm sideeffect "# LLVM BB: BB_95", ""() + %19 = load i64, ptr %4, align 8 + %20 = atomicrmw sub ptr %10, i64 %19 acq_rel, align 8 + store i64 %20, ptr %5, align 8 + br label %BB_97 + + BB_96: ; preds = %BB_91 + call void asm sideeffect "# LLVM BB: BB_96", ""() + %21 = load i64, ptr %4, align 8 + %22 = atomicrmw sub ptr %10, i64 %21 seq_cst, align 8 + store i64 %22, ptr %5, align 8 + br label %BB_97 + + BB_97: ; preds = %BB_96, %BB_95, %BB_94, %BB_93, %BB_92 + call void asm sideeffect "# LLVM BB: BB_97", ""() + %23 = load i64, ptr %5, align 8 + %24 = sub i64 %23, 1 + ret i64 %24 + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZN3c106detail26atomic_weakcount_decrementERSt6atomicImE(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #3 comdat { + BB_98: + call void asm sideeffect "# LLVM BB: BB_98", ""() + %1 = alloca ptr, align 8 + %2 = alloca i64, align 8 + %3 = alloca i32, align 4 + %4 = alloca i64, align 8 + %5 = alloca i64, align 8 + %6 = alloca ptr, align 8 + store ptr %0, ptr %6, align 8 + %7 = load ptr, ptr %6, align 8 + %8 = bitcast ptr %7 to ptr + store ptr %8, ptr %1, align 8 + store i64 1, ptr %2, align 8 + store i32 4, ptr %3, align 4 + %9 = load ptr, ptr %1, align 8 + %10 = getelementptr inbounds %"struct.std::__atomic_base", ptr %9, i32 0, i32 0 + %11 = load i32, ptr %3, align 4 + %12 = load i64, ptr %2, align 8 + store i64 %12, ptr %4, align 8 + switch i32 %11, label %BB_99 [ + i32 1, label %BB_100 + i32 2, label %BB_100 + i32 3, label %BB_101 + i32 4, label %BB_102 + i32 5, label %BB_103 + ] + + BB_99: ; preds = %BB_98 + call void asm sideeffect "# LLVM BB: BB_99", ""() + %13 = load i64, ptr %4, align 8 + %14 = atomicrmw sub ptr %10, i64 %13 monotonic, align 8 + store i64 %14, ptr %5, align 8 + br label %BB_104 + + BB_100: ; preds = %BB_98, %BB_98 + call void asm sideeffect "# LLVM BB: BB_100", ""() + %15 = load i64, ptr %4, align 8 + %16 = atomicrmw sub ptr %10, i64 %15 acquire, align 8 + store i64 %16, ptr %5, align 8 + br label %BB_104 + + BB_101: ; preds = %BB_98 + call void asm sideeffect "# LLVM BB: BB_101", ""() + %17 = load i64, ptr %4, align 8 + %18 = atomicrmw sub ptr %10, i64 %17 release, align 8 + store i64 %18, ptr %5, align 8 + br label %BB_104 + + BB_102: ; preds = %BB_98 + call void asm sideeffect "# LLVM BB: BB_102", ""() + %19 = load i64, ptr %4, align 8 + %20 = atomicrmw sub ptr %10, i64 %19 acq_rel, align 8 + store i64 %20, ptr %5, align 8 + br label %BB_104 + + BB_103: ; preds = %BB_98 + call void asm sideeffect "# LLVM BB: BB_103", ""() + %21 = load i64, ptr %4, align 8 + %22 = atomicrmw sub ptr %10, i64 %21 seq_cst, align 8 + store i64 %22, ptr %5, align 8 + br label %BB_104 + + BB_104: ; preds = %BB_103, %BB_102, %BB_101, %BB_100, %BB_99 + call void asm sideeffect "# LLVM BB: BB_104", ""() + %23 = load i64, ptr %5, align 8 + %24 = sub i64 %23, 1 + ret i64 %24 + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef i32 @_ZStanSt12memory_orderSt23__memory_order_modifier(i32 noundef %0, i32 noundef %1) local_unnamed_addr #3 comdat { + BB_105: + call void asm sideeffect "# LLVM BB: BB_105", ""() + %2 = alloca i32, align 4 + %3 = alloca i32, align 4 + store i32 %0, ptr %2, align 4 + store i32 %1, ptr %3, align 4 + %4 = load i32, ptr %2, align 4 + %5 = load i32, ptr %3, align 4 + %6 = and i32 %4, %5 + ret i32 %6 + } + + declare void @_ZN2at4_ops8int_repr4callERKNS_6TensorE(ptr sret(%"class.at::Tensor") align 8, ptr noundef nonnull align 8 dereferenceable(8)) local_unnamed_addr #5 + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZNK2at6Tensor2gtERKN3c106ScalarE(ptr noalias sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %1, ptr noundef nonnull align 16 dereferenceable(32) %2) local_unnamed_addr #0 comdat align 2 { + BB_106: + call void asm sideeffect "# LLVM BB: BB_106", ""() + %3 = alloca ptr, align 8 + %4 = alloca ptr, align 8 + %5 = alloca ptr, align 8 + %6 = bitcast ptr %0 to ptr + store ptr %6, ptr %3, align 8 + store ptr %1, ptr %4, align 8 + store ptr %2, ptr %5, align 8 + %7 = load ptr, ptr %4, align 8 + %8 = load ptr, ptr %5, align 8 + call void @_ZN2at4_ops9gt_Scalar4callERKNS_6TensorERKN3c106ScalarE(ptr sret(%"class.at::Tensor") align 8 %0, ptr noundef nonnull align 8 dereferenceable(8) %7, ptr noundef nonnull align 16 dereferenceable(32) %8) + ret void + } + + declare void @_ZN2at4_ops9gt_Scalar4callERKNS_6TensorERKN3c106ScalarE(ptr sret(%"class.at::Tensor") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 16 dereferenceable(32)) local_unnamed_addr #5 + + ; Function Attrs: noinline optnone uwtable + define linkonce_odr dso_local void @_ZN3c106ScalarC2IlLPb0EEET_b(ptr noundef nonnull align 16 dereferenceable(32) %0, i64 noundef %1, i1 noundef zeroext %2) unnamed_addr #2 comdat align 2 { + BB_107: + call void asm sideeffect "# LLVM BB: BB_107", ""() + %3 = alloca ptr, align 8 + %4 = alloca i64, align 8 + %5 = alloca i8, align 1 + store ptr %0, ptr %3, align 8 + store i64 %1, ptr %4, align 8 + %6 = zext i1 %2 to i8 + store i8 %6, ptr %5, align 1 + %7 = load ptr, ptr %3, align 8 + %8 = getelementptr inbounds %"class.c10::Scalar", ptr %7, i32 0, i32 0 + store i32 1, ptr %8, align 16 + %9 = getelementptr inbounds %"class.c10::Scalar", ptr %7, i32 0, i32 2 + call void @_ZN3c106Scalar3v_tC2Ev(ptr noundef nonnull align 16 dereferenceable(16) %9) + %10 = load i64, ptr %4, align 8 + %11 = call noundef i64 @_ZN3c107convertIllEET_T0_(i64 noundef %10) + %12 = getelementptr inbounds %"class.c10::Scalar", ptr %7, i32 0, i32 2 + %13 = bitcast ptr %12 to ptr + store i64 %11, ptr %13, align 16 + ret void + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c106Scalar3v_tC2Ev(ptr noundef nonnull align 16 dereferenceable(16) %0) unnamed_addr #1 comdat align 2 { + BB_108: + call void asm sideeffect "# LLVM BB: BB_108", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = bitcast ptr %2 to ptr + store double 0.000000e+00, ptr %3, align 16 + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZN3c107convertIllEET_T0_(i64 noundef %0) local_unnamed_addr #0 comdat { + BB_109: + call void asm sideeffect "# LLVM BB: BB_109", ""() + %1 = alloca i64, align 8 + store i64 %0, ptr %1, align 8 + %2 = load i64, ptr %1, align 8 + %3 = call noundef i64 @_ZN3c1027static_cast_with_inter_typeIllE5applyEl(i64 noundef %2) + ret i64 %3 + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZN3c1027static_cast_with_inter_typeIllE5applyEl(i64 noundef %0) local_unnamed_addr #0 comdat align 2 { + BB_110: + call void asm sideeffect "# LLVM BB: BB_110", ""() + %1 = alloca i64, align 8 + %2 = alloca i8, align 1 + %3 = alloca i64, align 8 + store i64 %0, ptr %1, align 8 + store i8 0, ptr %2, align 1 + %4 = load i64, ptr %1, align 8 + %5 = call noundef i64 @_ZN3c1010maybe_realILb0ElE5applyEl(i64 noundef %4) + store i64 %5, ptr %3, align 8 + %6 = load i64, ptr %3, align 8 + ret i64 %6 + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef i64 @_ZN3c1010maybe_realILb0ElE5applyEl(i64 noundef %0) local_unnamed_addr #3 comdat align 2 { + BB_111: + call void asm sideeffect "# LLVM BB: BB_111", ""() + %1 = alloca i64, align 8 + store i64 %0, ptr %1, align 8 + %2 = load i64, ptr %1, align 8 + ret i64 %2 + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZN3c106Scalar7destroyEv(ptr noundef nonnull align 16 dereferenceable(32) %0) local_unnamed_addr #0 comdat align 2 { + BB_112: + call void asm sideeffect "# LLVM BB: BB_112", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = getelementptr inbounds %"class.c10::Scalar", ptr %2, i32 0, i32 0 + %4 = load i32, ptr %3, align 16 + %5 = icmp eq i32 5, %4 + br i1 %5, label %BB_115, label %BB_113 + + BB_113: ; preds = %BB_112 + call void asm sideeffect "# LLVM BB: BB_113", ""() + %6 = getelementptr inbounds %"class.c10::Scalar", ptr %2, i32 0, i32 0 + %7 = load i32, ptr %6, align 16 + %8 = icmp eq i32 4, %7 + br i1 %8, label %BB_115, label %BB_114 + + BB_114: ; preds = %BB_113 + call void asm sideeffect "# LLVM BB: BB_114", ""() + %9 = getelementptr inbounds %"class.c10::Scalar", ptr %2, i32 0, i32 0 + %10 = load i32, ptr %9, align 16 + %11 = icmp eq i32 6, %10 + br i1 %11, label %BB_115, label %BB_116 + + BB_115: ; preds = %BB_114, %BB_113, %BB_112 + call void asm sideeffect "# LLVM BB: BB_115", ""() + %12 = getelementptr inbounds %"class.c10::Scalar", ptr %2, i32 0, i32 2 + %13 = bitcast ptr %12 to ptr + %14 = load ptr, ptr %13, align 16 + call void @_ZN3c103raw13intrusive_ptr6decrefEPNS_20intrusive_ptr_targetE(ptr noundef %14) + %15 = getelementptr inbounds %"class.c10::Scalar", ptr %2, i32 0, i32 2 + %16 = bitcast ptr %15 to ptr + store ptr null, ptr %16, align 16 + br label %BB_116 + + BB_116: ; preds = %BB_115, %BB_114 + call void asm sideeffect "# LLVM BB: BB_116", ""() + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZN3c103raw13intrusive_ptr6decrefEPNS_20intrusive_ptr_targetE(ptr noundef %0) local_unnamed_addr #0 comdat { + BB_117: + call void asm sideeffect "# LLVM BB: BB_117", ""() + %1 = alloca ptr, align 8 + %2 = alloca %"class.c10::intrusive_ptr.44", align 8 + store ptr %0, ptr %1, align 8 + %3 = load ptr, ptr %1, align 8 + call void @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_(ptr sret(%"class.c10::intrusive_ptr.44") align 8 %2, ptr noundef %3) + call void @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEED2Ev(ptr noundef nonnull align 8 dereferenceable(8) %2) #9 + ret void + } + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local void @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_(ptr noalias sret(%"class.c10::intrusive_ptr.44") align 8 %0, ptr noundef %1) local_unnamed_addr #0 comdat align 2 personality ptr @__gxx_personality_v0 { + BB_118: + call void asm sideeffect "# LLVM BB: BB_118", ""() + %2 = alloca ptr, align 8 + %3 = alloca i32, align 4 + %4 = alloca i32, align 4 + %5 = alloca i64, align 8 + %6 = alloca ptr, align 8 + %7 = alloca i32, align 4 + %8 = alloca i32, align 4 + %9 = alloca i64, align 8 + %10 = alloca ptr, align 8 + %11 = alloca ptr, align 8 + %12 = alloca %"struct.c10::raw::DontIncreaseRefcount", align 1 + %13 = bitcast ptr %0 to ptr + store ptr %13, ptr %10, align 8 + store ptr %1, ptr %11, align 8 + %14 = load ptr, ptr %11, align 8 + %15 = call noundef ptr @_ZN3c106detail34intrusive_target_default_null_typeINS_20intrusive_ptr_targetEE9singletonEv() #9 + %16 = icmp eq ptr %14, %15 + br i1 %16, label %BB_131, label %BB_119 + + BB_119: ; preds = %BB_118 + call void asm sideeffect "# LLVM BB: BB_119", ""() + %17 = load ptr, ptr %11, align 8 + %18 = getelementptr inbounds %"class.c10::intrusive_ptr_target", ptr %17, i32 0, i32 1 + %19 = bitcast ptr %18 to ptr + store ptr %19, ptr %2, align 8 + store i32 5, ptr %3, align 4 + %20 = load ptr, ptr %2, align 8 + %21 = load i32, ptr %3, align 4 + %22 = call noundef i32 @_ZStanSt12memory_orderSt23__memory_order_modifier(i32 noundef %21, i32 noundef 65535) + br label %BB_120 + + BB_120: ; preds = %BB_119 + call void asm sideeffect "# LLVM BB: BB_120", ""() + store i32 %22, ptr %4, align 4 + %23 = getelementptr inbounds %"struct.std::__atomic_base", ptr %20, i32 0, i32 0 + %24 = load i32, ptr %3, align 4 + switch i32 %24, label %BB_121 [ + i32 1, label %BB_122 + i32 2, label %BB_122 + i32 5, label %BB_123 + ] + + BB_121: ; preds = %BB_120 + call void asm sideeffect "# LLVM BB: BB_121", ""() + %25 = load atomic i64, ptr %23 monotonic, align 8 + store i64 %25, ptr %5, align 8 + br label %BB_124 + + BB_122: ; preds = %BB_120, %BB_120 + call void asm sideeffect "# LLVM BB: BB_122", ""() + %26 = load atomic i64, ptr %23 acquire, align 8 + store i64 %26, ptr %5, align 8 + br label %BB_124 + + BB_123: ; preds = %BB_120 + call void asm sideeffect "# LLVM BB: BB_123", ""() + %27 = load atomic i64, ptr %23 seq_cst, align 8 + store i64 %27, ptr %5, align 8 + br label %BB_124 + + BB_124: ; preds = %BB_123, %BB_122, %BB_121 + call void asm sideeffect "# LLVM BB: BB_124", ""() + %28 = load i64, ptr %5, align 8 + %29 = icmp eq i64 %28, 0 + br i1 %29, label %BB_131, label %BB_125 + + BB_125: ; preds = %BB_124 + call void asm sideeffect "# LLVM BB: BB_125", ""() + %30 = load ptr, ptr %11, align 8 + %31 = getelementptr inbounds %"class.c10::intrusive_ptr_target", ptr %30, i32 0, i32 2 + %32 = bitcast ptr %31 to ptr + store ptr %32, ptr %6, align 8 + store i32 5, ptr %7, align 4 + %33 = load ptr, ptr %6, align 8 + %34 = load i32, ptr %7, align 4 + %35 = call noundef i32 @_ZStanSt12memory_orderSt23__memory_order_modifier(i32 noundef %34, i32 noundef 65535) + br label %BB_126 + + BB_126: ; preds = %BB_125 + call void asm sideeffect "# LLVM BB: BB_126", ""() + store i32 %35, ptr %8, align 4 + %36 = getelementptr inbounds %"struct.std::__atomic_base", ptr %33, i32 0, i32 0 + %37 = load i32, ptr %7, align 4 + switch i32 %37, label %BB_127 [ + i32 1, label %BB_128 + i32 2, label %BB_128 + i32 5, label %BB_129 + ] + + BB_127: ; preds = %BB_126 + call void asm sideeffect "# LLVM BB: BB_127", ""() + %38 = load atomic i64, ptr %36 monotonic, align 8 + store i64 %38, ptr %9, align 8 + br label %BB_130 + + BB_128: ; preds = %BB_126, %BB_126 + call void asm sideeffect "# LLVM BB: BB_128", ""() + %39 = load atomic i64, ptr %36 acquire, align 8 + store i64 %39, ptr %9, align 8 + br label %BB_130 + + BB_129: ; preds = %BB_126 + call void asm sideeffect "# LLVM BB: BB_129", ""() + %40 = load atomic i64, ptr %36 seq_cst, align 8 + store i64 %40, ptr %9, align 8 + br label %BB_130 + + BB_130: ; preds = %BB_129, %BB_128, %BB_127 + call void asm sideeffect "# LLVM BB: BB_130", ""() + %41 = load i64, ptr %9, align 8 + %42 = icmp ne i64 %41, 0 + br label %BB_131 + + BB_131: ; preds = %BB_130, %BB_124, %BB_118 + %43 = phi i1 [ true, %BB_124 ], [ true, %BB_118 ], [ %42, %BB_130 ] + call void asm sideeffect "# LLVM BB: BB_131", ""() + %44 = xor i1 %43, true + br i1 %44, label %BB_132, label %BB_133 + + BB_132: ; preds = %BB_131 + call void asm sideeffect "# LLVM BB: BB_132", ""() + %45 = call noundef ptr @_ZN3c103strIJA68_cEEEDcDpRKT_(ptr noundef nonnull align 1 dereferenceable(68) @.str.3) + call void @_ZN3c106detail23torchInternalAssertFailEPKcS2_jS2_S2_(ptr noundef @__func__._ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_, ptr noundef @.str.1, i32 noundef 475, ptr noundef @.str.2, ptr noundef %45) #10 + unreachable + + BB_133: ; preds = %BB_131 + call void asm sideeffect "# LLVM BB: BB_133", ""() + %46 = load ptr, ptr %11, align 8 + call void @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEEC2EPS1_NS_3raw20DontIncreaseRefcountE(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef %46) #9 + ret void + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEED2Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) unnamed_addr #1 comdat align 2 { + BB_134: + call void asm sideeffect "# LLVM BB: BB_134", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + call void @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE6reset_Ev(ptr noundef nonnull align 8 dereferenceable(8) %2) #9 + ret void + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef ptr @_ZN3c106detail34intrusive_target_default_null_typeINS_20intrusive_ptr_targetEE9singletonEv() local_unnamed_addr #3 comdat align 2 { + BB_135: + call void asm sideeffect "# LLVM BB: BB_135", ""() + ret ptr null + } + + ; Function Attrs: noreturn + declare void @_ZN3c106detail23torchInternalAssertFailEPKcS2_jS2_S2_(ptr noundef, ptr noundef, i32 noundef, ptr noundef, ptr noundef) local_unnamed_addr #6 + + ; Function Attrs: mustprogress noinline optnone uwtable + define linkonce_odr dso_local noundef ptr @_ZN3c103strIJA68_cEEEDcDpRKT_(ptr noundef nonnull align 1 dereferenceable(68) %0) local_unnamed_addr #0 comdat { + BB_136: + call void asm sideeffect "# LLVM BB: BB_136", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + %3 = getelementptr inbounds [68 x i8], ptr %2, i64 0, i64 0 + %4 = call noundef ptr @_ZN3c106detail12_str_wrapperIJPKcEE4callES3_(ptr noundef %3) + ret ptr %4 + } + + ; Function Attrs: noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEEC2EPS1_NS_3raw20DontIncreaseRefcountE(ptr noundef nonnull align 8 dereferenceable(8) %0, ptr noundef %1) unnamed_addr #1 comdat align 2 { + BB_137: + call void asm sideeffect "# LLVM BB: BB_137", ""() + %2 = alloca %"struct.c10::raw::DontIncreaseRefcount", align 1 + %3 = alloca ptr, align 8 + %4 = alloca ptr, align 8 + store ptr %0, ptr %3, align 8 + store ptr %1, ptr %4, align 8 + %5 = load ptr, ptr %3, align 8 + %6 = getelementptr inbounds %"class.c10::intrusive_ptr.44", ptr %5, i32 0, i32 0 + %7 = load ptr, ptr %4, align 8 + store ptr %7, ptr %6, align 8 + ret void + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local noundef ptr @_ZN3c106detail12_str_wrapperIJPKcEE4callES3_(ptr noundef %0) local_unnamed_addr #3 comdat align 2 { + BB_138: + call void asm sideeffect "# LLVM BB: BB_138", ""() + %1 = alloca ptr, align 8 + store ptr %0, ptr %1, align 8 + %2 = load ptr, ptr %1, align 8 + ret ptr %2 + } + + ; Function Attrs: mustprogress noinline nounwind optnone uwtable + define linkonce_odr dso_local void @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE6reset_Ev(ptr noundef nonnull align 8 dereferenceable(8) %0) local_unnamed_addr #3 comdat align 2 personality ptr @__gxx_personality_v0 { + BB_139: + call void asm sideeffect "# LLVM BB: BB_139", ""() + %1 = alloca ptr, align 8 + %2 = alloca i32, align 4 + %3 = alloca i32, align 4 + %4 = alloca i64, align 8 + %5 = alloca ptr, align 8 + %6 = alloca i8, align 1 + store ptr %0, ptr %5, align 8 + %7 = load ptr, ptr %5, align 8 + %8 = getelementptr inbounds %"class.c10::intrusive_ptr.44", ptr %7, i32 0, i32 0 + %9 = load ptr, ptr %8, align 8 + %10 = call noundef ptr @_ZN3c106detail34intrusive_target_default_null_typeINS_20intrusive_ptr_targetEE9singletonEv() #9 + %11 = icmp ne ptr %9, %10 + br i1 %11, label %BB_140, label %BB_154 + + BB_140: ; preds = %BB_139 + call void asm sideeffect "# LLVM BB: BB_140", ""() + %12 = getelementptr inbounds %"class.c10::intrusive_ptr.44", ptr %7, i32 0, i32 0 + %13 = load ptr, ptr %12, align 8 + %14 = getelementptr inbounds %"class.c10::intrusive_ptr_target", ptr %13, i32 0, i32 1 + %15 = call noundef i64 @_ZN3c106detail25atomic_refcount_decrementERSt6atomicImE(ptr noundef nonnull align 8 dereferenceable(8) %14) + %16 = icmp eq i64 %15, 0 + br i1 %16, label %BB_141, label %BB_154 + + BB_141: ; preds = %BB_140 + call void asm sideeffect "# LLVM BB: BB_141", ""() + %17 = getelementptr inbounds %"class.c10::intrusive_ptr.44", ptr %7, i32 0, i32 0 + %18 = load ptr, ptr %17, align 8 + %19 = getelementptr inbounds %"class.c10::intrusive_ptr_target", ptr %18, i32 0, i32 2 + %20 = bitcast ptr %19 to ptr + store ptr %20, ptr %1, align 8 + store i32 2, ptr %2, align 4 + %21 = load ptr, ptr %1, align 8 + %22 = load i32, ptr %2, align 4 + %23 = call noundef i32 @_ZStanSt12memory_orderSt23__memory_order_modifier(i32 noundef %22, i32 noundef 65535) + br label %BB_142 + + BB_142: ; preds = %BB_141 + call void asm sideeffect "# LLVM BB: BB_142", ""() + store i32 %23, ptr %3, align 4 + %24 = getelementptr inbounds %"struct.std::__atomic_base", ptr %21, i32 0, i32 0 + %25 = load i32, ptr %2, align 4 + switch i32 %25, label %BB_143 [ + i32 1, label %BB_144 + i32 2, label %BB_144 + i32 5, label %BB_145 + ] + + BB_143: ; preds = %BB_142 + call void asm sideeffect "# LLVM BB: BB_143", ""() + %26 = load atomic i64, ptr %24 monotonic, align 8 + store i64 %26, ptr %4, align 8 + br label %BB_146 + + BB_144: ; preds = %BB_142, %BB_142 + call void asm sideeffect "# LLVM BB: BB_144", ""() + %27 = load atomic i64, ptr %24 acquire, align 8 + store i64 %27, ptr %4, align 8 + br label %BB_146 + + BB_145: ; preds = %BB_142 + call void asm sideeffect "# LLVM BB: BB_145", ""() + %28 = load atomic i64, ptr %24 seq_cst, align 8 + store i64 %28, ptr %4, align 8 + br label %BB_146 + + BB_146: ; preds = %BB_145, %BB_144, %BB_143 + call void asm sideeffect "# LLVM BB: BB_146", ""() + %29 = load i64, ptr %4, align 8 + %30 = icmp eq i64 %29, 1 + %31 = zext i1 %30 to i8 + store i8 %31, ptr %6, align 1 + %32 = load i8, ptr %6, align 1 + %33 = trunc i8 %32 to i1 + br i1 %33, label %BB_149, label %BB_147 + + BB_147: ; preds = %BB_146 + call void asm sideeffect "# LLVM BB: BB_147", ""() + %34 = getelementptr inbounds %"class.c10::intrusive_ptr.44", ptr %7, i32 0, i32 0 + %35 = load ptr, ptr %34, align 8 + %36 = bitcast ptr %35 to ptr + %37 = load ptr, ptr %36, align 8 + %38 = getelementptr inbounds ptr, ptr %37, i64 2 + %39 = load ptr, ptr %38, align 8 + invoke void %39(ptr noundef nonnull align 8 dereferenceable(24) %35) + to label %BB_148 unwind label %BB_155 + + BB_148: ; preds = %BB_147 + call void asm sideeffect "# LLVM BB: BB_148", ""() + %40 = getelementptr inbounds %"class.c10::intrusive_ptr.44", ptr %7, i32 0, i32 0 + %41 = load ptr, ptr %40, align 8 + %42 = getelementptr inbounds %"class.c10::intrusive_ptr_target", ptr %41, i32 0, i32 2 + %43 = call noundef i64 @_ZN3c106detail26atomic_weakcount_decrementERSt6atomicImE(ptr noundef nonnull align 8 dereferenceable(8) %42) + %44 = icmp eq i64 %43, 0 + %45 = zext i1 %44 to i8 + store i8 %45, ptr %6, align 1 + br label %BB_149 + + BB_149: ; preds = %BB_148, %BB_146 + call void asm sideeffect "# LLVM BB: BB_149", ""() + %46 = load i8, ptr %6, align 1 + %47 = trunc i8 %46 to i1 + br i1 %47, label %BB_150, label %BB_153 + + BB_150: ; preds = %BB_149 + call void asm sideeffect "# LLVM BB: BB_150", ""() + %48 = getelementptr inbounds %"class.c10::intrusive_ptr.44", ptr %7, i32 0, i32 0 + %49 = load ptr, ptr %48, align 8 + %50 = icmp eq ptr %49, null + br i1 %50, label %BB_152, label %BB_151 + + BB_151: ; preds = %BB_150 + call void asm sideeffect "# LLVM BB: BB_151", ""() + %51 = bitcast ptr %49 to ptr + %52 = load ptr, ptr %51, align 8 + %53 = getelementptr inbounds ptr, ptr %52, i64 1 + %54 = load ptr, ptr %53, align 8 + call void %54(ptr noundef nonnull align 8 dereferenceable(24) %49) #9 + br label %BB_152 + + BB_152: ; preds = %BB_151, %BB_150 + call void asm sideeffect "# LLVM BB: BB_152", ""() + br label %BB_153 + + BB_153: ; preds = %BB_152, %BB_149 + call void asm sideeffect "# LLVM BB: BB_153", ""() + br label %BB_154 + + BB_154: ; preds = %BB_153, %BB_140, %BB_139 + call void asm sideeffect "# LLVM BB: BB_154", ""() + ret void + + BB_155: ; preds = %BB_147 + %55 = landingpad { ptr, i32 } + catch ptr null + call void asm sideeffect "# LLVM BB: BB_155", ""() + %56 = extractvalue { ptr, i32 } %55, 0 + call void @__clang_call_terminate(ptr %56) #11 + unreachable + } + + declare void @_ZN2at4_ops17where_ScalarOther4callERKNS_6TensorES4_RKN3c106ScalarE(ptr sret(%"class.at::Tensor") align 8, ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 8 dereferenceable(8), ptr noundef nonnull align 16 dereferenceable(32)) local_unnamed_addr #5 + + declare void @_ZN2at4_ops33_make_per_tensor_quantized_tensor4callERKNS_6TensorEdl(ptr sret(%"class.at::Tensor") align 8, ptr noundef nonnull align 8 dereferenceable(8), double noundef, i64 noundef) local_unnamed_addr #5 + + ; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write) + declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #7 + + ; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: readwrite) + declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #8 + + declare void @_Unwind_Resume(ptr) + + attributes #0 = { mustprogress noinline optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #1 = { noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #2 = { noinline optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #3 = { mustprogress noinline nounwind optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #4 = { noinline noreturn nounwind } + attributes #5 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #6 = { noreturn "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #7 = { nocallback nofree nounwind willreturn memory(argmem: write) } + attributes #8 = { nocallback nofree nounwind willreturn memory(argmem: readwrite) } + attributes #9 = { nounwind } + attributes #10 = { noreturn } + attributes #11 = { noreturn nounwind } + + !llvm.module.flags = !{!0, !1, !2, !3, !4} + !llvm.ident = !{!5} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{i32 8, !"PIC Level", i32 2} + !2 = !{i32 7, !"PIE Level", i32 2} + !3 = !{i32 7, !"uwtable", i32 1} + !4 = !{i32 7, !"frame-pointer", i32 2} + !5 = !{!"Ubuntu clang version 14.0.0-1ubuntu1.1"} + !6 = distinct !{!6, !7} + !7 = !{!"llvm.loop.mustprogress"} + +... +--- +name: _ZN2at6native19gelu_quantized_cudaERKNS_6TensorEN3c1017basic_string_viewIcEE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: fr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr8, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr64, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr32, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr32, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr64, preferred-register: '' } + - { id: 29, class: fr64, preferred-register: '' } + - { id: 30, class: gr64, preferred-register: '' } + - { id: 31, class: gr64, preferred-register: '' } + - { id: 32, class: gr64, preferred-register: '' } + - { id: 33, class: gr8, preferred-register: '' } + - { id: 34, class: gr32, preferred-register: '' } + - { id: 35, class: gr64, preferred-register: '' } + - { id: 36, class: gr64, preferred-register: '' } + - { id: 37, class: gr64, preferred-register: '' } + - { id: 38, class: gr64, preferred-register: '' } + - { id: 39, class: gr32, preferred-register: '' } + - { id: 40, class: gr64, preferred-register: '' } + - { id: 41, class: gr32, preferred-register: '' } + - { id: 42, class: gr64, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: gr64, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: gr64, preferred-register: '' } + - { id: 47, class: gr64, preferred-register: '' } + - { id: 48, class: gr64, preferred-register: '' } + - { id: 49, class: gr32, preferred-register: '' } + - { id: 50, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%3' } + - { reg: '$rsi', virtual-reg: '%4' } + - { reg: '$rdx', virtual-reg: '%5' } + - { reg: '$rcx', virtual-reg: '%6' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 16, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 6, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 7, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_0: + successors: %bb.2(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $rsi, $rdx, $rcx + + %6:gr64 = COPY $rcx + %5:gr64 = COPY $rdx + %4:gr64 = COPY $rsi + %3:gr64 = COPY $rdi + %7:gr64 = COPY %3 + INLINEASM &"# LLVM BB: BB_0", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.4) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %5 :: (store (s64) into %ir.14) + MOV64mr %stack.1, 1, $noreg, 8, $noreg, %6 :: (store (s64) into %ir.15) + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %4 :: (store (s64) into %ir.6) + %12:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.6) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %12 + CALL64pcrel32 @_ZNK2at10TensorBase5numelEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %10:gr64 = COPY $rax + CMP64ri32 %10, 0, implicit-def $eflags + JCC_1 %bb.2, 5, implicit $eflags + + bb.1.BB_1: + successors: %bb.12(0x80000000) + + INLINEASM &"# LLVM BB: BB_1", 1 /* sideeffect attdialect */ + %49:gr32 = MOV32r0 implicit-def $eflags + %50:gr64 = MOV32ri64 8 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %3 + $esi = COPY %49 + $rdx = COPY %50 + CALL64pcrel32 target-flags(x86-plt) , csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit $rdx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %3 + CALL64pcrel32 @_ZN2at6TensorC2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + JMP_1 %bb.12 + + bb.2.BB_2: + successors: %bb.3(0x40000000), %bb.9(0x40000000) + + INLINEASM &"# LLVM BB: BB_2", 1 /* sideeffect attdialect */ + %14:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.6) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %15:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + $rdi = COPY %15 + $rsi = COPY %14 + CALL64pcrel32 @_ZN2at10dequantizeERKNS_6TensorE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %16:gr64 = MOV32ri64 @.str + %17:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + $rdi = COPY %17 + $rsi = COPY %16 + CALL64pcrel32 @_ZN3c1017basic_string_viewIcEC2EPKc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.3 + + bb.3.BB_3: + successors: %bb.4(0x40000000), %bb.9(0x40000000) + + INLINEASM &"# LLVM BB: BB_3", 1 /* sideeffect attdialect */ + %18:gr64 = MOV64rm %stack.5, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.23) + %19:gr64 = MOV64rm %stack.5, 1, $noreg, 8, $noreg :: (dereferenceable load (s64) from %ir.25) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %20:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + %21:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + $rdi = COPY %20 + $rsi = COPY %21 + $rdx = COPY %18 + $rcx = COPY %19 + CALL64pcrel32 @_ZN2at4geluERKNS_6TensorEN3c1017basic_string_viewIcEE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.4 + + bb.4.BB_4: + successors: %bb.5(0x40000000), %bb.10(0x40000000) + + INLINEASM &"# LLVM BB: BB_4", 1 /* sideeffect attdialect */ + %28:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.6) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %28 + CALL64pcrel32 @_ZNK2at6Tensor7q_scaleEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $xmm0 + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %29:fr64 = COPY $xmm0 + EH_LABEL + %0:fr64 = COPY %29 + JMP_1 %bb.5 + + bb.5.BB_5: + successors: %bb.6(0x40000000), %bb.10(0x40000000) + + INLINEASM &"# LLVM BB: BB_5", 1 /* sideeffect attdialect */ + %30:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.6) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %30 + CALL64pcrel32 @_ZNK2at6Tensor12q_zero_pointEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %31:gr64 = COPY $rax + EH_LABEL + %1:gr64 = COPY %31 + JMP_1 %bb.6 + + bb.6.BB_6: + successors: %bb.7(0x40000000), %bb.10(0x40000000) + + INLINEASM &"# LLVM BB: BB_6", 1 /* sideeffect attdialect */ + %32:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.6) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %32 + CALL64pcrel32 @_ZNK2at10TensorBase11scalar_typeEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $al + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %33:gr8 = COPY $al + EH_LABEL + %2:gr8 = COPY %33 + JMP_1 %bb.7 + + bb.7.BB_7: + successors: %bb.8(0x40000000), %bb.10(0x40000000) + + INLINEASM &"# LLVM BB: BB_7", 1 /* sideeffect attdialect */ + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %34:gr32 = MOVSX32rr8 %2 + %35:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + $rdi = COPY %3 + $rsi = COPY %35 + $xmm0 = COPY %0 + $rdx = COPY %1 + $ecx = COPY %34 + CALL64pcrel32 @_ZN2at19quantize_per_tensorERKNS_6TensorEdlN3c1010ScalarTypeE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $xmm0, implicit $rdx, implicit $ecx, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.8 + + bb.8.BB_8: + successors: %bb.12(0x80000000) + + INLINEASM &"# LLVM BB: BB_8", 1 /* sideeffect attdialect */ + %47:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %47 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %46:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %46 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + JMP_1 %bb.12 + + bb.9.BB_9 (landing-pad): + successors: %bb.11(0x80000000) + liveins: $rax, $rdx + + EH_LABEL + %23:gr64 = COPY killed $rdx + %22:gr64 = COPY killed $rax + %26:gr32 = COPY %23.sub_32bit + %25:gr64 = COPY %22 + INLINEASM &"# LLVM BB: BB_9", 1 /* sideeffect attdialect */ + MOV64mr %stack.6, 1, $noreg, 0, $noreg, %25 :: (store (s64) into %ir.10) + MOV32mr %stack.7, 1, $noreg, 0, $noreg, %26 :: (store (s32) into %ir.11) + JMP_1 %bb.11 + + bb.10.BB_10 (landing-pad): + successors: %bb.11(0x80000000) + liveins: $rax, $rdx + + EH_LABEL + %37:gr64 = COPY killed $rdx + %36:gr64 = COPY killed $rax + %41:gr32 = COPY %37.sub_32bit + %40:gr64 = COPY %36 + INLINEASM &"# LLVM BB: BB_10", 1 /* sideeffect attdialect */ + MOV64mr %stack.6, 1, $noreg, 0, $noreg, %40 :: (store (s64) into %ir.10) + MOV32mr %stack.7, 1, $noreg, 0, $noreg, %41 :: (store (s32) into %ir.11) + %38:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %38 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + + bb.11.BB_11: + successors: %bb.13(0x80000000) + + INLINEASM &"# LLVM BB: BB_11", 1 /* sideeffect attdialect */ + %43:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %43 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + JMP_1 %bb.13 + + bb.12.BB_12: + INLINEASM &"# LLVM BB: BB_12", 1 /* sideeffect attdialect */ + $rax = COPY %7 + RET64 implicit $rax + + bb.13.BB_13: + INLINEASM &"# LLVM BB: BB_13", 1 /* sideeffect attdialect */ + %45:gr64 = MOV64rm %stack.6, 1, $noreg, 0, $noreg :: (load (s64) from %ir.10) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %45 + CALL64pcrel32 target-flags(x86-plt) @_Unwind_Resume, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + +... +--- +name: _ZNK2at10TensorBase5numelEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_14: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_14", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %8:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %8 + CALL64pcrel32 @_ZNK3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEptEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %6:gr64 = COPY $rax + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %6 + CALL64pcrel32 @_ZNK3c1010TensorImpl5numelEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %4:gr64 = COPY $rax + $rax = COPY %4 + RET64 implicit $rax + +... +--- +name: _ZN2at6TensorC2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_15: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_15", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %4:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %4 + CALL64pcrel32 @_ZN2at10TensorBaseC2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN2at10dequantizeERKNS_6TensorE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_16: + liveins: $rdi, $rsi + + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %2:gr64 = COPY %0 + INLINEASM &"# LLVM BB: BB_16", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.2) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.3) + %4:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %0 + $rsi = COPY %4 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops15dequantize_self4callERKNS_6TensorE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %2 + RET64 implicit $rax + +... +--- +name: _ZN2at4geluERKNS_6TensorEN3c1017basic_string_viewIcEE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } + - { reg: '$rdx', virtual-reg: '%2' } + - { reg: '$rcx', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 16, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_17: + liveins: $rdi, $rsi, $rdx, $rcx + + %3:gr64 = COPY $rcx + %2:gr64 = COPY $rdx + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %4:gr64 = COPY %0 + INLINEASM &"# LLVM BB: BB_17", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.4) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.10) + MOV64mr %stack.1, 1, $noreg, 8, $noreg, %3 :: (store (s64) into %ir.11) + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.6) + %12:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.6) + %10:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %10 + %11:gr64 = MOV64rm %stack.1, 1, $noreg, 8, $noreg + MOV64mr %stack.3, 1, $noreg, 8, $noreg, %11 + %9:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %ir.16) + %8:gr64 = MOV64rm %stack.3, 1, $noreg, 8, $noreg :: (load (s64) from %ir.18) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %0 + $rsi = COPY %12 + $rdx = COPY %9 + $rcx = COPY %8 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops4gelu4callERKNS_6TensorEN3c1017basic_string_viewIcEE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %4 + RET64 implicit $rax + +... +--- +name: _ZN3c1017basic_string_viewIcEC2EPKc +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_18: + liveins: $rdi, $rsi + + %2:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + %3:gr64 = COPY killed %2 + INLINEASM &"# LLVM BB: BB_18", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.2) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.3) + %11:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.2) + %10:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + %9:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %9 + CALL64pcrel32 @_ZN3c1017basic_string_viewIcE7strlen_EPKc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %8:gr64 = COPY $rax + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %11 + $rsi = COPY %10 + $rdx = COPY %8 + CALL64pcrel32 @_ZN3c1017basic_string_viewIcEC2EPKcm, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN2at19quantize_per_tensorERKNS_6TensorEdlN3c1010ScalarTypeE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: fr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr8, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: fr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr8, preferred-register: '' } + - { id: 11, class: gr32, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: fr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } + - { reg: '$xmm0', virtual-reg: '%2' } + - { reg: '$rdx', virtual-reg: '%3' } + - { reg: '$ecx', virtual-reg: '%4' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_19: + liveins: $rdi, $rsi, $xmm0, $rdx, $ecx + + %4:gr32 = COPY $ecx + %3:gr64 = COPY $rdx + %2:fr64 = COPY $xmm0 + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %6:gr8 = COPY %4.sub_8bit + %5:gr64 = COPY %0 + INLINEASM &"# LLVM BB: BB_19", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.5) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.6) + MOVSDmr %stack.2, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.7) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.8) + MOV8mr %stack.4, 1, $noreg, 0, $noreg, %6 :: (store (s8) into %ir.9) + %14:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.6) + %13:fr64 = MOVSDrm_alt %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.7) + %12:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %ir.8) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %0 + $rsi = COPY %14 + $xmm0 = COPY %13 + $rdx = COPY %12 + %11:gr32 = MOVSX32rm8 %stack.4, 1, $noreg, 0, $noreg :: (load (s8) from %ir.9) + $ecx = COPY %11 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops19quantize_per_tensor4callERKNS_6TensorEdlN3c1010ScalarTypeE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $xmm0, implicit $rdx, implicit $ecx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %5 + RET64 implicit $rax + +... +--- +name: _ZNK2at6Tensor7q_scaleEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: fr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: fr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_20: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_20", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %5:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %5 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops7q_scale4callERKNS_6TensorE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $xmm0 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %4:fr64 = COPY $xmm0 + $xmm0 = COPY %4 + RET64 implicit $xmm0 + +... +--- +name: _ZNK2at6Tensor12q_zero_pointEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_21: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_21", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %5:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %5 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops12q_zero_point4callERKNS_6TensorE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %4:gr64 = COPY $rax + $rax = COPY %4 + RET64 implicit $rax + +... +--- +name: _ZNK2at10TensorBase11scalar_typeEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr8, preferred-register: '' } + - { id: 3, class: gr32, preferred-register: '' } + - { id: 4, class: gr16, preferred-register: '' } + - { id: 5, class: gr32, preferred-register: '' } + - { id: 6, class: gr8, preferred-register: '' } + - { id: 7, class: gr16, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr16, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 2, alignment: 2, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_22: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_22", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %13:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %13 + CALL64pcrel32 @_ZNK3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEptEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %11:gr64 = COPY $rax + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %11 + CALL64pcrel32 @_ZNK3c1010TensorImpl5dtypeEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $ax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %9:gr16 = COPY $ax + MOV16mr %stack.1, 1, $noreg, 0, $noreg, %9 :: (store (s16) into %ir.7) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %5:gr32 = MOVZX32rm16 %stack.1, 1, $noreg, 0, $noreg :: (load (s16) from %ir.8) + $edi = COPY %5 + CALL64pcrel32 @_ZN3c10L20typeMetaToScalarTypeEN6caffe28TypeMetaE, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $al + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %6:gr8 = COPY $al + %3:gr32 = MOVSX32rr8 %6 + $eax = COPY %3 + RET64 implicit $eax + +... +--- +name: _ZN2at6TensorD2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_23: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_23", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %4:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %4 + CALL64pcrel32 @_ZN2at10TensorBaseD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN2at6native19relu_quantized_cudaERKNS_6TensorE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: fr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr32, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr32, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr64, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr32, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr32, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr64, preferred-register: '' } + - { id: 29, class: gr64, preferred-register: '' } + - { id: 30, class: gr64, preferred-register: '' } + - { id: 31, class: gr32, preferred-register: '' } + - { id: 32, class: gr64, preferred-register: '' } + - { id: 33, class: gr32, preferred-register: '' } + - { id: 34, class: gr64, preferred-register: '' } + - { id: 35, class: gr64, preferred-register: '' } + - { id: 36, class: gr64, preferred-register: '' } + - { id: 37, class: gr64, preferred-register: '' } + - { id: 38, class: gr64, preferred-register: '' } + - { id: 39, class: gr64, preferred-register: '' } + - { id: 40, class: gr64, preferred-register: '' } + - { id: 41, class: gr64, preferred-register: '' } + - { id: 42, class: gr32, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: gr32, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: gr64, preferred-register: '' } + - { id: 47, class: gr64, preferred-register: '' } + - { id: 48, class: fr64, preferred-register: '' } + - { id: 49, class: gr64, preferred-register: '' } + - { id: 50, class: gr64, preferred-register: '' } + - { id: 51, class: gr64, preferred-register: '' } + - { id: 52, class: gr64, preferred-register: '' } + - { id: 53, class: gr64, preferred-register: '' } + - { id: 54, class: gr32, preferred-register: '' } + - { id: 55, class: gr64, preferred-register: '' } + - { id: 56, class: gr32, preferred-register: '' } + - { id: 57, class: gr64, preferred-register: '' } + - { id: 58, class: gr64, preferred-register: '' } + - { id: 59, class: gr64, preferred-register: '' } + - { id: 60, class: gr64, preferred-register: '' } + - { id: 61, class: gr64, preferred-register: '' } + - { id: 62, class: gr64, preferred-register: '' } + - { id: 63, class: gr64, preferred-register: '' } + - { id: 64, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%1' } + - { reg: '$rsi', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 16 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 32, alignment: 16, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 6, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 7, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 8, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 9, name: '', type: default, offset: 0, size: 32, alignment: 16, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_24: + successors: %bb.1(0x40000000), %bb.7(0x40000000) + liveins: $rdi, $rsi + + %2:gr64 = COPY $rsi + %1:gr64 = COPY $rdi + %3:gr64 = COPY %1 + INLINEASM &"# LLVM BB: BB_24", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.2) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.3) + %4:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.3) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %4 + CALL64pcrel32 @_ZNK2at6Tensor12q_zero_pointEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %5:gr64 = COPY $rax + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %5 :: (store (s64) into %ir.4) + %6:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.3) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %7:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + $rdi = COPY %7 + $rsi = COPY %6 + CALL64pcrel32 @_ZNK2at6Tensor8int_reprEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %8:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %9:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + $rdi = COPY %9 + $rsi = COPY %8 + CALL64pcrel32 @_ZN3c106ScalarC2El, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.1 + + bb.1.BB_25: + successors: %bb.2(0x40000000), %bb.8(0x40000000) + + INLINEASM &"# LLVM BB: BB_25", 1 /* sideeffect attdialect */ + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %16:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + %17:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + %18:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + $rdi = COPY %16 + $rsi = COPY %17 + $rdx = COPY %18 + CALL64pcrel32 @_ZN2atgtERKNS_6TensorERKN3c106ScalarE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.2 + + bb.2.BB_26: + successors: %bb.3(0x40000000), %bb.9(0x40000000) + + INLINEASM &"# LLVM BB: BB_26", 1 /* sideeffect attdialect */ + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %26:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + $rdi = COPY %26 + CALL64pcrel32 @_ZN3c106ScalarD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %27:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %28:gr64 = LEA64r %stack.9, 1, $noreg, 0, $noreg + $rdi = COPY %28 + $rsi = COPY %27 + CALL64pcrel32 @_ZN3c106ScalarC2El, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.3 + + bb.3.BB_27: + successors: %bb.4(0x40000000), %bb.10(0x40000000) + + INLINEASM &"# LLVM BB: BB_27", 1 /* sideeffect attdialect */ + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %35:gr64 = LEA64r %stack.8, 1, $noreg, 0, $noreg + %36:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + %37:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + %38:gr64 = LEA64r %stack.9, 1, $noreg, 0, $noreg + $rdi = COPY %35 + $rsi = COPY %36 + $rdx = COPY %37 + $rcx = COPY %38 + CALL64pcrel32 @_ZN2at5whereERKNS_6TensorES2_RKN3c106ScalarE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.4 + + bb.4.BB_28: + successors: %bb.5(0x40000000), %bb.11(0x40000000) + + INLINEASM &"# LLVM BB: BB_28", 1 /* sideeffect attdialect */ + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %46:gr64 = LEA64r %stack.9, 1, $noreg, 0, $noreg + $rdi = COPY %46 + CALL64pcrel32 @_ZN3c106ScalarD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %47:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.3) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %47 + CALL64pcrel32 @_ZNK2at6Tensor7q_scaleEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $xmm0 + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %48:fr64 = COPY $xmm0 + EH_LABEL + %0:fr64 = COPY %48 + JMP_1 %bb.5 + + bb.5.BB_29: + successors: %bb.6(0x40000000), %bb.11(0x40000000) + + INLINEASM &"# LLVM BB: BB_29", 1 /* sideeffect attdialect */ + %49:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %50:gr64 = LEA64r %stack.8, 1, $noreg, 0, $noreg + $rdi = COPY %1 + $rsi = COPY %50 + $xmm0 = COPY %0 + $rdx = COPY %49 + CALL64pcrel32 @_ZN2at33_make_per_tensor_quantized_tensorERKNS_6TensorEdl, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $xmm0, implicit $rdx, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.6 + + bb.6.BB_30: + INLINEASM &"# LLVM BB: BB_30", 1 /* sideeffect attdialect */ + %64:gr64 = LEA64r %stack.8, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %64 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %63:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %63 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %62:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %62 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %3 + RET64 implicit $rax + + bb.7.BB_31 (landing-pad): + successors: %bb.13(0x80000000) + liveins: $rax, $rdx + + EH_LABEL + %11:gr64 = COPY killed $rdx + %10:gr64 = COPY killed $rax + %14:gr32 = COPY %11.sub_32bit + %13:gr64 = COPY %10 + INLINEASM &"# LLVM BB: BB_31", 1 /* sideeffect attdialect */ + MOV64mr %stack.6, 1, $noreg, 0, $noreg, %13 :: (store (s64) into %ir.8) + MOV32mr %stack.7, 1, $noreg, 0, $noreg, %14 :: (store (s32) into %ir.9) + JMP_1 %bb.13 + + bb.8.BB_32 (landing-pad): + successors: %bb.13(0x80000000) + liveins: $rax, $rdx + + EH_LABEL + %20:gr64 = COPY killed $rdx + %19:gr64 = COPY killed $rax + %24:gr32 = COPY %20.sub_32bit + %23:gr64 = COPY %19 + INLINEASM &"# LLVM BB: BB_32", 1 /* sideeffect attdialect */ + MOV64mr %stack.6, 1, $noreg, 0, $noreg, %23 :: (store (s64) into %ir.8) + MOV32mr %stack.7, 1, $noreg, 0, $noreg, %24 :: (store (s32) into %ir.9) + %21:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %21 + CALL64pcrel32 @_ZN3c106ScalarD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + JMP_1 %bb.13 + + bb.9.BB_33 (landing-pad): + successors: %bb.12(0x80000000) + liveins: $rax, $rdx + + EH_LABEL + %30:gr64 = COPY killed $rdx + %29:gr64 = COPY killed $rax + %33:gr32 = COPY %30.sub_32bit + %32:gr64 = COPY %29 + INLINEASM &"# LLVM BB: BB_33", 1 /* sideeffect attdialect */ + MOV64mr %stack.6, 1, $noreg, 0, $noreg, %32 :: (store (s64) into %ir.8) + MOV32mr %stack.7, 1, $noreg, 0, $noreg, %33 :: (store (s32) into %ir.9) + JMP_1 %bb.12 + + bb.10.BB_34 (landing-pad): + successors: %bb.12(0x80000000) + liveins: $rax, $rdx + + EH_LABEL + %40:gr64 = COPY killed $rdx + %39:gr64 = COPY killed $rax + %44:gr32 = COPY %40.sub_32bit + %43:gr64 = COPY %39 + INLINEASM &"# LLVM BB: BB_34", 1 /* sideeffect attdialect */ + MOV64mr %stack.6, 1, $noreg, 0, $noreg, %43 :: (store (s64) into %ir.8) + MOV32mr %stack.7, 1, $noreg, 0, $noreg, %44 :: (store (s32) into %ir.9) + %41:gr64 = LEA64r %stack.9, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %41 + CALL64pcrel32 @_ZN3c106ScalarD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + JMP_1 %bb.12 + + bb.11.BB_35 (landing-pad): + successors: %bb.12(0x80000000) + liveins: $rax, $rdx + + EH_LABEL + %52:gr64 = COPY killed $rdx + %51:gr64 = COPY killed $rax + %56:gr32 = COPY %52.sub_32bit + %55:gr64 = COPY %51 + INLINEASM &"# LLVM BB: BB_35", 1 /* sideeffect attdialect */ + MOV64mr %stack.6, 1, $noreg, 0, $noreg, %55 :: (store (s64) into %ir.8) + MOV32mr %stack.7, 1, $noreg, 0, $noreg, %56 :: (store (s32) into %ir.9) + %53:gr64 = LEA64r %stack.8, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %53 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + + bb.12.BB_36: + successors: %bb.13(0x80000000) + + INLINEASM &"# LLVM BB: BB_36", 1 /* sideeffect attdialect */ + %58:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %58 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + + bb.13.BB_37: + successors: %bb.14(0x80000000) + + INLINEASM &"# LLVM BB: BB_37", 1 /* sideeffect attdialect */ + %59:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %59 + CALL64pcrel32 @_ZN2at6TensorD2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + + bb.14.BB_38: + INLINEASM &"# LLVM BB: BB_38", 1 /* sideeffect attdialect */ + %61:gr64 = MOV64rm %stack.6, 1, $noreg, 0, $noreg :: (load (s64) from %ir.8) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %61 + CALL64pcrel32 target-flags(x86-plt) @_Unwind_Resume, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + +... +--- +name: _ZNK2at6Tensor8int_reprEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_39: + liveins: $rdi, $rsi + + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %2:gr64 = COPY %0 + INLINEASM &"# LLVM BB: BB_39", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.2) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.3) + %4:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %0 + $rsi = COPY %4 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops8int_repr4callERKNS_6TensorE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %2 + RET64 implicit $rax + +... +--- +name: _ZN2atgtERKNS_6TensorERKN3c106ScalarE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } + - { reg: '$rdx', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_40: + liveins: $rdi, $rsi, $rdx + + %2:gr64 = COPY $rdx + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + INLINEASM &"# LLVM BB: BB_40", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.3) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.4) + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.5) + %6:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.4) + %5:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %0 + $rsi = COPY %6 + $rdx = COPY %5 + CALL64pcrel32 @_ZNK2at6Tensor2gtERKN3c106ScalarE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN3c106ScalarC2El +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr32, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_41: + liveins: $rdi, $rsi + + %2:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + %3:gr64 = COPY killed %2 + INLINEASM &"# LLVM BB: BB_41", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.2) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.3) + %8:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.2) + %7:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + %6:gr32 = MOV32ri 1 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %8 + $rsi = COPY %7 + $edx = COPY %6 + CALL64pcrel32 @_ZN3c106ScalarC2IlLPb0EEET_b, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $edx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN3c106ScalarD2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_42: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_42", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %2:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.1) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %2 + CALL64pcrel32 @_ZN3c106Scalar7destroyEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.1 + + bb.1.BB_43: + INLINEASM &"# LLVM BB: BB_43", 1 /* sideeffect attdialect */ + RET64 + + bb.2.BB_44 (landing-pad): + liveins: $rax, $rdx + + EH_LABEL + %4:gr64 = COPY killed $rdx + %3:gr64 = COPY killed $rax + %7:gr32 = COPY %4.sub_32bit + %6:gr64 = COPY %3 + INLINEASM &"# LLVM BB: BB_44", 1 /* sideeffect attdialect */ + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %6 + CALL64pcrel32 @__clang_call_terminate, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + +... +--- +name: _ZN2at5whereERKNS_6TensorES2_RKN3c106ScalarE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } + - { reg: '$rdx', virtual-reg: '%2' } + - { reg: '$rcx', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_45: + liveins: $rdi, $rsi, $rdx, $rcx + + %3:gr64 = COPY $rcx + %2:gr64 = COPY $rdx + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %4:gr64 = COPY %0 + INLINEASM &"# LLVM BB: BB_45", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.4) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.5) + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.6) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.7) + %10:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + %9:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.6) + %8:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %ir.7) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %0 + $rsi = COPY %10 + $rdx = COPY %9 + $rcx = COPY %8 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops17where_ScalarOther4callERKNS_6TensorES4_RKN3c106ScalarE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %4 + RET64 implicit $rax + +... +--- +name: _ZN2at33_make_per_tensor_quantized_tensorERKNS_6TensorEdl +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: fr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: fr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: fr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } + - { reg: '$xmm0', virtual-reg: '%2' } + - { reg: '$rdx', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_46: + liveins: $rdi, $rsi, $xmm0, $rdx + + %3:gr64 = COPY $rdx + %2:fr64 = COPY $xmm0 + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %4:gr64 = COPY %0 + INLINEASM &"# LLVM BB: BB_46", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.4) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.5) + MOVSDmr %stack.2, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.6) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.7) + %10:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + %9:fr64 = MOVSDrm_alt %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.6) + %8:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %ir.7) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %0 + $rsi = COPY %10 + $xmm0 = COPY %9 + $rdx = COPY %8 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops33_make_per_tensor_quantized_tensor4callERKNS_6TensorEdl, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $xmm0, implicit $rdx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %4 + RET64 implicit $rax + +... +--- +name: _ZNK3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEptEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_47: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_47", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %5:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + %4:gr64 = MOV64rm %5, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + $rax = COPY %4 + RET64 implicit $rax + +... +--- +name: _ZNK3c1010TensorImpl5numelEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr8, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr8, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_48: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $rdi + + %1:gr64 = COPY $rdi + %2:gr64 = COPY killed %1 + INLINEASM &"# LLVM BB: BB_48", 1 /* sideeffect attdialect */ + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.2) + %6:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.2) + %4:gr32 = MOV32ri 2 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %6 + $esi = COPY %4 + CALL64pcrel32 @_ZNK3c1010TensorImpl14matches_policyENS0_18SizesStridesPolicyE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit-def $al + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %5:gr8 = COPY $al + TEST8ri %5, 1, implicit-def $eflags + JCC_1 %bb.1, 5, implicit $eflags + JMP_1 %bb.2 + + bb.1.BB_49: + successors: %bb.3(0x80000000) + + INLINEASM &"# LLVM BB: BB_49", 1 /* sideeffect attdialect */ + %13:gr64 = MOV64rm %6, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %6 + CALL64m %13, 1, $noreg, 80, $noreg, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax :: (load (s64) from %ir.7) + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %11:gr64 = COPY $rax + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %11 :: (store (s64) into %ir.1) + JMP_1 %bb.3 + + bb.2.BB_50: + successors: %bb.3(0x80000000) + + INLINEASM &"# LLVM BB: BB_50", 1 /* sideeffect attdialect */ + %8:gr64 = MOV64rm %6, 1, $noreg, 168, $noreg :: (load (s64) from %ir.10) + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %8 :: (store (s64) into %ir.1) + + bb.3.BB_51: + INLINEASM &"# LLVM BB: BB_51", 1 /* sideeffect attdialect */ + %15:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + $rax = COPY %15 + RET64 implicit $rax + +... +--- +name: _ZNK3c1010TensorImpl14matches_policyENS0_18SizesStridesPolicyE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr32, preferred-register: '' } + - { id: 2, class: gr8, preferred-register: '' } + - { id: 3, class: gr8, preferred-register: '' } + - { id: 4, class: gr8, preferred-register: '' } + - { id: 5, class: gr32, preferred-register: '' } + - { id: 6, class: gr8, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr32, preferred-register: '' } + - { id: 9, class: gr8, preferred-register: '' } + - { id: 10, class: gr32, preferred-register: '' } + - { id: 11, class: gr8, preferred-register: '' } + - { id: 12, class: gr32, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr32, preferred-register: '' } + - { id: 15, class: gr32, preferred-register: '' } + - { id: 16, class: gr8, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$esi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_52: + liveins: $rdi, $esi + + %1:gr32 = COPY $esi + %0:gr64 = COPY $rdi + %2:gr8 = COPY %1.sub_8bit + INLINEASM &"# LLVM BB: BB_52", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.2) + MOV8mr %stack.1, 1, $noreg, 0, $noreg, %2 :: (store (s8) into %ir.3) + %13:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.2) + %14:gr32 = MOVZX32rm16 killed %13, 1, $noreg, 181, $noreg :: (load (s16) from %ir.6, align 1) + %15:gr32 = SHR32ri %14, 10, implicit-def dead $eflags + %16:gr8 = COPY %15.sub_8bit + %11:gr8 = AND8ri %16, 3, implicit-def dead $eflags + %12:gr32 = MOVZX32rr8 %11 + %10:gr32 = MOVZX32rm8 %stack.1, 1, $noreg, 0, $noreg :: (load (s8) from %ir.3) + CMP32rr %12, %10, implicit-def $eflags + %6:gr8 = SETCCr 13, implicit $eflags + %4:gr8 = AND8ri %6, 1, implicit-def $eflags + %5:gr32 = MOVZX32rr8 %4 + $eax = COPY %5 + RET64 implicit $eax + +... +--- +name: _ZN2at10TensorBaseC2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_53: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_53", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %4:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %4 + CALL64pcrel32 @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_54: + successors: %bb.1(0x80000000) + liveins: $rdi + + %2:gr64 = COPY $rdi + %3:gr64 = COPY killed %2 + INLINEASM &"# LLVM BB: BB_54", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.1) + %5:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 @_ZN3c1019UndefinedTensorImpl9singletonEv, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %4:gr64 = COPY $rax + + bb.1.BB_55: + INLINEASM &"# LLVM BB: BB_55", 1 /* sideeffect attdialect */ + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %5 + $rsi = COPY %4 + CALL64pcrel32 @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2EPS1_NS_3raw20DontIncreaseRefcountE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN3c1019UndefinedTensorImpl9singletonEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } +liveins: [] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_56: + INLINEASM &"# LLVM BB: BB_56", 1 /* sideeffect attdialect */ + %0:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @_ZN3c1019UndefinedTensorImpl10_singletonE, $noreg + $rax = COPY %0 + RET64 implicit $rax + +... +--- +name: __clang_call_terminate +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_57: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_57", 1 /* sideeffect attdialect */ + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %1 + CALL64pcrel32 target-flags(x86-plt) @__cxa_begin_catch, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %2:gr64 = COPY $rax + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 target-flags(x86-plt) @_ZSt9terminatev, csr_64, implicit $rsp, implicit $ssp + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + +... +--- +name: _ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2EPS1_NS_3raw20DontIncreaseRefcountE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_58: + liveins: $rdi, $rsi + + %2:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + %3:gr64 = COPY killed %2 + INLINEASM &"# LLVM BB: BB_58", 1 /* sideeffect attdialect */ + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.3) + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.4) + %7:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + %6:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.4) + MOV64mr %7, 1, $noreg, 0, $noreg, %6 :: (store (s64) into %ir.6) + RET64 + +... +--- +name: _ZN3c1017basic_string_viewIcE7strlen_EPKc +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr8, preferred-register: '' } + - { id: 6, class: gr32, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr64, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_59: + successors: %bb.1(0x80000000) + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_59", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %3:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.2) + + bb.1.BB_60: + successors: %bb.3(0x40000000), %bb.2(0x40000000) + + INLINEASM &"# LLVM BB: BB_60", 1 /* sideeffect attdialect */ + %8:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.2) + %6:gr32 = MOVSX32rm8 %8, 1, $noreg, 0, $noreg :: (load (s8) from %ir.4) + CMP32ri %6, 0, implicit-def $eflags + JCC_1 %bb.3, 4, implicit $eflags + + bb.2.BB_61: + successors: %bb.1(0x80000000) + + INLINEASM &"# LLVM BB: BB_61", 1 /* sideeffect attdialect */ + %20:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.2) + %19:gr64 = ADD64ri32 %20, 1, implicit-def $eflags + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %19 :: (store (s64) into %ir.2) + JMP_1 %bb.1 + + bb.3.BB_62: + INLINEASM &"# LLVM BB: BB_62", 1 /* sideeffect attdialect */ + %16:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.2) + %15:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + %12:gr64 = SUB64rr %16, %15, implicit-def $eflags + $rax = COPY %12 + RET64 implicit $rax + +... +--- +name: _ZN3c1017basic_string_viewIcEC2EPKcm +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%2' } + - { reg: '$rdx', virtual-reg: '%4' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_63: + liveins: $rdi, $rsi, $rdx + + %4:gr64 = COPY $rdx + %2:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + %3:gr64 = COPY killed %2 + %5:gr64 = COPY killed %4 + INLINEASM &"# LLVM BB: BB_63", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.3) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.4) + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %5 :: (store (s64) into %ir.5) + %11:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + %10:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.4) + MOV64mr %11, 1, $noreg, 0, $noreg, %10 :: (store (s64) into %ir.7) + %8:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + MOV64mr %11, 1, $noreg, 8, $noreg, %8 :: (store (s64) into %ir.9) + RET64 + +... +--- +name: _ZN3c10L20typeMetaToScalarTypeEN6caffe28TypeMetaE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr32, preferred-register: '' } + - { id: 1, class: gr16, preferred-register: '' } + - { id: 2, class: gr8, preferred-register: '' } + - { id: 3, class: gr32, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr8, preferred-register: '' } +liveins: + - { reg: '$edi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 2 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 2, alignment: 2, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_64: + liveins: $edi + + %0:gr32 = COPY $edi + %1:gr16 = COPY %0.sub_16bit + INLINEASM &"# LLVM BB: BB_64", 1 /* sideeffect attdialect */ + MOV16mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s16) into %ir.2) + %4:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %4 + CALL64pcrel32 @_ZN6caffe28TypeMeta12toScalarTypeEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $al + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %5:gr8 = COPY $al + %3:gr32 = MOVSX32rr8 %5 + $eax = COPY %3 + RET64 implicit $eax + +... +--- +name: _ZNK3c1010TensorImpl5dtypeEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr16, preferred-register: '' } + - { id: 3, class: gr16, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr16, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 2, alignment: 2, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_65: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_65", 1 /* sideeffect attdialect */ + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.2) + %6:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.2) + %5:gr16 = MOV16rm %6, 1, $noreg, 176, $noreg + MOV16mr %stack.0, 1, $noreg, 0, $noreg, %5 + %3:gr16 = MOV16rm %stack.0, 1, $noreg, 0, $noreg :: (load (s16) from %ir.7) + $ax = COPY %3 + RET64 implicit $ax + +... +--- +name: _ZN6caffe28TypeMeta12toScalarTypeEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr8, preferred-register: '' } + - { id: 4, class: gr8, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr16, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr16, preferred-register: '' } + - { id: 9, class: gr8, preferred-register: '' } + - { id: 10, class: gr32, preferred-register: '' } + - { id: 11, class: gr16, preferred-register: '' } + - { id: 12, class: gr8, preferred-register: '' } + - { id: 13, class: gr16, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 2, alignment: 2, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_66: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $rdi + + %1:gr64 = COPY $rdi + %2:gr64 = COPY killed %1 + INLINEASM &"# LLVM BB: BB_66", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.1) + %5:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %5 + CALL64pcrel32 @_ZNK6caffe28TypeMeta12isScalarTypeEv, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $al + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %4:gr8 = COPY $al + TEST8ri %4, 1, implicit-def $eflags + JCC_1 %bb.1, 5, implicit $eflags + JMP_1 %bb.2 + + bb.1.BB_67: + INLINEASM &"# LLVM BB: BB_67", 1 /* sideeffect attdialect */ + %13:gr16 = MOV16rm %5, 1, $noreg, 0, $noreg :: (load (s16) from %ir.5) + %12:gr8 = COPY %13.sub_8bit + %10:gr32 = MOVSX32rr8 %12 + $eax = COPY %10 + RET64 implicit $eax + + bb.2.BB_68: + INLINEASM &"# LLVM BB: BB_68", 1 /* sideeffect attdialect */ + %8:gr16 = MOV16rm %5, 1, $noreg, 0, $noreg + MOV16mr %stack.1, 1, $noreg, 0, $noreg, %8 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %7:gr32 = MOVZX32rm16 %stack.1, 1, $noreg, 0, $noreg :: (load (s16) from %ir.10) + $edi = COPY %7 + CALL64pcrel32 target-flags(x86-plt) @_ZN6caffe28TypeMeta26error_unsupported_typemetaES0_, csr_64, implicit $rsp, implicit $ssp, implicit $edi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + +... +--- +name: _ZNK6caffe28TypeMeta12isScalarTypeEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr8, preferred-register: '' } + - { id: 3, class: gr8, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr8, preferred-register: '' } + - { id: 6, class: gr32, preferred-register: '' } + - { id: 7, class: gr16, preferred-register: '' } + - { id: 8, class: gr32, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_69: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_69", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %10:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + %8:gr32 = MOVZX32rm16 %10, 1, $noreg, 0, $noreg :: (load (s16) from %ir.3) + CMP32ri %8, 26, implicit-def $eflags + %5:gr8 = SETCCr 12, implicit $eflags + %3:gr8 = AND8ri %5, 1, implicit-def $eflags + %4:gr32 = MOVZX32rr8 %3 + $eax = COPY %4 + RET64 implicit $eax + +... +--- +name: _ZN2at10TensorBaseD2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_70: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_70", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %4:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %4 + CALL64pcrel32 @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEED2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEED2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_71: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_71", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %3:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %3 + CALL64pcrel32 @_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEE6reset_Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEE6reset_Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr32, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr64, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr32, preferred-register: '' } + - { id: 21, class: gr32, preferred-register: '' } + - { id: 22, class: gr32, preferred-register: '' } + - { id: 23, class: gr32, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr64, preferred-register: '' } + - { id: 29, class: gr64, preferred-register: '' } + - { id: 30, class: gr64, preferred-register: '' } + - { id: 31, class: gr32, preferred-register: '' } + - { id: 32, class: gr32, preferred-register: '' } + - { id: 33, class: gr32, preferred-register: '' } + - { id: 34, class: gr32, preferred-register: '' } + - { id: 35, class: gr64, preferred-register: '' } + - { id: 36, class: gr64, preferred-register: '' } + - { id: 37, class: gr64, preferred-register: '' } + - { id: 38, class: gr8, preferred-register: '' } + - { id: 39, class: gr8, preferred-register: '' } + - { id: 40, class: gr8, preferred-register: '' } + - { id: 41, class: gr8, preferred-register: '' } + - { id: 42, class: gr8, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: gr64, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: gr64, preferred-register: '' } + - { id: 47, class: gr64, preferred-register: '' } + - { id: 48, class: gr64, preferred-register: '' } + - { id: 49, class: gr64, preferred-register: '' } + - { id: 50, class: gr64, preferred-register: '' } + - { id: 51, class: gr32, preferred-register: '' } + - { id: 52, class: gr64, preferred-register: '' } + - { id: 53, class: gr64, preferred-register: '' } + - { id: 54, class: gr64, preferred-register: '' } + - { id: 55, class: gr64, preferred-register: '' } + - { id: 56, class: gr64, preferred-register: '' } + - { id: 57, class: gr64, preferred-register: '' } + - { id: 58, class: gr8, preferred-register: '' } + - { id: 59, class: gr8, preferred-register: '' } + - { id: 60, class: gr8, preferred-register: '' } + - { id: 61, class: gr8, preferred-register: '' } + - { id: 62, class: gr8, preferred-register: '' } + - { id: 63, class: gr64, preferred-register: '' } + - { id: 64, class: gr64, preferred-register: '' } + - { id: 65, class: gr64, preferred-register: '' } + - { id: 66, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%7' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_72: + successors: %bb.17(0x40000000), %bb.1(0x40000000) + liveins: $rdi + + %7:gr64 = COPY $rdi + %8:gr64 = COPY killed %7 + INLINEASM &"# LLVM BB: BB_72", 1 /* sideeffect attdialect */ + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %8 :: (store (s64) into %ir.5) + %13:gr64 = MOV64rm %stack.4, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + %12:gr64 = MOV64rm %13, 1, $noreg, 0, $noreg :: (load (s64) from %ir.8) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 @_ZN3c1019UndefinedTensorImpl9singletonEv, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %11:gr64 = COPY $rax + CMP64rr %12, %11, implicit-def $eflags + JCC_1 %bb.17, 4, implicit $eflags + + bb.1.BB_73: + successors: %bb.2(0x80000000) + + INLINEASM &"# LLVM BB: BB_73", 1 /* sideeffect attdialect */ + %19:gr64 = MOV64rm %13, 1, $noreg, 0, $noreg :: (load (s64) from %ir.12) + %17:gr64 = ADD64ri32 %19, 8, implicit-def $eflags + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %17 + CALL64pcrel32 @_ZN3c106detail25atomic_refcount_decrementERSt6atomicImE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %15:gr64 = COPY $rax + + bb.2.BB_74: + successors: %bb.17(0x40000000), %bb.3(0x40000000) + + INLINEASM &"# LLVM BB: BB_74", 1 /* sideeffect attdialect */ + CMP64ri32 %15, 0, implicit-def $eflags + JCC_1 %bb.17, 5, implicit $eflags + + bb.3.BB_75: + successors: %bb.4(0x80000000) + + INLINEASM &"# LLVM BB: BB_75", 1 /* sideeffect attdialect */ + %30:gr64 = MOV64rm %13, 1, $noreg, 0, $noreg :: (load (s64) from %ir.18) + %28:gr64 = ADD64ri32 %30, 16, implicit-def $eflags + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %28 :: (store (s64) into %ir.1) + MOV32mi %stack.1, 1, $noreg, 0, $noreg, 2 :: (store (s32) into %ir.2) + %24:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + %23:gr32 = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %ir.2) + %21:gr32 = MOV32ri 65535 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $edi = COPY %23 + $esi = COPY %21 + CALL64pcrel32 @_ZStanSt12memory_orderSt23__memory_order_modifier, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $eax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %22:gr32 = COPY $eax + + bb.4.BB_76: + successors: %bb.6(0x40000000), %bb.19(0x40000000) + + INLINEASM &"# LLVM BB: BB_76", 1 /* sideeffect attdialect */ + MOV32mr %stack.2, 1, $noreg, 0, $noreg, %22 :: (store (s32) into %ir.3) + %4:gr64 = COPY %24 + %31:gr32 = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.2) + %32:gr32 = DEC32r %31, implicit-def dead $eflags + %33:gr32 = SUB32ri %32, 2, implicit-def $eflags + JCC_1 %bb.6, 2, implicit $eflags + JMP_1 %bb.19 + + bb.19.BB_76: + successors: %bb.7(0x40000000), %bb.5(0x40000000) + + %34:gr32 = SUB32ri %31, 5, implicit-def $eflags + JCC_1 %bb.7, 4, implicit $eflags + JMP_1 %bb.5 + + bb.5.BB_77: + successors: %bb.8(0x80000000) + + INLINEASM &"# LLVM BB: BB_77", 1 /* sideeffect attdialect */ + %37:gr64 = MOV64rm %4, 1, $noreg, 0, $noreg :: (load monotonic (s64) from %ir.26) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %37 :: (store (s64) into %ir.4) + JMP_1 %bb.8 + + bb.6.BB_78: + successors: %bb.8(0x80000000) + + INLINEASM &"# LLVM BB: BB_78", 1 /* sideeffect attdialect */ + %36:gr64 = MOV64rm %4, 1, $noreg, 0, $noreg :: (load acquire (s64) from %ir.26) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %36 :: (store (s64) into %ir.4) + JMP_1 %bb.8 + + bb.7.BB_79: + successors: %bb.8(0x80000000) + + INLINEASM &"# LLVM BB: BB_79", 1 /* sideeffect attdialect */ + %35:gr64 = MOV64rm %4, 1, $noreg, 0, $noreg :: (load seq_cst (s64) from %ir.26) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %35 :: (store (s64) into %ir.4) + + bb.8.BB_80: + successors: %bb.12(0x40000000), %bb.9(0x40000000) + + INLINEASM &"# LLVM BB: BB_80", 1 /* sideeffect attdialect */ + CMP64mi32 %stack.3, 1, $noreg, 0, $noreg, 1, implicit-def $eflags :: (load (s64) from %ir.4) + %42:gr8 = SETCCr 4, implicit $eflags + %41:gr8 = AND8ri %42, 1, implicit-def $eflags + MOV8mr %stack.5, 1, $noreg, 0, $noreg, %41 :: (store (s8) into %ir.6) + TEST8mi %stack.5, 1, $noreg, 0, $noreg, 1, implicit-def $eflags :: (load (s8) from %ir.6) + JCC_1 %bb.12, 5, implicit $eflags + + bb.9.BB_81: + successors: %bb.10(0x40000000), %bb.18(0x40000000) + + INLINEASM &"# LLVM BB: BB_81", 1 /* sideeffect attdialect */ + %44:gr64 = MOV64rm %13, 1, $noreg, 0, $noreg :: (load (s64) from %ir.36) + %45:gr64 = MOV64rm %44, 1, $noreg, 0, $noreg :: (load (s64) from %ir.38) + %46:gr64 = MOV64rm killed %45, 1, $noreg, 16, $noreg :: (load (s64) from %ir.40) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %44 + CALL64r killed %46, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.10 + + bb.10.BB_82: + successors: %bb.11(0x80000000) + + INLINEASM &"# LLVM BB: BB_82", 1 /* sideeffect attdialect */ + %57:gr64 = MOV64rm %13, 1, $noreg, 0, $noreg :: (load (s64) from %ir.42) + %55:gr64 = ADD64ri32 %57, 16, implicit-def $eflags + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %55 + CALL64pcrel32 @_ZN3c106detail26atomic_weakcount_decrementERSt6atomicImE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %53:gr64 = COPY $rax + + bb.11.BB_83: + successors: %bb.12(0x80000000) + + INLINEASM &"# LLVM BB: BB_83", 1 /* sideeffect attdialect */ + CMP64ri32 %53, 0, implicit-def $eflags + %61:gr8 = SETCCr 4, implicit $eflags + %60:gr8 = AND8ri %61, 1, implicit-def $eflags + MOV8mr %stack.5, 1, $noreg, 0, $noreg, %60 :: (store (s8) into %ir.6) + + bb.12.BB_84: + successors: %bb.16(0x40000000), %bb.13(0x40000000) + + INLINEASM &"# LLVM BB: BB_84", 1 /* sideeffect attdialect */ + TEST8mi %stack.5, 1, $noreg, 0, $noreg, 1, implicit-def $eflags :: (load (s8) from %ir.6) + JCC_1 %bb.16, 4, implicit $eflags + + bb.13.BB_85: + successors: %bb.15(0x40000000), %bb.14(0x40000000) + + INLINEASM &"# LLVM BB: BB_85", 1 /* sideeffect attdialect */ + %63:gr64 = MOV64rm %13, 1, $noreg, 0, $noreg :: (load (s64) from %ir.51) + CMP64ri32 %63, 0, implicit-def $eflags + JCC_1 %bb.15, 4, implicit $eflags + + bb.14.BB_86: + successors: %bb.15(0x80000000) + + INLINEASM &"# LLVM BB: BB_86", 1 /* sideeffect attdialect */ + %66:gr64 = MOV64rm %63, 1, $noreg, 0, $noreg :: (load (s64) from %ir.54) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %63 + CALL64m %66, 1, $noreg, 8, $noreg, csr_64, implicit $rsp, implicit $ssp, implicit $rdi :: (load (s64) from %ir.56) + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + + bb.15.BB_87: + successors: %bb.16(0x80000000) + + INLINEASM &"# LLVM BB: BB_87", 1 /* sideeffect attdialect */ + + bb.16.BB_88: + successors: %bb.17(0x80000000) + + INLINEASM &"# LLVM BB: BB_88", 1 /* sideeffect attdialect */ + + bb.17.BB_89: + INLINEASM &"# LLVM BB: BB_89", 1 /* sideeffect attdialect */ + RET64 + + bb.18.BB_90 (landing-pad): + liveins: $rax, $rdx + + EH_LABEL + %48:gr64 = COPY killed $rdx + %47:gr64 = COPY killed $rax + %51:gr32 = COPY %48.sub_32bit + %50:gr64 = COPY %47 + INLINEASM &"# LLVM BB: BB_90", 1 /* sideeffect attdialect */ + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %50 + CALL64pcrel32 @__clang_call_terminate, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + +... +--- +name: _ZN3c106detail25atomic_refcount_decrementERSt6atomicImE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64_nosp, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr32, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr32, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr64, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +jumpTable: + kind: block-address + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.2', '%bb.3', '%bb.4', '%bb.5' ] +body: | + bb.0.BB_91: + successors: %bb.1(0x40000000), %bb.7(0x40000000) + liveins: $rdi + + %1:gr64 = COPY $rdi + %2:gr64 = COPY killed %1 + INLINEASM &"# LLVM BB: BB_91", 1 /* sideeffect attdialect */ + MOV64mr %stack.5, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.6) + %4:gr64 = MOV64rm %stack.5, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.6) + MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed %4 :: (store (s64) into %ir.1) + MOV64mi32 %stack.1, 1, $noreg, 0, $noreg, 1 :: (store (s64) into %ir.2) + MOV32mi %stack.2, 1, $noreg, 0, $noreg, 4 :: (store (s32) into %ir.3) + %0:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.1) + %5:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.3) + %6:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.2) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, killed %6 :: (store (s64) into %ir.4) + %7:gr32 = DEC32r %5, implicit-def dead $eflags + %3:gr64_nosp = SUBREG_TO_REG 0, %7, %subreg.sub_32bit + %8:gr32 = SUB32ri %7, 4, implicit-def $eflags + JCC_1 %bb.1, 7, implicit $eflags + + bb.7.BB_91: + successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000) + + %9:gr64 = MOV64rm $noreg, 8, %3, %jump-table.0, $noreg :: (load (s64) from jump-table) + JMP64r killed %9 + + bb.1.BB_92: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_92", 1 /* sideeffect attdialect */ + %23:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %24:gr64 = NEG64r %23, implicit-def dead $eflags + %22:gr64 = LXADD64 %24, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store monotonic (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %22 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.2.BB_93: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_93", 1 /* sideeffect attdialect */ + %20:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %21:gr64 = NEG64r %20, implicit-def dead $eflags + %19:gr64 = LXADD64 %21, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store acquire (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %19 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.3.BB_94: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_94", 1 /* sideeffect attdialect */ + %17:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %18:gr64 = NEG64r %17, implicit-def dead $eflags + %16:gr64 = LXADD64 %18, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store release (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %16 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.4.BB_95: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_95", 1 /* sideeffect attdialect */ + %14:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %15:gr64 = NEG64r %14, implicit-def dead $eflags + %13:gr64 = LXADD64 %15, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store acq_rel (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %13 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.5.BB_96: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_96", 1 /* sideeffect attdialect */ + %11:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %12:gr64 = NEG64r %11, implicit-def dead $eflags + %10:gr64 = LXADD64 %12, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store seq_cst (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %10 :: (store (s64) into %ir.5) + + bb.6.BB_97: + INLINEASM &"# LLVM BB: BB_97", 1 /* sideeffect attdialect */ + %28:gr64 = MOV64rm %stack.4, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + %27:gr64 = SUB64ri32 %28, 1, implicit-def $eflags + $rax = COPY %27 + RET64 implicit $rax + +... +--- +name: _ZN3c106detail26atomic_weakcount_decrementERSt6atomicImE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64_nosp, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr32, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr32, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr64, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +jumpTable: + kind: block-address + entries: + - id: 0 + blocks: [ '%bb.2', '%bb.2', '%bb.3', '%bb.4', '%bb.5' ] +body: | + bb.0.BB_98: + successors: %bb.1(0x40000000), %bb.7(0x40000000) + liveins: $rdi + + %1:gr64 = COPY $rdi + %2:gr64 = COPY killed %1 + INLINEASM &"# LLVM BB: BB_98", 1 /* sideeffect attdialect */ + MOV64mr %stack.5, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.6) + %4:gr64 = MOV64rm %stack.5, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.6) + MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed %4 :: (store (s64) into %ir.1) + MOV64mi32 %stack.1, 1, $noreg, 0, $noreg, 1 :: (store (s64) into %ir.2) + MOV32mi %stack.2, 1, $noreg, 0, $noreg, 4 :: (store (s32) into %ir.3) + %0:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.1) + %5:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.3) + %6:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.2) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, killed %6 :: (store (s64) into %ir.4) + %7:gr32 = DEC32r %5, implicit-def dead $eflags + %3:gr64_nosp = SUBREG_TO_REG 0, %7, %subreg.sub_32bit + %8:gr32 = SUB32ri %7, 4, implicit-def $eflags + JCC_1 %bb.1, 7, implicit $eflags + + bb.7.BB_98: + successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000) + + %9:gr64 = MOV64rm $noreg, 8, %3, %jump-table.0, $noreg :: (load (s64) from jump-table) + JMP64r killed %9 + + bb.1.BB_99: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_99", 1 /* sideeffect attdialect */ + %23:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %24:gr64 = NEG64r %23, implicit-def dead $eflags + %22:gr64 = LXADD64 %24, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store monotonic (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %22 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.2.BB_100: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_100", 1 /* sideeffect attdialect */ + %20:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %21:gr64 = NEG64r %20, implicit-def dead $eflags + %19:gr64 = LXADD64 %21, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store acquire (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %19 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.3.BB_101: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_101", 1 /* sideeffect attdialect */ + %17:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %18:gr64 = NEG64r %17, implicit-def dead $eflags + %16:gr64 = LXADD64 %18, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store release (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %16 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.4.BB_102: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_102", 1 /* sideeffect attdialect */ + %14:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %15:gr64 = NEG64r %14, implicit-def dead $eflags + %13:gr64 = LXADD64 %15, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store acq_rel (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %13 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.5.BB_103: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_103", 1 /* sideeffect attdialect */ + %11:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (dereferenceable load (s64) from %ir.4) + %12:gr64 = NEG64r %11, implicit-def dead $eflags + %10:gr64 = LXADD64 %12, %0, 1, $noreg, 0, $noreg, implicit-def dead $eflags :: (load store seq_cst (s64) on %ir.10) + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %10 :: (store (s64) into %ir.5) + + bb.6.BB_104: + INLINEASM &"# LLVM BB: BB_104", 1 /* sideeffect attdialect */ + %28:gr64 = MOV64rm %stack.4, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + %27:gr64 = SUB64ri32 %28, 1, implicit-def $eflags + $rax = COPY %27 + RET64 implicit $rax + +... +--- +name: _ZStanSt12memory_orderSt23__memory_order_modifier +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr32, preferred-register: '' } + - { id: 1, class: gr32, preferred-register: '' } + - { id: 2, class: gr32, preferred-register: '' } + - { id: 3, class: gr32, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr32, preferred-register: '' } + - { id: 6, class: gr32, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr32, preferred-register: '' } +liveins: + - { reg: '$edi', virtual-reg: '%0' } + - { reg: '$esi', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_105: + liveins: $edi, $esi + + %2:gr32 = COPY $esi + %0:gr32 = COPY $edi + %1:gr32 = COPY killed %0 + %3:gr32 = COPY killed %2 + INLINEASM &"# LLVM BB: BB_105", 1 /* sideeffect attdialect */ + MOV32mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s32) into %ir.2) + MOV32mr %stack.1, 1, $noreg, 0, $noreg, %3 :: (store (s32) into %ir.3) + %8:gr32 = MOV32rm %stack.0, 1, $noreg, 0, $noreg :: (load (s32) from %ir.2) + %7:gr32 = AND32rm %8, %stack.1, 1, $noreg, 0, $noreg, implicit-def $eflags :: (load (s32) from %ir.3) + $eax = COPY %7 + RET64 implicit $eax + +... +--- +name: _ZNK2at6Tensor2gtERKN3c106ScalarE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } + - { reg: '$rdx', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_106: + liveins: $rdi, $rsi, $rdx + + %2:gr64 = COPY $rdx + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %3:gr64 = COPY %0 + INLINEASM &"# LLVM BB: BB_106", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.3) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.4) + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.5) + %7:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.4) + %6:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %0 + $rsi = COPY %7 + $rdx = COPY %6 + CALL64pcrel32 target-flags(x86-plt) @_ZN2at4_ops9gt_Scalar4callERKNS_6TensorERKN3c106ScalarE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %3 + RET64 implicit $rax + +... +--- +name: _ZN3c106ScalarC2IlLPb0EEET_b +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr32, preferred-register: '' } + - { id: 3, class: gr8, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr8, preferred-register: '' } + - { id: 13, class: gr8, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%1' } + - { reg: '$edx', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_107: + liveins: $rdi, $rsi, $edx + + %2:gr32 = COPY $edx + %1:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %3:gr8 = COPY %2.sub_8bit + INLINEASM &"# LLVM BB: BB_107", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %0 :: (store (s64) into %ir.3) + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.4) + %13:gr8 = AND8ri %3, 1, implicit-def $eflags + MOV8mr %stack.2, 1, $noreg, 0, $noreg, %13 :: (store (s8) into %ir.5) + %11:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + MOV32mi %11, 1, $noreg, 0, $noreg, 1 :: (store (s32) into %ir.8, align 16) + %10:gr64 = ADD64ri32 %11, 16, implicit-def $eflags + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %10 + CALL64pcrel32 @_ZN3c106Scalar3v_tC2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %8:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.4) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %8 + CALL64pcrel32 @_ZN3c107convertIllEET_T0_, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %7:gr64 = COPY $rax + MOV64mr %11, 1, $noreg, 16, $noreg, %7 :: (store (s64) into %ir.13, align 16) + RET64 + +... +--- +name: _ZN3c106Scalar3v_tC2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: fr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_108: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_108", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %4:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + %3:fr64 = FsFLD0SD + MOVSDmr %4, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.3, align 16) + RET64 + +... +--- +name: _ZN3c107convertIllEET_T0_ +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_109: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_109", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %5:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %5 + CALL64pcrel32 @_ZN3c1027static_cast_with_inter_typeIllE5applyEl, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %4:gr64 = COPY $rax + $rax = COPY %4 + RET64 implicit $rax + +... +--- +name: _ZN3c1027static_cast_with_inter_typeIllE5applyEl +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_110: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_110", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + MOV8mi %stack.1, 1, $noreg, 0, $noreg, 0 :: (store (s8) into %ir.2) + %7:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %7 + CALL64pcrel32 @_ZN3c1010maybe_realILb0ElE5applyEl, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %6:gr64 = COPY $rax + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %6 :: (store (s64) into %ir.3) + %3:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + $rax = COPY %3 + RET64 implicit $rax + +... +--- +name: _ZN3c1010maybe_realILb0ElE5applyEl +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_111: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_111", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %3:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + $rax = COPY %3 + RET64 implicit $rax + +... +--- +name: _ZN3c106Scalar7destroyEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr32, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr32, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr32, preferred-register: '' } + - { id: 9, class: gr32, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_112: + successors: %bb.3(0x40000000), %bb.1(0x40000000) + liveins: $rdi + + %1:gr64 = COPY $rdi + %2:gr64 = COPY killed %1 + INLINEASM &"# LLVM BB: BB_112", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %2 :: (store (s64) into %ir.1) + %5:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + %3:gr32 = MOV32ri 5 + CMP32rm %3, %5, 1, $noreg, 0, $noreg, implicit-def $eflags :: (load (s32) from %ir.3, align 16) + JCC_1 %bb.3, 4, implicit $eflags + + bb.1.BB_113: + successors: %bb.3(0x40000000), %bb.2(0x40000000) + + INLINEASM &"# LLVM BB: BB_113", 1 /* sideeffect attdialect */ + %6:gr32 = MOV32ri 4 + CMP32rm %6, %5, 1, $noreg, 0, $noreg, implicit-def $eflags :: (load (s32) from %ir.6, align 16) + JCC_1 %bb.3, 4, implicit $eflags + + bb.2.BB_114: + successors: %bb.4(0x40000000), %bb.3(0x40000000) + + INLINEASM &"# LLVM BB: BB_114", 1 /* sideeffect attdialect */ + %8:gr32 = MOV32ri 6 + CMP32rm %8, %5, 1, $noreg, 0, $noreg, implicit-def $eflags :: (load (s32) from %ir.9, align 16) + JCC_1 %bb.4, 5, implicit $eflags + + bb.3.BB_115: + successors: %bb.4(0x80000000) + + INLINEASM &"# LLVM BB: BB_115", 1 /* sideeffect attdialect */ + %11:gr64 = MOV64rm %5, 1, $noreg, 16, $noreg :: (load (s64) from %ir.13, align 16) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %11 + CALL64pcrel32 @_ZN3c103raw13intrusive_ptr6decrefEPNS_20intrusive_ptr_targetE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + MOV64mi32 %5, 1, $noreg, 16, $noreg, 0 :: (store (s64) into %ir.16, align 16) + + bb.4.BB_116: + INLINEASM &"# LLVM BB: BB_116", 1 /* sideeffect attdialect */ + RET64 + +... +--- +name: _ZN3c103raw13intrusive_ptr6decrefEPNS_20intrusive_ptr_targetE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_117: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_117", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %5:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + %3:gr64 = LEA64r %stack.1, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %3 + $rsi = COPY %5 + CALL64pcrel32 @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %2:gr64 = LEA64r %stack.1, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %2 + CALL64pcrel32 @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEED2Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_ +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr32, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr8, preferred-register: '' } + - { id: 7, class: gr8, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr8, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr32, preferred-register: '' } + - { id: 18, class: gr32, preferred-register: '' } + - { id: 19, class: gr32, preferred-register: '' } + - { id: 20, class: gr32, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr32, preferred-register: '' } + - { id: 28, class: gr32, preferred-register: '' } + - { id: 29, class: gr32, preferred-register: '' } + - { id: 30, class: gr32, preferred-register: '' } + - { id: 31, class: gr64, preferred-register: '' } + - { id: 32, class: gr64, preferred-register: '' } + - { id: 33, class: gr64, preferred-register: '' } + - { id: 34, class: gr8, preferred-register: '' } + - { id: 35, class: gr64, preferred-register: '' } + - { id: 36, class: gr32, preferred-register: '' } + - { id: 37, class: gr32, preferred-register: '' } + - { id: 38, class: gr32, preferred-register: '' } + - { id: 39, class: gr32, preferred-register: '' } + - { id: 40, class: gr64, preferred-register: '' } + - { id: 41, class: gr64, preferred-register: '' } + - { id: 42, class: gr64, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: gr64, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: gr32, preferred-register: '' } + - { id: 47, class: gr32, preferred-register: '' } + - { id: 48, class: gr32, preferred-register: '' } + - { id: 49, class: gr32, preferred-register: '' } + - { id: 50, class: gr64, preferred-register: '' } + - { id: 51, class: gr64, preferred-register: '' } + - { id: 52, class: gr64, preferred-register: '' } + - { id: 53, class: gr8, preferred-register: '' } + - { id: 54, class: gr64, preferred-register: '' } + - { id: 55, class: gr8, preferred-register: '' } + - { id: 56, class: gr8, preferred-register: '' } + - { id: 57, class: gr64, preferred-register: '' } + - { id: 58, class: gr64, preferred-register: '' } + - { id: 59, class: gr64, preferred-register: '' } + - { id: 60, class: gr64, preferred-register: '' } + - { id: 61, class: gr32, preferred-register: '' } + - { id: 62, class: gr64, preferred-register: '' } + - { id: 63, class: gr64, preferred-register: '' } + - { id: 64, class: gr64, preferred-register: '' } + - { id: 65, class: gr64, preferred-register: '' } + - { id: 66, class: gr8, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%8' } + - { reg: '$rsi', virtual-reg: '%9' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 6, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 7, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 8, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 9, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 10, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_118: + successors: %bb.13(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $rsi + + %9:gr64 = COPY $rsi + %8:gr64 = COPY $rdi + %10:gr64 = COPY %8 + INLINEASM &"# LLVM BB: BB_118", 1 /* sideeffect attdialect */ + MOV64mr %stack.8, 1, $noreg, 0, $noreg, %8 :: (store (s64) into %ir.10) + MOV64mr %stack.9, 1, $noreg, 0, $noreg, %9 :: (store (s64) into %ir.11) + %15:gr64 = MOV64rm %stack.9, 1, $noreg, 0, $noreg :: (load (s64) from %ir.11) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 @_ZN3c106detail34intrusive_target_default_null_typeINS_20intrusive_ptr_targetEE9singletonEv, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %14:gr64 = COPY $rax + %11:gr8 = MOV8ri 1 + CMP64rr %15, %14, implicit-def $eflags + %66:gr8 = COPY %11 + JCC_1 %bb.13, 4, implicit $eflags + + bb.1.BB_119: + successors: %bb.2(0x80000000) + + INLINEASM &"# LLVM BB: BB_119", 1 /* sideeffect attdialect */ + %26:gr64 = MOV64rm %stack.9, 1, $noreg, 0, $noreg :: (load (s64) from %ir.11) + %25:gr64 = ADD64ri32 %26, 8, implicit-def $eflags + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %25 :: (store (s64) into %ir.2) + MOV32mi %stack.1, 1, $noreg, 0, $noreg, 5 :: (store (s32) into %ir.3) + %21:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.2) + %20:gr32 = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %ir.3) + %18:gr32 = MOV32ri 65535 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $edi = COPY %20 + $esi = COPY %18 + CALL64pcrel32 @_ZStanSt12memory_orderSt23__memory_order_modifier, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $eax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %19:gr32 = COPY $eax + + bb.2.BB_120: + successors: %bb.4(0x40000000), %bb.16(0x40000000) + + INLINEASM &"# LLVM BB: BB_120", 1 /* sideeffect attdialect */ + MOV32mr %stack.2, 1, $noreg, 0, $noreg, %19 :: (store (s32) into %ir.4) + %2:gr64 = COPY %21 + %27:gr32 = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.3) + %28:gr32 = DEC32r %27, implicit-def dead $eflags + %29:gr32 = SUB32ri %28, 2, implicit-def $eflags + JCC_1 %bb.4, 2, implicit $eflags + JMP_1 %bb.16 + + bb.16.BB_120: + successors: %bb.5(0x40000000), %bb.3(0x40000000) + + %30:gr32 = SUB32ri %27, 5, implicit-def $eflags + JCC_1 %bb.5, 4, implicit $eflags + JMP_1 %bb.3 + + bb.3.BB_121: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_121", 1 /* sideeffect attdialect */ + %33:gr64 = MOV64rm %2, 1, $noreg, 0, $noreg :: (load monotonic (s64) from %ir.23) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %33 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.4.BB_122: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_122", 1 /* sideeffect attdialect */ + %32:gr64 = MOV64rm %2, 1, $noreg, 0, $noreg :: (load acquire (s64) from %ir.23) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %32 :: (store (s64) into %ir.5) + JMP_1 %bb.6 + + bb.5.BB_123: + successors: %bb.6(0x80000000) + + INLINEASM &"# LLVM BB: BB_123", 1 /* sideeffect attdialect */ + %31:gr64 = MOV64rm %2, 1, $noreg, 0, $noreg :: (load seq_cst (s64) from %ir.23) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %31 :: (store (s64) into %ir.5) + + bb.6.BB_124: + successors: %bb.13(0x40000000), %bb.7(0x40000000) + + INLINEASM &"# LLVM BB: BB_124", 1 /* sideeffect attdialect */ + %34:gr8 = MOV8ri 1 + CMP64mi32 %stack.3, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load (s64) from %ir.5) + %66:gr8 = COPY %34 + JCC_1 %bb.13, 4, implicit $eflags + + bb.7.BB_125: + successors: %bb.8(0x80000000) + + INLINEASM &"# LLVM BB: BB_125", 1 /* sideeffect attdialect */ + %45:gr64 = MOV64rm %stack.9, 1, $noreg, 0, $noreg :: (load (s64) from %ir.11) + %44:gr64 = ADD64ri32 %45, 16, implicit-def $eflags + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %44 :: (store (s64) into %ir.6) + MOV32mi %stack.5, 1, $noreg, 0, $noreg, 5 :: (store (s32) into %ir.7) + %40:gr64 = MOV64rm %stack.4, 1, $noreg, 0, $noreg :: (load (s64) from %ir.6) + %39:gr32 = MOV32rm %stack.5, 1, $noreg, 0, $noreg :: (load (s32) from %ir.7) + %37:gr32 = MOV32ri 65535 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $edi = COPY %39 + $esi = COPY %37 + CALL64pcrel32 @_ZStanSt12memory_orderSt23__memory_order_modifier, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $eax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %38:gr32 = COPY $eax + + bb.8.BB_126: + successors: %bb.10(0x40000000), %bb.17(0x40000000) + + INLINEASM &"# LLVM BB: BB_126", 1 /* sideeffect attdialect */ + MOV32mr %stack.6, 1, $noreg, 0, $noreg, %38 :: (store (s32) into %ir.8) + %5:gr64 = COPY %40 + %46:gr32 = MOV32rm %stack.5, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.7) + %47:gr32 = DEC32r %46, implicit-def dead $eflags + %48:gr32 = SUB32ri %47, 2, implicit-def $eflags + JCC_1 %bb.10, 2, implicit $eflags + JMP_1 %bb.17 + + bb.17.BB_126: + successors: %bb.11(0x40000000), %bb.9(0x40000000) + + %49:gr32 = SUB32ri %46, 5, implicit-def $eflags + JCC_1 %bb.11, 4, implicit $eflags + JMP_1 %bb.9 + + bb.9.BB_127: + successors: %bb.12(0x80000000) + + INLINEASM &"# LLVM BB: BB_127", 1 /* sideeffect attdialect */ + %52:gr64 = MOV64rm %5, 1, $noreg, 0, $noreg :: (load monotonic (s64) from %ir.36) + MOV64mr %stack.7, 1, $noreg, 0, $noreg, %52 :: (store (s64) into %ir.9) + JMP_1 %bb.12 + + bb.10.BB_128: + successors: %bb.12(0x80000000) + + INLINEASM &"# LLVM BB: BB_128", 1 /* sideeffect attdialect */ + %51:gr64 = MOV64rm %5, 1, $noreg, 0, $noreg :: (load acquire (s64) from %ir.36) + MOV64mr %stack.7, 1, $noreg, 0, $noreg, %51 :: (store (s64) into %ir.9) + JMP_1 %bb.12 + + bb.11.BB_129: + successors: %bb.12(0x80000000) + + INLINEASM &"# LLVM BB: BB_129", 1 /* sideeffect attdialect */ + %50:gr64 = MOV64rm %5, 1, $noreg, 0, $noreg :: (load seq_cst (s64) from %ir.36) + MOV64mr %stack.7, 1, $noreg, 0, $noreg, %50 :: (store (s64) into %ir.9) + + bb.12.BB_130: + successors: %bb.13(0x80000000) + + INLINEASM &"# LLVM BB: BB_130", 1 /* sideeffect attdialect */ + CMP64mi32 %stack.7, 1, $noreg, 0, $noreg, 0, implicit-def $eflags :: (load (s64) from %ir.9) + %53:gr8 = SETCCr 5, implicit $eflags + %66:gr8 = COPY %53 + + bb.13.BB_131: + successors: %bb.14(0x40000000), %bb.15(0x40000000) + + %7:gr8 = COPY %66 + INLINEASM &"# LLVM BB: BB_131", 1 /* sideeffect attdialect */ + %56:gr8 = XOR8ri %7, -1, implicit-def $eflags + TEST8ri %56, 1, implicit-def $eflags + JCC_1 %bb.14, 5, implicit $eflags + JMP_1 %bb.15 + + bb.14.BB_132: + successors: + + INLINEASM &"# LLVM BB: BB_132", 1 /* sideeffect attdialect */ + %64:gr64 = MOV64ri @.str.3 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %64 + CALL64pcrel32 @_ZN3c103strIJA68_cEEEDcDpRKT_, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %65:gr64 = COPY $rax + %59:gr64 = MOV64ri @__func__._ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_ + %60:gr64 = MOV64ri @.str.1 + %61:gr32 = MOV32ri 475 + %62:gr64 = MOV64ri @.str.2 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %59 + $rsi = COPY %60 + $edx = COPY %61 + $rcx = COPY %62 + $r8 = COPY %65 + CALL64pcrel32 target-flags(x86-plt) @_ZN3c106detail23torchInternalAssertFailEPKcS2_jS2_S2_, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $edx, implicit $rcx, implicit $r8 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + + bb.15.BB_133: + INLINEASM &"# LLVM BB: BB_133", 1 /* sideeffect attdialect */ + %58:gr64 = MOV64rm %stack.9, 1, $noreg, 0, $noreg :: (load (s64) from %ir.11) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %8 + $rsi = COPY %58 + CALL64pcrel32 @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEEC2EPS1_NS_3raw20DontIncreaseRefcountE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rax = COPY %10 + RET64 implicit $rax + +... +--- +name: _ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEED2Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_134: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_134", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %3:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %3 + CALL64pcrel32 @_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE6reset_Ev, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + RET64 + +... +--- +name: _ZN3c106detail34intrusive_target_default_null_typeINS_20intrusive_ptr_targetEE9singletonEv +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr32, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } +liveins: [] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_135: + INLINEASM &"# LLVM BB: BB_135", 1 /* sideeffect attdialect */ + %0:gr32 = MOV32r0 implicit-def $eflags + %1:gr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32bit + $rax = COPY %1 + RET64 implicit $rax + +... +--- +name: _ZN3c103strIJA68_cEEEDcDpRKT_ +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_136: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_136", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %6:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %6 + CALL64pcrel32 @_ZN3c106detail12_str_wrapperIJPKcEE4callES3_, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %4:gr64 = COPY $rax + $rax = COPY %4 + RET64 implicit $rax + +... +--- +name: _ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEEC2EPS1_NS_3raw20DontIncreaseRefcountE +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } + - { reg: '$rsi', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_137: + liveins: $rdi, $rsi + + %2:gr64 = COPY $rsi + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + %3:gr64 = COPY killed %2 + INLINEASM &"# LLVM BB: BB_137", 1 /* sideeffect attdialect */ + MOV64mr %stack.1, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.3) + MOV64mr %stack.2, 1, $noreg, 0, $noreg, %3 :: (store (s64) into %ir.4) + %7:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.3) + %6:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.4) + MOV64mr %7, 1, $noreg, 0, $noreg, %6 :: (store (s64) into %ir.6) + RET64 + +... +--- +name: _ZN3c106detail12_str_wrapperIJPKcEE4callES3_ +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_138: + liveins: $rdi + + %0:gr64 = COPY $rdi + %1:gr64 = COPY killed %0 + INLINEASM &"# LLVM BB: BB_138", 1 /* sideeffect attdialect */ + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %1 :: (store (s64) into %ir.1) + %3:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + $rax = COPY %3 + RET64 implicit $rax + +... +--- +name: _ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE6reset_Ev +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr32, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr64, preferred-register: '' } + - { id: 18, class: gr32, preferred-register: '' } + - { id: 19, class: gr32, preferred-register: '' } + - { id: 20, class: gr32, preferred-register: '' } + - { id: 21, class: gr32, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr32, preferred-register: '' } + - { id: 29, class: gr32, preferred-register: '' } + - { id: 30, class: gr32, preferred-register: '' } + - { id: 31, class: gr32, preferred-register: '' } + - { id: 32, class: gr64, preferred-register: '' } + - { id: 33, class: gr64, preferred-register: '' } + - { id: 34, class: gr64, preferred-register: '' } + - { id: 35, class: gr8, preferred-register: '' } + - { id: 36, class: gr8, preferred-register: '' } + - { id: 37, class: gr8, preferred-register: '' } + - { id: 38, class: gr8, preferred-register: '' } + - { id: 39, class: gr8, preferred-register: '' } + - { id: 40, class: gr64, preferred-register: '' } + - { id: 41, class: gr64, preferred-register: '' } + - { id: 42, class: gr64, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: gr64, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: gr64, preferred-register: '' } + - { id: 47, class: gr64, preferred-register: '' } + - { id: 48, class: gr32, preferred-register: '' } + - { id: 49, class: gr8, preferred-register: '' } + - { id: 50, class: gr8, preferred-register: '' } + - { id: 51, class: gr8, preferred-register: '' } + - { id: 52, class: gr8, preferred-register: '' } + - { id: 53, class: gr64, preferred-register: '' } + - { id: 54, class: gr64, preferred-register: '' } + - { id: 55, class: gr64, preferred-register: '' } + - { id: 56, class: gr64, preferred-register: '' } + - { id: 57, class: gr64, preferred-register: '' } + - { id: 58, class: gr64, preferred-register: '' } + - { id: 59, class: gr8, preferred-register: '' } + - { id: 60, class: gr64, preferred-register: '' } + - { id: 61, class: gr64, preferred-register: '' } + - { id: 62, class: gr64, preferred-register: '' } + - { id: 63, class: gr64, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%5' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 1, alignment: 1, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_139: + successors: %bb.15(0x40000000), %bb.1(0x40000000) + liveins: $rdi + + %5:gr64 = COPY $rdi + %6:gr64 = COPY killed %5 + INLINEASM &"# LLVM BB: BB_139", 1 /* sideeffect attdialect */ + MOV64mr %stack.4, 1, $noreg, 0, $noreg, %6 :: (store (s64) into %ir.5) + %11:gr64 = MOV64rm %stack.4, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5) + %10:gr64 = MOV64rm %11, 1, $noreg, 0, $noreg :: (load (s64) from %ir.8) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 @_ZN3c106detail34intrusive_target_default_null_typeINS_20intrusive_ptr_targetEE9singletonEv, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %9:gr64 = COPY $rax + CMP64rr %10, %9, implicit-def $eflags + JCC_1 %bb.15, 4, implicit $eflags + + bb.1.BB_140: + successors: %bb.15(0x40000000), %bb.2(0x40000000) + + INLINEASM &"# LLVM BB: BB_140", 1 /* sideeffect attdialect */ + %17:gr64 = MOV64rm %11, 1, $noreg, 0, $noreg :: (load (s64) from %ir.12) + %16:gr64 = ADD64ri32 %17, 8, implicit-def $eflags + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %16 + CALL64pcrel32 @_ZN3c106detail25atomic_refcount_decrementERSt6atomicImE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %14:gr64 = COPY $rax + CMP64ri32 %14, 0, implicit-def $eflags + JCC_1 %bb.15, 5, implicit $eflags + + bb.2.BB_141: + successors: %bb.3(0x80000000) + + INLINEASM &"# LLVM BB: BB_141", 1 /* sideeffect attdialect */ + %27:gr64 = MOV64rm %11, 1, $noreg, 0, $noreg :: (load (s64) from %ir.17) + %26:gr64 = ADD64ri32 %27, 16, implicit-def $eflags + MOV64mr %stack.0, 1, $noreg, 0, $noreg, %26 :: (store (s64) into %ir.1) + MOV32mi %stack.1, 1, $noreg, 0, $noreg, 2 :: (store (s32) into %ir.2) + %22:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.1) + %21:gr32 = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (load (s32) from %ir.2) + %19:gr32 = MOV32ri 65535 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $edi = COPY %21 + $esi = COPY %19 + CALL64pcrel32 @_ZStanSt12memory_orderSt23__memory_order_modifier, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit $esi, implicit-def $eax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %20:gr32 = COPY $eax + + bb.3.BB_142: + successors: %bb.5(0x40000000), %bb.17(0x40000000) + + INLINEASM &"# LLVM BB: BB_142", 1 /* sideeffect attdialect */ + MOV32mr %stack.2, 1, $noreg, 0, $noreg, %20 :: (store (s32) into %ir.3) + %3:gr64 = COPY %22 + %28:gr32 = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from %ir.2) + %29:gr32 = DEC32r %28, implicit-def dead $eflags + %30:gr32 = SUB32ri %29, 2, implicit-def $eflags + JCC_1 %bb.5, 2, implicit $eflags + JMP_1 %bb.17 + + bb.17.BB_142: + successors: %bb.6(0x40000000), %bb.4(0x40000000) + + %31:gr32 = SUB32ri %28, 5, implicit-def $eflags + JCC_1 %bb.6, 4, implicit $eflags + JMP_1 %bb.4 + + bb.4.BB_143: + successors: %bb.7(0x80000000) + + INLINEASM &"# LLVM BB: BB_143", 1 /* sideeffect attdialect */ + %34:gr64 = MOV64rm %3, 1, $noreg, 0, $noreg :: (load monotonic (s64) from %ir.24) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %34 :: (store (s64) into %ir.4) + JMP_1 %bb.7 + + bb.5.BB_144: + successors: %bb.7(0x80000000) + + INLINEASM &"# LLVM BB: BB_144", 1 /* sideeffect attdialect */ + %33:gr64 = MOV64rm %3, 1, $noreg, 0, $noreg :: (load acquire (s64) from %ir.24) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %33 :: (store (s64) into %ir.4) + JMP_1 %bb.7 + + bb.6.BB_145: + successors: %bb.7(0x80000000) + + INLINEASM &"# LLVM BB: BB_145", 1 /* sideeffect attdialect */ + %32:gr64 = MOV64rm %3, 1, $noreg, 0, $noreg :: (load seq_cst (s64) from %ir.24) + MOV64mr %stack.3, 1, $noreg, 0, $noreg, %32 :: (store (s64) into %ir.4) + + bb.7.BB_146: + successors: %bb.10(0x40000000), %bb.8(0x40000000) + + INLINEASM &"# LLVM BB: BB_146", 1 /* sideeffect attdialect */ + CMP64mi32 %stack.3, 1, $noreg, 0, $noreg, 1, implicit-def $eflags :: (load (s64) from %ir.4) + %39:gr8 = SETCCr 4, implicit $eflags + %38:gr8 = AND8ri %39, 1, implicit-def $eflags + MOV8mr %stack.5, 1, $noreg, 0, $noreg, %38 :: (store (s8) into %ir.6) + TEST8mi %stack.5, 1, $noreg, 0, $noreg, 1, implicit-def $eflags :: (load (s8) from %ir.6) + JCC_1 %bb.10, 5, implicit $eflags + + bb.8.BB_147: + successors: %bb.9(0x40000000), %bb.16(0x40000000) + + INLINEASM &"# LLVM BB: BB_147", 1 /* sideeffect attdialect */ + %41:gr64 = MOV64rm %11, 1, $noreg, 0, $noreg :: (load (s64) from %ir.34) + %42:gr64 = MOV64rm %41, 1, $noreg, 0, $noreg :: (load (s64) from %ir.36) + %43:gr64 = MOV64rm killed %42, 1, $noreg, 16, $noreg :: (load (s64) from %ir.38) + EH_LABEL + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %41 + CALL64r killed %43, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + EH_LABEL + JMP_1 %bb.9 + + bb.9.BB_148: + successors: %bb.10(0x80000000) + + INLINEASM &"# LLVM BB: BB_148", 1 /* sideeffect attdialect */ + %58:gr64 = MOV64rm %11, 1, $noreg, 0, $noreg :: (load (s64) from %ir.40) + %57:gr64 = ADD64ri32 %58, 16, implicit-def $eflags + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %57 + CALL64pcrel32 @_ZN3c106detail26atomic_weakcount_decrementERSt6atomicImE, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %55:gr64 = COPY $rax + CMP64ri32 %55, 0, implicit-def $eflags + %52:gr8 = SETCCr 4, implicit $eflags + %51:gr8 = AND8ri %52, 1, implicit-def $eflags + MOV8mr %stack.5, 1, $noreg, 0, $noreg, %51 :: (store (s8) into %ir.6) + + bb.10.BB_149: + successors: %bb.14(0x40000000), %bb.11(0x40000000) + + INLINEASM &"# LLVM BB: BB_149", 1 /* sideeffect attdialect */ + TEST8mi %stack.5, 1, $noreg, 0, $noreg, 1, implicit-def $eflags :: (load (s8) from %ir.6) + JCC_1 %bb.14, 4, implicit $eflags + + bb.11.BB_150: + successors: %bb.13(0x40000000), %bb.12(0x40000000) + + INLINEASM &"# LLVM BB: BB_150", 1 /* sideeffect attdialect */ + %60:gr64 = MOV64rm %11, 1, $noreg, 0, $noreg :: (load (s64) from %ir.48) + CMP64ri32 %60, 0, implicit-def $eflags + JCC_1 %bb.13, 4, implicit $eflags + + bb.12.BB_151: + successors: %bb.13(0x80000000) + + INLINEASM &"# LLVM BB: BB_151", 1 /* sideeffect attdialect */ + %63:gr64 = MOV64rm %60, 1, $noreg, 0, $noreg :: (load (s64) from %ir.51) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %60 + CALL64m %63, 1, $noreg, 8, $noreg, csr_64, implicit $rsp, implicit $ssp, implicit $rdi :: (load (s64) from %ir.53) + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + + bb.13.BB_152: + successors: %bb.14(0x80000000) + + INLINEASM &"# LLVM BB: BB_152", 1 /* sideeffect attdialect */ + + bb.14.BB_153: + successors: %bb.15(0x80000000) + + INLINEASM &"# LLVM BB: BB_153", 1 /* sideeffect attdialect */ + + bb.15.BB_154: + INLINEASM &"# LLVM BB: BB_154", 1 /* sideeffect attdialect */ + RET64 + + bb.16.BB_155 (landing-pad): + liveins: $rax, $rdx + + EH_LABEL + %45:gr64 = COPY killed $rdx + %44:gr64 = COPY killed $rax + %48:gr32 = COPY %45.sub_32bit + %47:gr64 = COPY %44 + INLINEASM &"# LLVM BB: BB_155", 1 /* sideeffect attdialect */ + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %47 + CALL64pcrel32 @__clang_call_terminate, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + +... diff --git a/mir_input/test_mir_input/Activation.mir.liveinfo b/mir_input/test_mir_input/Activation.mir.liveinfo new file mode 100644 index 00000000..16eb5e73 --- /dev/null +++ b/mir_input/test_mir_input/Activation.mir.liveinfo @@ -0,0 +1,1077 @@ +_ZN2at6native19gelu_quantized_cudaERKNS_6TensorEN3c1017basic_string_viewIcEE +AH [224r,256r:4)[1392r,1424r:3)[2128B,2176r:0)[2288B,2336r:1)[2672r,2688r:2) 0@2128B-phi 1@2288B-phi 2@2672r 3@1392r 4@224r +AL [224r,256r:5)[1392r,1424r:4)[1584r,1616r:2)[2128B,2176r:0)[2288B,2336r:1)[2672r,2688r:3) 0@2128B-phi 1@2288B-phi 2@1584r 3@2672r 4@1392r 5@224r +CH [0B,16r:0)[1024r,1040r:2)[1840r,1856r:1) 0@0B-phi 1@1840r 2@1024r +CL [0B,16r:0)[1024r,1040r:2)[1840r,1856r:1) 0@0B-phi 1@1840r 2@1024r +DH [0B,32r:0)[416r,432r:5)[1008r,1040r:4)[1824r,1856r:3)[2128B,2160r:1)[2288B,2320r:2) 0@0B-phi 1@2128B-phi 2@2288B-phi 3@1824r 4@1008r 5@416r +DIL [0B,64r:0)[208r,224r:15)[384r,432r:14)[480r,496r:13)[624r,656r:12)[752r,784r:11)[976r,1040r:10)[1184r,1200r:9)[1376r,1392r:8)[1568r,1584r:7)[1776r,1856r:6)[1984r,2000r:5)[2064r,2080r:4)[2464r,2480r:3)[2576r,2592r:2)[2768r,2784r:1) 0@0B-phi 1@2768r 2@2576r 3@2464r 4@2064r 5@1984r 6@1776r 7@1568r 8@1376r 9@1184r 10@976r 11@752r 12@624r 13@480r 14@384r 15@208r +DIH [0B,64r:0)[208r,224r:15)[384r,432r:14)[480r,496r:13)[624r,656r:12)[752r,784r:11)[976r,1040r:10)[1184r,1200r:9)[1376r,1392r:8)[1568r,1584r:7)[1776r,1856r:6)[1984r,2000r:5)[2064r,2080r:4)[2464r,2480r:3)[2576r,2592r:2)[2768r,2784r:1) 0@0B-phi 1@2768r 2@2576r 3@2464r 4@2064r 5@1984r 6@1776r 7@1568r 8@1376r 9@1184r 10@976r 11@752r 12@624r 13@480r 14@384r 15@208r +DL [0B,32r:0)[416r,432r:5)[1008r,1040r:4)[1824r,1856r:3)[2128B,2160r:1)[2288B,2320r:2) 0@0B-phi 1@2128B-phi 2@2288B-phi 3@1824r 4@1008r 5@416r +HAX [224r,256r:4)[1392r,1424r:3)[2128B,2176r:0)[2288B,2336r:1)[2672r,2688r:2) 0@2128B-phi 1@2288B-phi 2@2672r 3@1392r 4@224r +HCX [0B,16r:0)[1024r,1040r:2)[1840r,1856r:1) 0@0B-phi 1@1840r 2@1024r +HDI [0B,64r:0)[208r,224r:15)[384r,432r:14)[480r,496r:13)[624r,656r:12)[752r,784r:11)[976r,1040r:10)[1184r,1200r:9)[1376r,1392r:8)[1568r,1584r:7)[1776r,1856r:6)[1984r,2000r:5)[2064r,2080r:4)[2464r,2480r:3)[2576r,2592r:2)[2768r,2784r:1) 0@0B-phi 1@2768r 2@2576r 3@2464r 4@2064r 5@1984r 6@1776r 7@1568r 8@1376r 9@1184r 10@976r 11@752r 12@624r 13@480r 14@384r 15@208r +HDX [0B,32r:0)[416r,432r:5)[1008r,1040r:4)[1824r,1856r:3)[2128B,2160r:1)[2288B,2320r:2) 0@0B-phi 1@2128B-phi 2@2288B-phi 3@1824r 4@1008r 5@416r +SIL [0B,48r:0)[400r,432r:1)[640r,656r:5)[768r,784r:4)[992r,1040r:3)[1792r,1856r:2) 0@0B-phi 1@400r 2@1792r 3@992r 4@768r 5@640r +SIH [0B,48r:0)[400r,432r:1)[640r,656r:5)[768r,784r:4)[992r,1040r:3)[1792r,1856r:2) 0@0B-phi 1@400r 2@1792r 3@992r 4@768r 5@640r +HSI [0B,48r:0)[400r,432r:1)[640r,656r:5)[768r,784r:4)[992r,1040r:3)[1792r,1856r:2) 0@0B-phi 1@400r 2@1792r 3@992r 4@768r 5@640r +%0 [1264r,1808r:0) 0@1264r weight:0.000000e+00 +%1 [1456r,1824r:0) 0@1456r weight:0.000000e+00 +%2 [1648r,1744r:0) 0@1648r weight:0.000000e+00 +%3 [64r,480r:0)[544B,1776r:0) 0@64r weight:0.000000e+00 +%4 [48r,160r:0) 0@48r weight:0.000000e+00 +%5 [32r,128r:0) 0@32r weight:0.000000e+00 +%6 [16r,144r:0) 0@16r weight:0.000000e+00 +%7 [80r,2128B:0)[2640B,2672r:0) 0@80r weight:0.000000e+00 +%10 [256r,272r:0) 0@256r weight:0.000000e+00 +%12 [176r,208r:0) 0@176r weight:0.000000e+00 +%14 [576r,640r:0) 0@576r weight:0.000000e+00 +%15 [608r,624r:0) 0@608r weight:0.000000e+00 +%16 [720r,768r:0) 0@720r weight:0.000000e+00 +%17 [736r,752r:0) 0@736r weight:0.000000e+00 +%18 [880r,1008r:0) 0@880r weight:0.000000e+00 +%19 [896r,1024r:0) 0@896r weight:0.000000e+00 +%20 [944r,976r:0) 0@944r weight:0.000000e+00 +%21 [960r,992r:0) 0@960r weight:0.000000e+00 +%22 [2176r,2208r:0) 0@2176r weight:0.000000e+00 +%23 [2160r,2192r:0) 0@2160r weight:0.000000e+00 +%25 [2208r,2240r:0) 0@2208r weight:0.000000e+00 +%26 [2192r,2256r:0) 0@2192r weight:0.000000e+00 +%28 [1136r,1184r:0) 0@1136r weight:0.000000e+00 +%29 [1232r,1264r:0) 0@1232r weight:0.000000e+00 +%30 [1328r,1376r:0) 0@1328r weight:0.000000e+00 +%31 [1424r,1456r:0) 0@1424r weight:0.000000e+00 +%32 [1520r,1568r:0) 0@1520r weight:0.000000e+00 +%33 [1616r,1648r:0) 0@1616r weight:0.000000e+00 +%34 [1744r,1840r:0) 0@1744r weight:0.000000e+00 +%35 [1760r,1792r:0) 0@1760r weight:0.000000e+00 +%36 [2336r,2368r:0) 0@2336r weight:0.000000e+00 +%37 [2320r,2352r:0) 0@2320r weight:0.000000e+00 +%38 [2432r,2464r:0) 0@2432r weight:0.000000e+00 +%40 [2368r,2400r:0) 0@2368r weight:0.000000e+00 +%41 [2352r,2416r:0) 0@2352r weight:0.000000e+00 +%43 [2544r,2576r:0) 0@2544r weight:0.000000e+00 +%45 [2736r,2768r:0) 0@2736r weight:0.000000e+00 +%46 [2032r,2064r:0) 0@2032r weight:0.000000e+00 +%47 [1952r,1984r:0) 0@1952r weight:0.000000e+00 +%49 [336r,400r:0) 0@336r weight:0.000000e+00 +%50 [352r,416r:0) 0@352r weight:0.000000e+00 +RegMasks: 224r 432r 496r 656r 784r 1040r 1200r 1392r 1584r 1856r 2000r 2080r 2480r 2592r 2784r +BB_0: 0B 288B +BB_1: 304B 528B +BB_2: 544B 832B +BB_3: 848B 1088B +BB_4: 1104B 1280B +BB_5: 1296B 1472B +BB_6: 1488B 1664B +BB_7: 1680B 1904B +BB_8: 1920B 2112B +BB_9: 2128B 2272B +BB_10: 2288B 2496B +BB_11: 2512B 2624B +BB_12: 2640B 2688B +BB_13: 2704B 2800B +_ZNK2at10TensorBase5numelEv +DIL [0B,16r:0)[112r,128r:2)[192r,208r:1) 0@0B-phi 1@192r 2@112r +DIH [0B,16r:0)[112r,128r:2)[192r,208r:1) 0@0B-phi 1@192r 2@112r +HDI [0B,16r:0)[112r,128r:2)[192r,208r:1) 0@0B-phi 1@192r 2@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [240r,256r:0) 0@240r weight:0.000000e+00 +%6 [160r,192r:0) 0@160r weight:0.000000e+00 +%8 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r 208r +BB_14: 0B 272B +_ZN2at6TensorC2Ev +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_15: 0B 160B +_ZN2at10dequantizeERKNS_6TensorE +DIL [0B,32r:0)[144r,176r:1) 0@0B-phi 1@144r +DIH [0B,32r:0)[144r,176r:1) 0@0B-phi 1@144r +HDI [0B,32r:0)[144r,176r:1) 0@0B-phi 1@144r +SIL [0B,16r:0)[160r,176r:1) 0@0B-phi 1@160r +SIH [0B,16r:0)[160r,176r:1) 0@0B-phi 1@160r +HSI [0B,16r:0)[160r,176r:1) 0@0B-phi 1@160r +%0 [32r,144r:0) 0@32r weight:0.000000e+00 +%1 [16r,96r:0) 0@16r weight:0.000000e+00 +%2 [48r,208r:0) 0@48r weight:0.000000e+00 +%4 [112r,160r:0) 0@112r weight:0.000000e+00 +RegMasks: 176r +BB_16: 0B 224B +_ZN2at4geluERKNS_6TensorEN3c1017basic_string_viewIcEE +CH [0B,16r:0)[352r,368r:1) 0@0B-phi 1@352r +CL [0B,16r:0)[352r,368r:1) 0@0B-phi 1@352r +DH [0B,32r:0)[336r,368r:1) 0@0B-phi 1@336r +DIL [0B,64r:0)[304r,368r:1) 0@0B-phi 1@304r +DIH [0B,64r:0)[304r,368r:1) 0@0B-phi 1@304r +DL [0B,32r:0)[336r,368r:1) 0@0B-phi 1@336r +HCX [0B,16r:0)[352r,368r:1) 0@0B-phi 1@352r +HDI [0B,64r:0)[304r,368r:1) 0@0B-phi 1@304r +HDX [0B,32r:0)[336r,368r:1) 0@0B-phi 1@336r +SIL [0B,48r:0)[320r,368r:1) 0@0B-phi 1@320r +SIH [0B,48r:0)[320r,368r:1) 0@0B-phi 1@320r +HSI [0B,48r:0)[320r,368r:1) 0@0B-phi 1@320r +%0 [64r,304r:0) 0@64r weight:0.000000e+00 +%1 [48r,160r:0) 0@48r weight:0.000000e+00 +%2 [32r,128r:0) 0@32r weight:0.000000e+00 +%3 [16r,144r:0) 0@16r weight:0.000000e+00 +%4 [80r,400r:0) 0@80r weight:0.000000e+00 +%8 [272r,352r:0) 0@272r weight:0.000000e+00 +%9 [256r,336r:0) 0@256r weight:0.000000e+00 +%10 [192r,208r:0) 0@192r weight:0.000000e+00 +%11 [224r,240r:0) 0@224r weight:0.000000e+00 +%12 [176r,320r:0) 0@176r weight:0.000000e+00 +RegMasks: 368r +BB_17: 0B 416B +_ZN3c1017basic_string_viewIcEC2EPKc +DIL [0B,32r:0)[192r,208r:2)[272r,320r:1) 0@0B-phi 1@272r 2@192r +DIH [0B,32r:0)[192r,208r:2)[272r,320r:1) 0@0B-phi 1@272r 2@192r +HDI [0B,32r:0)[192r,208r:2)[272r,320r:1) 0@0B-phi 1@272r 2@192r +SIL [0B,16r:0)[288r,320r:1) 0@0B-phi 1@288r +SIH [0B,16r:0)[288r,320r:1) 0@0B-phi 1@288r +HSI [0B,16r:0)[288r,320r:1) 0@0B-phi 1@288r +%0 [32r,48r:0) 0@32r weight:0.000000e+00 +%1 [48r,96r:0) 0@48r weight:0.000000e+00 +%2 [16r,64r:0) 0@16r weight:0.000000e+00 +%3 [64r,112r:0) 0@64r weight:0.000000e+00 +%8 [240r,304r:0) 0@240r weight:0.000000e+00 +%9 [160r,192r:0) 0@160r weight:0.000000e+00 +%10 [144r,288r:0) 0@144r weight:0.000000e+00 +%11 [128r,272r:0) 0@128r weight:0.000000e+00 +RegMasks: 208r 320r +BB_18: 0B 352B +_ZN2at19quantize_per_tensorERKNS_6TensorEdlN3c1010ScalarTypeE +CH [0B,16r:0)[368r,384r:1) 0@0B-phi 1@368r +CL [0B,16r:0)[368r,384r:1) 0@0B-phi 1@368r +DH [0B,32r:0)[336r,384r:1) 0@0B-phi 1@336r +DIL [0B,80r:0)[288r,384r:1) 0@0B-phi 1@288r +DIH [0B,80r:0)[288r,384r:1) 0@0B-phi 1@288r +DL [0B,32r:0)[336r,384r:1) 0@0B-phi 1@336r +HCX [0B,16r:0)[368r,384r:1) 0@0B-phi 1@368r +HDI [0B,80r:0)[288r,384r:1) 0@0B-phi 1@288r +HDX [0B,32r:0)[336r,384r:1) 0@0B-phi 1@336r +SIL [0B,64r:0)[304r,384r:1) 0@0B-phi 1@304r +SIH [0B,64r:0)[304r,384r:1) 0@0B-phi 1@304r +HSI [0B,64r:0)[304r,384r:1) 0@0B-phi 1@304r +XMM0 [0B,48r:0)[320r,384r:1) 0@0B-phi 1@320r +%0 [80r,288r:0) 0@80r weight:0.000000e+00 +%1 [64r,160r:0) 0@64r weight:0.000000e+00 +%2 [48r,176r:0) 0@48r weight:0.000000e+00 +%3 [32r,192r:0) 0@32r weight:0.000000e+00 +%4 [16r,96r:0) 0@16r weight:0.000000e+00 +%5 [112r,416r:0) 0@112r weight:0.000000e+00 +%6 [96r,208r:0) 0@96r weight:0.000000e+00 +%11 [352r,368r:0) 0@352r weight:0.000000e+00 +%12 [256r,336r:0) 0@256r weight:0.000000e+00 +%13 [240r,320r:0) 0@240r weight:0.000000e+00 +%14 [224r,304r:0) 0@224r weight:0.000000e+00 +RegMasks: 384r +BB_19: 0B 432B +_ZNK2at6Tensor7q_scaleEv +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [160r,176r:0) 0@160r weight:0.000000e+00 +%5 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_20: 0B 192B +_ZNK2at6Tensor12q_zero_pointEv +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [160r,176r:0) 0@160r weight:0.000000e+00 +%5 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_21: 0B 192B +_ZNK2at10TensorBase11scalar_typeEv +DIL [0B,16r:0)[112r,128r:3)[192r,208r:2)[304r,320r:1) 0@0B-phi 1@304r 2@192r 3@112r +DIH [0B,16r:0)[112r,128r:3)[192r,208r:2)[304r,320r:1) 0@0B-phi 1@304r 2@192r 3@112r +HDI [0B,16r:0)[112r,128r:3)[192r,208r:2)[304r,320r:1) 0@0B-phi 1@304r 2@192r 3@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [368r,384r:0) 0@368r weight:0.000000e+00 +%5 [288r,304r:0) 0@288r weight:0.000000e+00 +%6 [352r,368r:0) 0@352r weight:0.000000e+00 +%9 [240r,256r:0) 0@240r weight:0.000000e+00 +%11 [160r,192r:0) 0@160r weight:0.000000e+00 +%13 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r 208r 320r +BB_22: 0B 400B +_ZN2at6TensorD2Ev +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_23: 0B 160B +_ZN2at6native19relu_quantized_cudaERKNS_6TensorE +AH [160r,192r:6)[2016r,2032r:5)[2048B,2096r:0)[2208B,2256r:1)[2448B,2496r:2)[2608B,2656r:3)[2848B,2896r:4) 0@2048B-phi 1@2208B-phi 2@2448B-phi 3@2608B-phi 4@2848B-phi 5@2016r 6@160r +AL [160r,192r:6)[2016r,2032r:5)[2048B,2096r:0)[2208B,2256r:1)[2448B,2496r:2)[2608B,2656r:3)[2848B,2896r:4) 0@2048B-phi 1@2208B-phi 2@2448B-phi 3@2608B-phi 4@2848B-phi 5@2016r 6@160r +DH [640r,656r:7)[1152r,1184r:6)[1664r,1680r:5)[2048B,2080r:0)[2208B,2240r:1)[2448B,2480r:2)[2608B,2640r:3)[2848B,2880r:4) 0@2048B-phi 1@2208B-phi 2@2448B-phi 3@2608B-phi 4@2848B-phi 5@1664r 6@1152r 7@640r +DIL [0B,32r:0)[144r,160r:19)[272r,304r:18)[400r,432r:17)[608r,656r:16)[784r,800r:15)[896r,928r:14)[1120r,1184r:13)[1312r,1328r:12)[1408r,1424r:11)[1616r,1680r:10)[1808r,1824r:9)[1888r,1904r:8)[1968r,1984r:7)[2384r,2400r:6)[2784r,2800r:5)[3024r,3040r:4)[3136r,3152r:3)[3248r,3264r:2)[3360r,3376r:1) 0@0B-phi 1@3360r 2@3248r 3@3136r 4@3024r 5@2784r 6@2384r 7@1968r 8@1888r 9@1808r 10@1616r 11@1408r 12@1312r 13@1120r 14@896r 15@784r 16@608r 17@400r 18@272r 19@144r +DIH [0B,32r:0)[144r,160r:19)[272r,304r:18)[400r,432r:17)[608r,656r:16)[784r,800r:15)[896r,928r:14)[1120r,1184r:13)[1312r,1328r:12)[1408r,1424r:11)[1616r,1680r:10)[1808r,1824r:9)[1888r,1904r:8)[1968r,1984r:7)[2384r,2400r:6)[2784r,2800r:5)[3024r,3040r:4)[3136r,3152r:3)[3248r,3264r:2)[3360r,3376r:1) 0@0B-phi 1@3360r 2@3248r 3@3136r 4@3024r 5@2784r 6@2384r 7@1968r 8@1888r 9@1808r 10@1616r 11@1408r 12@1312r 13@1120r 14@896r 15@784r 16@608r 17@400r 18@272r 19@144r +DL [640r,656r:7)[1152r,1184r:6)[1664r,1680r:5)[2048B,2080r:0)[2208B,2240r:1)[2448B,2480r:2)[2608B,2640r:3)[2848B,2880r:4) 0@2048B-phi 1@2208B-phi 2@2448B-phi 3@2608B-phi 4@2848B-phi 5@1664r 6@1152r 7@640r +HAX [160r,192r:6)[2016r,2032r:5)[2048B,2096r:0)[2208B,2256r:1)[2448B,2496r:2)[2608B,2656r:3)[2848B,2896r:4) 0@2048B-phi 1@2208B-phi 2@2448B-phi 3@2608B-phi 4@2848B-phi 5@2016r 6@160r +HDI [0B,32r:0)[144r,160r:19)[272r,304r:18)[400r,432r:17)[608r,656r:16)[784r,800r:15)[896r,928r:14)[1120r,1184r:13)[1312r,1328r:12)[1408r,1424r:11)[1616r,1680r:10)[1808r,1824r:9)[1888r,1904r:8)[1968r,1984r:7)[2384r,2400r:6)[2784r,2800r:5)[3024r,3040r:4)[3136r,3152r:3)[3248r,3264r:2)[3360r,3376r:1) 0@0B-phi 1@3360r 2@3248r 3@3136r 4@3024r 5@2784r 6@2384r 7@1968r 8@1888r 9@1808r 10@1616r 11@1408r 12@1312r 13@1120r 14@896r 15@784r 16@608r 17@400r 18@272r 19@144r +HDX [640r,656r:7)[1152r,1184r:6)[1664r,1680r:5)[2048B,2080r:0)[2208B,2240r:1)[2448B,2480r:2)[2608B,2640r:3)[2848B,2880r:4) 0@2048B-phi 1@2208B-phi 2@2448B-phi 3@2608B-phi 4@2848B-phi 5@1664r 6@1152r 7@640r +SIL [0B,16r:0)[288r,304r:6)[416r,432r:5)[624r,656r:4)[912r,928r:3)[1136r,1184r:2)[1632r,1680r:1) 0@0B-phi 1@1632r 2@1136r 3@912r 4@624r 5@416r 6@288r +SIH [0B,16r:0)[288r,304r:6)[416r,432r:5)[624r,656r:4)[912r,928r:3)[1136r,1184r:2)[1632r,1680r:1) 0@0B-phi 1@1632r 2@1136r 3@912r 4@624r 5@416r 6@288r +HSI [0B,16r:0)[288r,304r:6)[416r,432r:5)[624r,656r:4)[912r,928r:3)[1136r,1184r:2)[1632r,1680r:1) 0@0B-phi 1@1632r 2@1136r 3@912r 4@624r 5@416r 6@288r +%0 [1488r,1648r:0) 0@1488r weight:0.000000e+00 +%1 [32r,1616r:0) 0@32r weight:0.000000e+00 +%2 [16r,96r:0) 0@16r weight:0.000000e+00 +%3 [48r,2016r:0) 0@48r weight:0.000000e+00 +%4 [112r,144r:0) 0@112r weight:0.000000e+00 +%5 [192r,208r:0) 0@192r weight:0.000000e+00 +%6 [224r,288r:0) 0@224r weight:0.000000e+00 +%7 [256r,272r:0) 0@256r weight:0.000000e+00 +%8 [336r,416r:0) 0@336r weight:0.000000e+00 +%9 [384r,400r:0) 0@384r weight:0.000000e+00 +%10 [2096r,2128r:0) 0@2096r weight:0.000000e+00 +%11 [2080r,2112r:0) 0@2080r weight:0.000000e+00 +%13 [2128r,2160r:0) 0@2128r weight:0.000000e+00 +%14 [2112r,2176r:0) 0@2112r weight:0.000000e+00 +%16 [560r,608r:0) 0@560r weight:0.000000e+00 +%17 [576r,624r:0) 0@576r weight:0.000000e+00 +%18 [592r,640r:0) 0@592r weight:0.000000e+00 +%19 [2256r,2288r:0) 0@2256r weight:0.000000e+00 +%20 [2240r,2272r:0) 0@2240r weight:0.000000e+00 +%21 [2352r,2384r:0) 0@2352r weight:0.000000e+00 +%23 [2288r,2320r:0) 0@2288r weight:0.000000e+00 +%24 [2272r,2336r:0) 0@2272r weight:0.000000e+00 +%26 [768r,784r:0) 0@768r weight:0.000000e+00 +%27 [832r,912r:0) 0@832r weight:0.000000e+00 +%28 [880r,896r:0) 0@880r weight:0.000000e+00 +%29 [2496r,2528r:0) 0@2496r weight:0.000000e+00 +%30 [2480r,2512r:0) 0@2480r weight:0.000000e+00 +%32 [2528r,2560r:0) 0@2528r weight:0.000000e+00 +%33 [2512r,2576r:0) 0@2512r weight:0.000000e+00 +%35 [1056r,1120r:0) 0@1056r weight:0.000000e+00 +%36 [1072r,1136r:0) 0@1072r weight:0.000000e+00 +%37 [1088r,1152r:0) 0@1088r weight:0.000000e+00 +%38 [1104r,1168r:0) 0@1104r weight:0.000000e+00 +%39 [2656r,2688r:0) 0@2656r weight:0.000000e+00 +%40 [2640r,2672r:0) 0@2640r weight:0.000000e+00 +%41 [2752r,2784r:0) 0@2752r weight:0.000000e+00 +%43 [2688r,2720r:0) 0@2688r weight:0.000000e+00 +%44 [2672r,2736r:0) 0@2672r weight:0.000000e+00 +%46 [1296r,1312r:0) 0@1296r weight:0.000000e+00 +%47 [1360r,1408r:0) 0@1360r weight:0.000000e+00 +%48 [1456r,1488r:0) 0@1456r weight:0.000000e+00 +%49 [1552r,1664r:0) 0@1552r weight:0.000000e+00 +%50 [1600r,1632r:0) 0@1600r weight:0.000000e+00 +%51 [2896r,2928r:0) 0@2896r weight:0.000000e+00 +%52 [2880r,2912r:0) 0@2880r weight:0.000000e+00 +%53 [2992r,3024r:0) 0@2992r weight:0.000000e+00 +%55 [2928r,2960r:0) 0@2928r weight:0.000000e+00 +%56 [2912r,2976r:0) 0@2912r weight:0.000000e+00 +%58 [3104r,3136r:0) 0@3104r weight:0.000000e+00 +%59 [3216r,3248r:0) 0@3216r weight:0.000000e+00 +%61 [3328r,3360r:0) 0@3328r weight:0.000000e+00 +%62 [1936r,1968r:0) 0@1936r weight:0.000000e+00 +%63 [1856r,1888r:0) 0@1856r weight:0.000000e+00 +%64 [1776r,1808r:0) 0@1776r weight:0.000000e+00 +RegMasks: 160r 304r 432r 656r 800r 928r 1184r 1328r 1424r 1680r 1824r 1904r 1984r 2400r 2800r 3040r 3152r 3264r 3376r +BB_24: 0B 480B +BB_25: 496B 704B +BB_26: 720B 976B +BB_27: 992B 1232B +BB_28: 1248B 1504B +BB_29: 1520B 1728B +BB_30: 1744B 2032B +BB_31: 2048B 2192B +BB_32: 2208B 2432B +BB_33: 2448B 2592B +BB_34: 2608B 2832B +BB_35: 2848B 3056B +BB_36: 3072B 3168B +BB_37: 3184B 3280B +BB_38: 3296B 3392B +_ZNK2at6Tensor8int_reprEv +DIL [0B,32r:0)[144r,176r:1) 0@0B-phi 1@144r +DIH [0B,32r:0)[144r,176r:1) 0@0B-phi 1@144r +HDI [0B,32r:0)[144r,176r:1) 0@0B-phi 1@144r +SIL [0B,16r:0)[160r,176r:1) 0@0B-phi 1@160r +SIH [0B,16r:0)[160r,176r:1) 0@0B-phi 1@160r +HSI [0B,16r:0)[160r,176r:1) 0@0B-phi 1@160r +%0 [32r,144r:0) 0@32r weight:0.000000e+00 +%1 [16r,96r:0) 0@16r weight:0.000000e+00 +%2 [48r,208r:0) 0@48r weight:0.000000e+00 +%4 [112r,160r:0) 0@112r weight:0.000000e+00 +RegMasks: 176r +BB_39: 0B 224B +_ZN2atgtERKNS_6TensorERKN3c106ScalarE +DH [0B,16r:0)[208r,224r:1) 0@0B-phi 1@208r +DIL [0B,48r:0)[176r,224r:1) 0@0B-phi 1@176r +DIH [0B,48r:0)[176r,224r:1) 0@0B-phi 1@176r +DL [0B,16r:0)[208r,224r:1) 0@0B-phi 1@208r +HDI [0B,48r:0)[176r,224r:1) 0@0B-phi 1@176r +HDX [0B,16r:0)[208r,224r:1) 0@0B-phi 1@208r +SIL [0B,32r:0)[192r,224r:1) 0@0B-phi 1@192r +SIH [0B,32r:0)[192r,224r:1) 0@0B-phi 1@192r +HSI [0B,32r:0)[192r,224r:1) 0@0B-phi 1@192r +%0 [48r,176r:0) 0@48r weight:0.000000e+00 +%1 [32r,96r:0) 0@32r weight:0.000000e+00 +%2 [16r,112r:0) 0@16r weight:0.000000e+00 +%5 [144r,208r:0) 0@144r weight:0.000000e+00 +%6 [128r,192r:0) 0@128r weight:0.000000e+00 +RegMasks: 224r +BB_40: 0B 256B +_ZN3c106ScalarC2El +DIL [0B,32r:0)[192r,240r:1) 0@0B-phi 1@192r +DIH [0B,32r:0)[192r,240r:1) 0@0B-phi 1@192r +HDI [0B,32r:0)[192r,240r:1) 0@0B-phi 1@192r +SIL [0B,16r:0)[208r,240r:1) 0@0B-phi 1@208r +SIH [0B,16r:0)[208r,240r:1) 0@0B-phi 1@208r +HSI [0B,16r:0)[208r,240r:1) 0@0B-phi 1@208r +%0 [32r,48r:0) 0@32r weight:0.000000e+00 +%1 [48r,96r:0) 0@48r weight:0.000000e+00 +%2 [16r,64r:0) 0@16r weight:0.000000e+00 +%3 [64r,112r:0) 0@64r weight:0.000000e+00 +%6 [160r,224r:0) 0@160r weight:0.000000e+00 +%7 [144r,208r:0) 0@144r weight:0.000000e+00 +%8 [128r,192r:0) 0@128r weight:0.000000e+00 +RegMasks: 240r +BB_41: 0B 272B +_ZN3c106ScalarD2Ev +AH [256B,304r:0) 0@256B-phi +AL [256B,304r:0) 0@256B-phi +DH [256B,288r:0) 0@256B-phi +DIL [0B,16r:0)[128r,144r:2)[384r,400r:1) 0@0B-phi 1@384r 2@128r +DIH [0B,16r:0)[128r,144r:2)[384r,400r:1) 0@0B-phi 1@384r 2@128r +DL [256B,288r:0) 0@256B-phi +HAX [256B,304r:0) 0@256B-phi +HDI [0B,16r:0)[128r,144r:2)[384r,400r:1) 0@0B-phi 1@384r 2@128r +HDX [256B,288r:0) 0@256B-phi +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%2 [80r,128r:0) 0@80r weight:0.000000e+00 +%3 [304r,336r:0) 0@304r weight:0.000000e+00 +%4 [288r,320r:0) 0@288r weight:0.000000e+00 +%6 [336r,384r:0) 0@336r weight:0.000000e+00 +%7 [320r,320d:0) 0@320r weight:0.000000e+00 +RegMasks: 144r 400r +BB_42: 0B 192B +BB_43: 208B 240B +BB_44: 256B 416B +_ZN2at5whereERKNS_6TensorES2_RKN3c106ScalarE +CH [0B,16r:0)[288r,304r:1) 0@0B-phi 1@288r +CL [0B,16r:0)[288r,304r:1) 0@0B-phi 1@288r +DH [0B,32r:0)[272r,304r:1) 0@0B-phi 1@272r +DIL [0B,64r:0)[240r,304r:1) 0@0B-phi 1@240r +DIH [0B,64r:0)[240r,304r:1) 0@0B-phi 1@240r +DL [0B,32r:0)[272r,304r:1) 0@0B-phi 1@272r +HCX [0B,16r:0)[288r,304r:1) 0@0B-phi 1@288r +HDI [0B,64r:0)[240r,304r:1) 0@0B-phi 1@240r +HDX [0B,32r:0)[272r,304r:1) 0@0B-phi 1@272r +SIL [0B,48r:0)[256r,304r:1) 0@0B-phi 1@256r +SIH [0B,48r:0)[256r,304r:1) 0@0B-phi 1@256r +HSI [0B,48r:0)[256r,304r:1) 0@0B-phi 1@256r +%0 [64r,240r:0) 0@64r weight:0.000000e+00 +%1 [48r,128r:0) 0@48r weight:0.000000e+00 +%2 [32r,144r:0) 0@32r weight:0.000000e+00 +%3 [16r,160r:0) 0@16r weight:0.000000e+00 +%4 [80r,336r:0) 0@80r weight:0.000000e+00 +%8 [208r,288r:0) 0@208r weight:0.000000e+00 +%9 [192r,272r:0) 0@192r weight:0.000000e+00 +%10 [176r,256r:0) 0@176r weight:0.000000e+00 +RegMasks: 304r +BB_45: 0B 352B +_ZN2at33_make_per_tensor_quantized_tensorERKNS_6TensorEdl +DH [0B,16r:0)[288r,304r:1) 0@0B-phi 1@288r +DIL [0B,64r:0)[240r,304r:1) 0@0B-phi 1@240r +DIH [0B,64r:0)[240r,304r:1) 0@0B-phi 1@240r +DL [0B,16r:0)[288r,304r:1) 0@0B-phi 1@288r +HDI [0B,64r:0)[240r,304r:1) 0@0B-phi 1@240r +HDX [0B,16r:0)[288r,304r:1) 0@0B-phi 1@288r +SIL [0B,48r:0)[256r,304r:1) 0@0B-phi 1@256r +SIH [0B,48r:0)[256r,304r:1) 0@0B-phi 1@256r +HSI [0B,48r:0)[256r,304r:1) 0@0B-phi 1@256r +XMM0 [0B,32r:0)[272r,304r:1) 0@0B-phi 1@272r +%0 [64r,240r:0) 0@64r weight:0.000000e+00 +%1 [48r,128r:0) 0@48r weight:0.000000e+00 +%2 [32r,144r:0) 0@32r weight:0.000000e+00 +%3 [16r,160r:0) 0@16r weight:0.000000e+00 +%4 [80r,336r:0) 0@80r weight:0.000000e+00 +%8 [208r,288r:0) 0@208r weight:0.000000e+00 +%9 [192r,272r:0) 0@192r weight:0.000000e+00 +%10 [176r,256r:0) 0@176r weight:0.000000e+00 +RegMasks: 304r +BB_46: 0B 352B +_ZNK3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEptEv +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [96r,112r:0) 0@96r weight:0.000000e+00 +%5 [80r,96r:0) 0@80r weight:0.000000e+00 +RegMasks: +BB_47: 0B 128B +_ZNK3c1010TensorImpl5numelEv +DIL [0B,16r:0)[128r,160r:2)[320r,336r:1) 0@0B-phi 1@320r 2@128r +DIH [0B,16r:0)[128r,160r:2)[320r,336r:1) 0@0B-phi 1@320r 2@128r +HDI [0B,16r:0)[128r,160r:2)[320r,336r:1) 0@0B-phi 1@320r 2@128r +%1 [16r,32r:0) 0@16r weight:0.000000e+00 +%2 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [96r,144r:0) 0@96r weight:0.000000e+00 +%5 [192r,208r:0) 0@192r weight:0.000000e+00 +%6 [80r,320r:0)[416B,448r:0) 0@80r weight:0.000000e+00 +%8 [448r,464r:0) 0@448r weight:0.000000e+00 +%11 [368r,384r:0) 0@368r weight:0.000000e+00 +%13 [288r,336r:0) 0@288r weight:0.000000e+00 +%15 [512r,528r:0) 0@512r weight:0.000000e+00 +RegMasks: 160r 336r +BB_48: 0B 240B +BB_49: 256B 400B +BB_50: 416B 464B +BB_51: 480B 544B +_ZNK3c1010TensorImpl14matches_policyENS0_18SizesStridesPolicyE +DIL [0B,32r:0) 0@0B-phi +DIH [0B,32r:0) 0@0B-phi +HDI [0B,32r:0) 0@0B-phi +SIL [0B,16r:0) 0@0B-phi +SIH [0B,16r:0) 0@0B-phi +HSI [0B,16r:0) 0@0B-phi +%0 [32r,80r:0) 0@32r weight:0.000000e+00 +%1 [16r,48r:0) 0@16r weight:0.000000e+00 +%2 [48r,96r:0) 0@48r weight:0.000000e+00 +%4 [256r,272r:0) 0@256r weight:0.000000e+00 +%5 [272r,288r:0) 0@272r weight:0.000000e+00 +%6 [240r,256r:0) 0@240r weight:0.000000e+00 +%10 [208r,224r:0) 0@208r weight:0.000000e+00 +%11 [176r,192r:0) 0@176r weight:0.000000e+00 +%12 [192r,224r:0) 0@192r weight:0.000000e+00 +%13 [112r,128r:0) 0@112r weight:0.000000e+00 +%14 [128r,144r:0) 0@128r weight:0.000000e+00 +%15 [144r,160r:0) 0@144r weight:0.000000e+00 +%16 [160r,176r:0) 0@160r weight:0.000000e+00 +RegMasks: +BB_52: 0B 304B +_ZN2at10TensorBaseC2Ev +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_53: 0B 160B +_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2Ev +DIL [0B,16r:0)[208r,240r:1) 0@0B-phi 1@208r +DIH [0B,16r:0)[208r,240r:1) 0@0B-phi 1@208r +HDI [0B,16r:0)[208r,240r:1) 0@0B-phi 1@208r +%2 [16r,32r:0) 0@16r weight:0.000000e+00 +%3 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [144r,224r:0) 0@144r weight:0.000000e+00 +%5 [80r,208r:0) 0@80r weight:0.000000e+00 +RegMasks: 112r 240r +BB_54: 0B 144B +BB_55: 160B 272B +_ZN3c1019UndefinedTensorImpl9singletonEv +%0 [32r,48r:0) 0@32r weight:0.000000e+00 +RegMasks: +BB_56: 0B 64B +__clang_call_terminate +DIL [0B,16r:0)[80r,96r:1) 0@0B-phi 1@80r +DIH [0B,16r:0)[80r,96r:1) 0@0B-phi 1@80r +HDI [0B,16r:0)[80r,96r:1) 0@0B-phi 1@80r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,80r:0) 0@32r weight:0.000000e+00 +%2 [128r,128d:0) 0@128r weight:0.000000e+00 +RegMasks: 96r 160r +BB_57: 0B 176B +_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEEC2EPS1_NS_3raw20DontIncreaseRefcountE +DIL [0B,32r:0) 0@0B-phi +DIH [0B,32r:0) 0@0B-phi +HDI [0B,32r:0) 0@0B-phi +SIL [0B,16r:0) 0@0B-phi +SIH [0B,16r:0) 0@0B-phi +HSI [0B,16r:0) 0@0B-phi +%0 [32r,48r:0) 0@32r weight:0.000000e+00 +%1 [48r,96r:0) 0@48r weight:0.000000e+00 +%2 [16r,64r:0) 0@16r weight:0.000000e+00 +%3 [64r,112r:0) 0@64r weight:0.000000e+00 +%6 [144r,160r:0) 0@144r weight:0.000000e+00 +%7 [128r,160r:0) 0@128r weight:0.000000e+00 +RegMasks: +BB_58: 0B 176B +_ZN3c1017basic_string_viewIcE7strlen_EPKc +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [80r,96r:0) 0@80r weight:0.000000e+00 +%6 [160r,176r:0) 0@160r weight:0.000000e+00 +%8 [144r,160r:0) 0@144r weight:0.000000e+00 +%12 [368r,384r:0) 0@368r weight:0.000000e+00 +%15 [352r,368r:0) 0@352r weight:0.000000e+00 +%16 [336r,368r:0) 0@336r weight:0.000000e+00 +%19 [256r,272r:0) 0@256r weight:0.000000e+00 +%20 [240r,256r:0) 0@240r weight:0.000000e+00 +RegMasks: +BB_59: 0B 96B +BB_60: 112B 192B +BB_61: 208B 288B +BB_62: 304B 400B +_ZN3c1017basic_string_viewIcEC2EPKcm +DH [0B,16r:0) 0@0B-phi +DIL [0B,48r:0) 0@0B-phi +DIH [0B,48r:0) 0@0B-phi +DL [0B,16r:0) 0@0B-phi +HDI [0B,48r:0) 0@0B-phi +HDX [0B,16r:0) 0@0B-phi +SIL [0B,32r:0) 0@0B-phi +SIH [0B,32r:0) 0@0B-phi +HSI [0B,32r:0) 0@0B-phi +%0 [48r,64r:0) 0@48r weight:0.000000e+00 +%1 [64r,128r:0) 0@64r weight:0.000000e+00 +%2 [32r,80r:0) 0@32r weight:0.000000e+00 +%3 [80r,144r:0) 0@80r weight:0.000000e+00 +%4 [16r,96r:0) 0@16r weight:0.000000e+00 +%5 [96r,160r:0) 0@96r weight:0.000000e+00 +%8 [224r,240r:0) 0@224r weight:0.000000e+00 +%10 [192r,208r:0) 0@192r weight:0.000000e+00 +%11 [176r,240r:0) 0@176r weight:0.000000e+00 +RegMasks: +BB_63: 0B 256B +_ZN3c10L20typeMetaToScalarTypeEN6caffe28TypeMetaE +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [176r,192r:0) 0@176r weight:0.000000e+00 +%4 [80r,112r:0) 0@80r weight:0.000000e+00 +%5 [160r,176r:0) 0@160r weight:0.000000e+00 +RegMasks: 128r +BB_64: 0B 208B +_ZNK3c1010TensorImpl5dtypeEv +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [128r,144r:0) 0@128r weight:0.000000e+00 +%5 [96r,112r:0) 0@96r weight:0.000000e+00 +%6 [80r,96r:0) 0@80r weight:0.000000e+00 +RegMasks: +BB_65: 0B 160B +_ZN6caffe28TypeMeta12toScalarTypeEv +DIL [0B,16r:0)[112r,128r:2)[432r,448r:1) 0@0B-phi 1@432r 2@112r +DIH [0B,16r:0)[112r,128r:2)[432r,448r:1) 0@0B-phi 1@432r 2@112r +HDI [0B,16r:0)[112r,128r:2)[432r,448r:1) 0@0B-phi 1@432r 2@112r +%1 [16r,32r:0) 0@16r weight:0.000000e+00 +%2 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [160r,176r:0) 0@160r weight:0.000000e+00 +%5 [80r,256r:0)[336B,368r:0) 0@80r weight:0.000000e+00 +%7 [416r,432r:0) 0@416r weight:0.000000e+00 +%8 [368r,384r:0) 0@368r weight:0.000000e+00 +%10 [288r,304r:0) 0@288r weight:0.000000e+00 +%12 [272r,288r:0) 0@272r weight:0.000000e+00 +%13 [256r,272r:0) 0@256r weight:0.000000e+00 +RegMasks: 128r 448r +BB_66: 0B 208B +BB_67: 224B 320B +BB_68: 336B 464B +_ZNK6caffe28TypeMeta12isScalarTypeEv +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [144r,160r:0) 0@144r weight:0.000000e+00 +%4 [160r,176r:0) 0@160r weight:0.000000e+00 +%5 [128r,144r:0) 0@128r weight:0.000000e+00 +%8 [96r,112r:0) 0@96r weight:0.000000e+00 +%10 [80r,96r:0) 0@80r weight:0.000000e+00 +RegMasks: +BB_69: 0B 192B +_ZN2at10TensorBaseD2Ev +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_70: 0B 160B +_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEED2Ev +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_71: 0B 160B +_ZN3c1013intrusive_ptrINS_10TensorImplENS_19UndefinedTensorImplEE6reset_Ev +AH [128r,160r:4)[304r,336r:3)[608r,640r:1)[1504r,1536r:2)[2016B,2064r:0) 0@2016B-phi 1@608r 2@1504r 3@304r 4@128r +AL [128r,160r:4)[304r,336r:3)[608r,640r:1)[1504r,1536r:2)[2016B,2064r:0) 0@2016B-phi 1@608r 2@1504r 3@304r 4@128r +DH [2016B,2048r:0) 0@2016B-phi +DIL [0B,16r:0)[288r,304r:6)[576r,608r:1)[1328r,1344r:5)[1488r,1504r:4)[1856r,1872r:3)[2144r,2160r:2) 0@0B-phi 1@576r 2@2144r 3@1856r 4@1488r 5@1328r 6@288r +DIH [0B,16r:0)[288r,304r:6)[576r,608r:1)[1328r,1344r:5)[1488r,1504r:4)[1856r,1872r:3)[2144r,2160r:2) 0@0B-phi 1@576r 2@2144r 3@1856r 4@1488r 5@1328r 6@288r +DL [2016B,2048r:0) 0@2016B-phi +HAX [128r,160r:4)[304r,336r:3)[608r,640r:1)[1504r,1536r:2)[2016B,2064r:0) 0@2016B-phi 1@608r 2@1504r 3@304r 4@128r +HDI [0B,16r:0)[288r,304r:6)[576r,608r:1)[1328r,1344r:5)[1488r,1504r:4)[1856r,1872r:3)[2144r,2160r:2) 0@0B-phi 1@576r 2@2144r 3@1856r 4@1488r 5@1328r 6@288r +HDX [2016B,2048r:0) 0@2016B-phi +%4 [704r,896r:0)[944B,976r:0)[1024B,1056r:0) 0@704r weight:0.000000e+00 +%7 [16r,32r:0) 0@16r weight:0.000000e+00 +%8 [32r,64r:0) 0@32r weight:0.000000e+00 +%11 [160r,176r:0) 0@160r weight:0.000000e+00 +%12 [96r,176r:0) 0@96r weight:0.000000e+00 +%13 [80r,1744r:0) 0@80r weight:0.000000e+00 +%15 [336r,384r:0) 0@336r weight:0.000000e+00 +%17 [256r,288r:0) 0@256r weight:0.000000e+00 +%19 [240r,256r:0) 0@240r weight:0.000000e+00 +%21 [544r,592r:0) 0@544r weight:0.000000e+00 +%22 [640r,688r:0) 0@640r weight:0.000000e+00 +%23 [528r,576r:0) 0@528r weight:0.000000e+00 +%24 [512r,704r:0) 0@512r weight:0.000000e+00 +%28 [464r,480r:0) 0@464r weight:0.000000e+00 +%30 [448r,464r:0) 0@448r weight:0.000000e+00 +%31 [720r,816r:0) 0@720r weight:0.000000e+00 +%32 [736r,752r:0) 0@736r weight:0.000000e+00 +%33 [752r,752d:0) 0@752r weight:0.000000e+00 +%34 [816r,816d:0) 0@816r weight:0.000000e+00 +%35 [1056r,1072r:0) 0@1056r weight:0.000000e+00 +%36 [976r,992r:0) 0@976r weight:0.000000e+00 +%37 [896r,912r:0) 0@896r weight:0.000000e+00 +%41 [1152r,1168r:0) 0@1152r weight:0.000000e+00 +%42 [1136r,1152r:0) 0@1136r weight:0.000000e+00 +%44 [1248r,1328r:0) 0@1248r weight:0.000000e+00 +%45 [1264r,1280r:0) 0@1264r weight:0.000000e+00 +%46 [1280r,1344r:0) 0@1280r weight:0.000000e+00 +%47 [2064r,2096r:0) 0@2064r weight:0.000000e+00 +%48 [2048r,2080r:0) 0@2048r weight:0.000000e+00 +%50 [2096r,2144r:0) 0@2096r weight:0.000000e+00 +%51 [2080r,2080d:0) 0@2080r weight:0.000000e+00 +%53 [1536r,1584r:0) 0@1536r weight:0.000000e+00 +%55 [1456r,1488r:0) 0@1456r weight:0.000000e+00 +%57 [1440r,1456r:0) 0@1440r weight:0.000000e+00 +%60 [1616r,1632r:0) 0@1616r weight:0.000000e+00 +%61 [1600r,1616r:0) 0@1600r weight:0.000000e+00 +%63 [1744r,1856r:0) 0@1744r weight:0.000000e+00 +%66 [1824r,1872r:0) 0@1824r weight:0.000000e+00 +RegMasks: 128r 304r 608r 1344r 1504r 1872r 2160r +BB_72: 0B 192B +BB_73: 208B 336B +BB_74: 352B 400B +BB_75: 416B 640B +BB_76: 656B 784B +BB_76: 800B 848B +BB_77: 864B 928B +BB_78: 944B 1008B +BB_79: 1024B 1072B +BB_80: 1088B 1200B +BB_81: 1216B 1392B +BB_82: 1408B 1536B +BB_83: 1552B 1632B +BB_84: 1648B 1696B +BB_85: 1712B 1776B +BB_86: 1792B 1888B +BB_87: 1904B 1920B +BB_88: 1936B 1952B +BB_89: 1968B 2000B +BB_90: 2016B 2176B +_ZN3c106detail25atomic_refcount_decrementERSt6atomicImE +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [144r,384r:0)[432B,496r:0)[544B,608r:0)[656B,720r:0)[768B,832r:0) 0@144r weight:0.000000e+00 +%1 [16r,32r:0) 0@16r weight:0.000000e+00 +%2 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [224r,288r:0) 0@224r weight:0.000000e+00 +%4 [80r,96r:0) 0@80r weight:0.000000e+00 +%5 [160r,208r:0) 0@160r weight:0.000000e+00 +%6 [176r,192r:0) 0@176r weight:0.000000e+00 +%7 [208r,240r:0) 0@208r weight:0.000000e+00 +%8 [240r,240d:0) 0@240r weight:0.000000e+00 +%9 [288r,304r:0) 0@288r weight:0.000000e+00 +%10 [832r,848r:0) 0@832r weight:0.000000e+00 +%11 [800r,816r:0) 0@800r weight:0.000000e+00 +%12 [816r,832r:0) 0@816r weight:0.000000e+00 +%13 [720r,736r:0) 0@720r weight:0.000000e+00 +%14 [688r,704r:0) 0@688r weight:0.000000e+00 +%15 [704r,720r:0) 0@704r weight:0.000000e+00 +%16 [608r,624r:0) 0@608r weight:0.000000e+00 +%17 [576r,592r:0) 0@576r weight:0.000000e+00 +%18 [592r,608r:0) 0@592r weight:0.000000e+00 +%19 [496r,512r:0) 0@496r weight:0.000000e+00 +%20 [464r,480r:0) 0@464r weight:0.000000e+00 +%21 [480r,496r:0) 0@480r weight:0.000000e+00 +%22 [384r,400r:0) 0@384r weight:0.000000e+00 +%23 [352r,368r:0) 0@352r weight:0.000000e+00 +%24 [368r,384r:0) 0@368r weight:0.000000e+00 +%27 [912r,928r:0) 0@912r weight:0.000000e+00 +%28 [896r,912r:0) 0@896r weight:0.000000e+00 +RegMasks: +BB_91: 0B 256B +BB_91: 272B 304B +BB_92: 320B 416B +BB_93: 432B 528B +BB_94: 544B 640B +BB_95: 656B 752B +BB_96: 768B 848B +BB_97: 864B 944B +_ZN3c106detail26atomic_weakcount_decrementERSt6atomicImE +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [144r,384r:0)[432B,496r:0)[544B,608r:0)[656B,720r:0)[768B,832r:0) 0@144r weight:0.000000e+00 +%1 [16r,32r:0) 0@16r weight:0.000000e+00 +%2 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [224r,288r:0) 0@224r weight:0.000000e+00 +%4 [80r,96r:0) 0@80r weight:0.000000e+00 +%5 [160r,208r:0) 0@160r weight:0.000000e+00 +%6 [176r,192r:0) 0@176r weight:0.000000e+00 +%7 [208r,240r:0) 0@208r weight:0.000000e+00 +%8 [240r,240d:0) 0@240r weight:0.000000e+00 +%9 [288r,304r:0) 0@288r weight:0.000000e+00 +%10 [832r,848r:0) 0@832r weight:0.000000e+00 +%11 [800r,816r:0) 0@800r weight:0.000000e+00 +%12 [816r,832r:0) 0@816r weight:0.000000e+00 +%13 [720r,736r:0) 0@720r weight:0.000000e+00 +%14 [688r,704r:0) 0@688r weight:0.000000e+00 +%15 [704r,720r:0) 0@704r weight:0.000000e+00 +%16 [608r,624r:0) 0@608r weight:0.000000e+00 +%17 [576r,592r:0) 0@576r weight:0.000000e+00 +%18 [592r,608r:0) 0@592r weight:0.000000e+00 +%19 [496r,512r:0) 0@496r weight:0.000000e+00 +%20 [464r,480r:0) 0@464r weight:0.000000e+00 +%21 [480r,496r:0) 0@480r weight:0.000000e+00 +%22 [384r,400r:0) 0@384r weight:0.000000e+00 +%23 [352r,368r:0) 0@352r weight:0.000000e+00 +%24 [368r,384r:0) 0@368r weight:0.000000e+00 +%27 [912r,928r:0) 0@912r weight:0.000000e+00 +%28 [896r,912r:0) 0@896r weight:0.000000e+00 +RegMasks: +BB_98: 0B 256B +BB_98: 272B 304B +BB_99: 320B 416B +BB_100: 432B 528B +BB_101: 544B 640B +BB_102: 656B 752B +BB_103: 768B 848B +BB_104: 864B 944B +_ZStanSt12memory_orderSt23__memory_order_modifier +DIL [0B,32r:0) 0@0B-phi +DIH [0B,32r:0) 0@0B-phi +HDI [0B,32r:0) 0@0B-phi +SIL [0B,16r:0) 0@0B-phi +SIH [0B,16r:0) 0@0B-phi +HSI [0B,16r:0) 0@0B-phi +%0 [32r,48r:0) 0@32r weight:0.000000e+00 +%1 [48r,96r:0) 0@48r weight:0.000000e+00 +%2 [16r,64r:0) 0@16r weight:0.000000e+00 +%3 [64r,112r:0) 0@64r weight:0.000000e+00 +%7 [144r,160r:0) 0@144r weight:0.000000e+00 +%8 [128r,144r:0) 0@128r weight:0.000000e+00 +RegMasks: +BB_105: 0B 176B +_ZNK2at6Tensor2gtERKN3c106ScalarE +DH [0B,16r:0)[224r,240r:1) 0@0B-phi 1@224r +DIL [0B,48r:0)[192r,240r:1) 0@0B-phi 1@192r +DIH [0B,48r:0)[192r,240r:1) 0@0B-phi 1@192r +DL [0B,16r:0)[224r,240r:1) 0@0B-phi 1@224r +HDI [0B,48r:0)[192r,240r:1) 0@0B-phi 1@192r +HDX [0B,16r:0)[224r,240r:1) 0@0B-phi 1@224r +SIL [0B,32r:0)[208r,240r:1) 0@0B-phi 1@208r +SIH [0B,32r:0)[208r,240r:1) 0@0B-phi 1@208r +HSI [0B,32r:0)[208r,240r:1) 0@0B-phi 1@208r +%0 [48r,192r:0) 0@48r weight:0.000000e+00 +%1 [32r,112r:0) 0@32r weight:0.000000e+00 +%2 [16r,128r:0) 0@16r weight:0.000000e+00 +%3 [64r,272r:0) 0@64r weight:0.000000e+00 +%6 [160r,224r:0) 0@160r weight:0.000000e+00 +%7 [144r,208r:0) 0@144r weight:0.000000e+00 +RegMasks: 240r +BB_106: 0B 288B +_ZN3c106ScalarC2IlLPb0EEET_b +DH [0B,16r:0) 0@0B-phi +DIL [0B,48r:0)[224r,240r:2)[304r,320r:1) 0@0B-phi 1@304r 2@224r +DIH [0B,48r:0)[224r,240r:2)[304r,320r:1) 0@0B-phi 1@304r 2@224r +DL [0B,16r:0) 0@0B-phi +HDI [0B,48r:0)[224r,240r:2)[304r,320r:1) 0@0B-phi 1@304r 2@224r +HDX [0B,16r:0) 0@0B-phi +SIL [0B,32r:0) 0@0B-phi +SIH [0B,32r:0) 0@0B-phi +HSI [0B,32r:0) 0@0B-phi +%0 [48r,96r:0) 0@48r weight:0.000000e+00 +%1 [32r,112r:0) 0@32r weight:0.000000e+00 +%2 [16r,64r:0) 0@16r weight:0.000000e+00 +%3 [64r,128r:0) 0@64r weight:0.000000e+00 +%7 [352r,368r:0) 0@352r weight:0.000000e+00 +%8 [272r,304r:0) 0@272r weight:0.000000e+00 +%10 [192r,224r:0) 0@192r weight:0.000000e+00 +%11 [160r,368r:0) 0@160r weight:0.000000e+00 +%13 [128r,144r:0) 0@128r weight:0.000000e+00 +RegMasks: 240r 320r +BB_107: 0B 384B +_ZN3c106Scalar3v_tC2Ev +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [96r,112r:0) 0@96r weight:0.000000e+00 +%4 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: +BB_108: 0B 128B +_ZN3c107convertIllEET_T0_ +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [160r,176r:0) 0@160r weight:0.000000e+00 +%5 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_109: 0B 192B +_ZN3c1027static_cast_with_inter_typeIllE5applyEl +DIL [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r +DIH [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r +HDI [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [208r,224r:0) 0@208r weight:0.000000e+00 +%6 [176r,192r:0) 0@176r weight:0.000000e+00 +%7 [96r,128r:0) 0@96r weight:0.000000e+00 +RegMasks: 144r +BB_110: 0B 240B +_ZN3c1010maybe_realILb0ElE5applyEl +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [80r,96r:0) 0@80r weight:0.000000e+00 +RegMasks: +BB_111: 0B 112B +_ZN3c106Scalar7destroyEv +DIL [0B,16r:0)[368r,384r:1) 0@0B-phi 1@368r +DIH [0B,16r:0)[368r,384r:1) 0@0B-phi 1@368r +HDI [0B,16r:0)[368r,384r:1) 0@0B-phi 1@368r +%1 [16r,32r:0) 0@16r weight:0.000000e+00 +%2 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [96r,112r:0) 0@96r weight:0.000000e+00 +%5 [80r,416r:0) 0@80r weight:0.000000e+00 +%6 [176r,192r:0) 0@176r weight:0.000000e+00 +%8 [256r,272r:0) 0@256r weight:0.000000e+00 +%11 [336r,368r:0) 0@336r weight:0.000000e+00 +RegMasks: 384r +BB_112: 0B 128B +BB_113: 144B 208B +BB_114: 224B 288B +BB_115: 304B 416B +BB_116: 432B 464B +_ZN3c103raw13intrusive_ptr6decrefEPNS_20intrusive_ptr_targetE +DIL [0B,16r:0)[128r,160r:2)[224r,240r:1) 0@0B-phi 1@224r 2@128r +DIH [0B,16r:0)[128r,160r:2)[224r,240r:1) 0@0B-phi 1@224r 2@128r +HDI [0B,16r:0)[128r,160r:2)[224r,240r:1) 0@0B-phi 1@224r 2@128r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%2 [192r,224r:0) 0@192r weight:0.000000e+00 +%3 [96r,128r:0) 0@96r weight:0.000000e+00 +%5 [80r,144r:0) 0@80r weight:0.000000e+00 +RegMasks: 160r 240r +BB_117: 0B 272B +_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE7reclaimEPS1_ +DIL [0B,32r:0)[416r,448r:2)[1184r,1216r:1)[1952r,1968r:5)[2096r,2176r:4)[2272r,2304r:3) 0@0B-phi 1@1184r 2@416r 3@2272r 4@2096r 5@1952r +DIH [0B,32r:0)[416r,448r:2)[1184r,1216r:1)[1952r,1968r:5)[2096r,2176r:4)[2272r,2304r:3) 0@0B-phi 1@1184r 2@416r 3@2272r 4@2096r 5@1952r +HDI [0B,32r:0)[416r,448r:2)[1184r,1216r:1)[1952r,1968r:5)[2096r,2176r:4)[2272r,2304r:3) 0@0B-phi 1@1184r 2@416r 3@2272r 4@2096r 5@1952r +SIL [0B,16r:0)[432r,448r:2)[1200r,1216r:1)[2112r,2176r:4)[2288r,2304r:3) 0@0B-phi 1@1200r 2@432r 3@2288r 4@2112r +SIH [0B,16r:0)[432r,448r:2)[1200r,1216r:1)[2112r,2176r:4)[2288r,2304r:3) 0@0B-phi 1@1200r 2@432r 3@2288r 4@2112r +HSI [0B,16r:0)[432r,448r:2)[1200r,1216r:1)[2112r,2176r:4)[2288r,2304r:3) 0@0B-phi 1@1200r 2@432r 3@2288r 4@2112r +%2 [544r,736r:0)[784B,816r:0)[864B,896r:0) 0@544r weight:0.000000e+00 +%5 [1312r,1504r:0)[1552B,1584r:0)[1632B,1664r:0) 0@1312r weight:0.000000e+00 +%7 [1792r,1824r:0) 0@1792r weight:0.000000e+00 +%8 [32r,1888B:0)[2208B,2272r:0) 0@32r weight:0.000000e+00 +%9 [16r,96r:0) 0@16r weight:0.000000e+00 +%10 [48r,1888B:0)[2208B,2336r:0) 0@48r weight:0.000000e+00 +%11 [192r,224r:0) 0@192r weight:0.000000e+00 +%14 [176r,208r:0) 0@176r weight:0.000000e+00 +%15 [112r,208r:0) 0@112r weight:0.000000e+00 +%18 [384r,432r:0) 0@384r weight:0.000000e+00 +%19 [480r,528r:0) 0@480r weight:0.000000e+00 +%20 [368r,416r:0) 0@368r weight:0.000000e+00 +%21 [352r,544r:0) 0@352r weight:0.000000e+00 +%25 [304r,320r:0) 0@304r weight:0.000000e+00 +%26 [288r,304r:0) 0@288r weight:0.000000e+00 +%27 [560r,656r:0) 0@560r weight:0.000000e+00 +%28 [576r,592r:0) 0@576r weight:0.000000e+00 +%29 [592r,592d:0) 0@592r weight:0.000000e+00 +%30 [656r,656d:0) 0@656r weight:0.000000e+00 +%31 [896r,912r:0) 0@896r weight:0.000000e+00 +%32 [816r,832r:0) 0@816r weight:0.000000e+00 +%33 [736r,752r:0) 0@736r weight:0.000000e+00 +%34 [960r,992r:0) 0@960r weight:0.000000e+00 +%37 [1152r,1200r:0) 0@1152r weight:0.000000e+00 +%38 [1248r,1296r:0) 0@1248r weight:0.000000e+00 +%39 [1136r,1184r:0) 0@1136r weight:0.000000e+00 +%40 [1120r,1312r:0) 0@1120r weight:0.000000e+00 +%44 [1072r,1088r:0) 0@1072r weight:0.000000e+00 +%45 [1056r,1072r:0) 0@1056r weight:0.000000e+00 +%46 [1328r,1424r:0) 0@1328r weight:0.000000e+00 +%47 [1344r,1360r:0) 0@1344r weight:0.000000e+00 +%48 [1360r,1360d:0) 0@1360r weight:0.000000e+00 +%49 [1424r,1424d:0) 0@1424r weight:0.000000e+00 +%50 [1664r,1680r:0) 0@1664r weight:0.000000e+00 +%51 [1584r,1600r:0) 0@1584r weight:0.000000e+00 +%52 [1504r,1520r:0) 0@1504r weight:0.000000e+00 +%53 [1744r,1760r:0) 0@1744r weight:0.000000e+00 +%56 [1824r,1840r:0) 0@1824r weight:0.000000e+00 +%58 [2240r,2288r:0) 0@2240r weight:0.000000e+00 +%59 [2016r,2096r:0) 0@2016r weight:0.000000e+00 +%60 [2032r,2112r:0) 0@2032r weight:0.000000e+00 +%61 [2048r,2128r:0) 0@2048r weight:0.000000e+00 +%62 [2064r,2144r:0) 0@2064r weight:0.000000e+00 +%64 [1920r,1952r:0) 0@1920r weight:0.000000e+00 +%65 [2000r,2160r:0) 0@2000r weight:0.000000e+00 +%66 [224r,256B:2)[992r,1024B:1)[1760r,1776B:0)[1776B,1792r:3) 0@1760r 1@992r 2@224r 3@1776B-phi weight:0.000000e+00 +RegMasks: 144r 448r 1216r 1968r 2176r 2304r +BB_118: 0B 240B +BB_119: 256B 480B +BB_120: 496B 624B +BB_120: 640B 688B +BB_121: 704B 768B +BB_122: 784B 848B +BB_123: 864B 912B +BB_124: 928B 1008B +BB_125: 1024B 1248B +BB_126: 1264B 1392B +BB_126: 1408B 1456B +BB_127: 1472B 1536B +BB_128: 1552B 1616B +BB_129: 1632B 1680B +BB_130: 1696B 1760B +BB_131: 1776B 1872B +BB_132: 1888B 2192B +BB_133: 2208B 2352B +_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEED2Ev +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_134: 0B 160B +_ZN3c106detail34intrusive_target_default_null_typeINS_20intrusive_ptr_targetEE9singletonEv +%0 [32r,48r:0) 0@32r weight:0.000000e+00 +%1 [48r,64r:0) 0@48r weight:0.000000e+00 +RegMasks: +BB_135: 0B 80B +_ZN3c103strIJA68_cEEEDcDpRKT_ +DIL [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +DIH [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +HDI [0B,16r:0)[112r,128r:1) 0@0B-phi 1@112r +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%4 [160r,176r:0) 0@160r weight:0.000000e+00 +%6 [80r,112r:0) 0@80r weight:0.000000e+00 +RegMasks: 128r +BB_136: 0B 192B +_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEEC2EPS1_NS_3raw20DontIncreaseRefcountE +DIL [0B,32r:0) 0@0B-phi +DIH [0B,32r:0) 0@0B-phi +HDI [0B,32r:0) 0@0B-phi +SIL [0B,16r:0) 0@0B-phi +SIH [0B,16r:0) 0@0B-phi +HSI [0B,16r:0) 0@0B-phi +%0 [32r,48r:0) 0@32r weight:0.000000e+00 +%1 [48r,96r:0) 0@48r weight:0.000000e+00 +%2 [16r,64r:0) 0@16r weight:0.000000e+00 +%3 [64r,112r:0) 0@64r weight:0.000000e+00 +%6 [144r,160r:0) 0@144r weight:0.000000e+00 +%7 [128r,160r:0) 0@128r weight:0.000000e+00 +RegMasks: +BB_137: 0B 176B +_ZN3c106detail12_str_wrapperIJPKcEE4callES3_ +DIL [0B,16r:0) 0@0B-phi +DIH [0B,16r:0) 0@0B-phi +HDI [0B,16r:0) 0@0B-phi +%0 [16r,32r:0) 0@16r weight:0.000000e+00 +%1 [32r,64r:0) 0@32r weight:0.000000e+00 +%3 [80r,96r:0) 0@80r weight:0.000000e+00 +RegMasks: +BB_138: 0B 112B +_ZN3c1013intrusive_ptrINS_20intrusive_ptr_targetENS_6detail34intrusive_target_default_null_typeIS1_EEE6reset_Ev +AH [128r,160r:4)[304r,336r:3)[576r,608r:1)[1472r,1504r:2)[1952B,2000r:0) 0@1952B-phi 1@576r 2@1472r 3@304r 4@128r +AL [128r,160r:4)[304r,336r:3)[576r,608r:1)[1472r,1504r:2)[1952B,2000r:0) 0@1952B-phi 1@576r 2@1472r 3@304r 4@128r +DH [1952B,1984r:0) 0@1952B-phi +DIL [0B,16r:0)[288r,304r:6)[544r,576r:1)[1296r,1312r:5)[1456r,1472r:4)[1792r,1808r:3)[2080r,2096r:2) 0@0B-phi 1@544r 2@2080r 3@1792r 4@1456r 5@1296r 6@288r +DIH [0B,16r:0)[288r,304r:6)[544r,576r:1)[1296r,1312r:5)[1456r,1472r:4)[1792r,1808r:3)[2080r,2096r:2) 0@0B-phi 1@544r 2@2080r 3@1792r 4@1456r 5@1296r 6@288r +DL [1952B,1984r:0) 0@1952B-phi +HAX [128r,160r:4)[304r,336r:3)[576r,608r:1)[1472r,1504r:2)[1952B,2000r:0) 0@1952B-phi 1@576r 2@1472r 3@304r 4@128r +HDI [0B,16r:0)[288r,304r:6)[544r,576r:1)[1296r,1312r:5)[1456r,1472r:4)[1792r,1808r:3)[2080r,2096r:2) 0@0B-phi 1@544r 2@2080r 3@1792r 4@1456r 5@1296r 6@288r +HDX [1952B,1984r:0) 0@1952B-phi +%3 [672r,864r:0)[912B,944r:0)[992B,1024r:0) 0@672r weight:0.000000e+00 +%5 [16r,32r:0) 0@16r weight:0.000000e+00 +%6 [32r,64r:0) 0@32r weight:0.000000e+00 +%9 [160r,176r:0) 0@160r weight:0.000000e+00 +%10 [96r,176r:0) 0@96r weight:0.000000e+00 +%11 [80r,1680r:0) 0@80r weight:0.000000e+00 +%14 [336r,352r:0) 0@336r weight:0.000000e+00 +%16 [256r,288r:0) 0@256r weight:0.000000e+00 +%17 [240r,256r:0) 0@240r weight:0.000000e+00 +%19 [512r,560r:0) 0@512r weight:0.000000e+00 +%20 [608r,656r:0) 0@608r weight:0.000000e+00 +%21 [496r,544r:0) 0@496r weight:0.000000e+00 +%22 [480r,672r:0) 0@480r weight:0.000000e+00 +%26 [432r,448r:0) 0@432r weight:0.000000e+00 +%27 [416r,432r:0) 0@416r weight:0.000000e+00 +%28 [688r,784r:0) 0@688r weight:0.000000e+00 +%29 [704r,720r:0) 0@704r weight:0.000000e+00 +%30 [720r,720d:0) 0@720r weight:0.000000e+00 +%31 [784r,784d:0) 0@784r weight:0.000000e+00 +%32 [1024r,1040r:0) 0@1024r weight:0.000000e+00 +%33 [944r,960r:0) 0@944r weight:0.000000e+00 +%34 [864r,880r:0) 0@864r weight:0.000000e+00 +%38 [1120r,1136r:0) 0@1120r weight:0.000000e+00 +%39 [1104r,1120r:0) 0@1104r weight:0.000000e+00 +%41 [1216r,1296r:0) 0@1216r weight:0.000000e+00 +%42 [1232r,1248r:0) 0@1232r weight:0.000000e+00 +%43 [1248r,1312r:0) 0@1248r weight:0.000000e+00 +%44 [2000r,2032r:0) 0@2000r weight:0.000000e+00 +%45 [1984r,2016r:0) 0@1984r weight:0.000000e+00 +%47 [2032r,2080r:0) 0@2032r weight:0.000000e+00 +%48 [2016r,2016d:0) 0@2016r weight:0.000000e+00 +%51 [1552r,1568r:0) 0@1552r weight:0.000000e+00 +%52 [1536r,1552r:0) 0@1536r weight:0.000000e+00 +%55 [1504r,1520r:0) 0@1504r weight:0.000000e+00 +%57 [1424r,1456r:0) 0@1424r weight:0.000000e+00 +%58 [1408r,1424r:0) 0@1408r weight:0.000000e+00 +%60 [1680r,1792r:0) 0@1680r weight:0.000000e+00 +%63 [1760r,1808r:0) 0@1760r weight:0.000000e+00 +RegMasks: 128r 304r 576r 1312r 1472r 1808r 2096r +BB_139: 0B 192B +BB_140: 208B 368B +BB_141: 384B 608B +BB_142: 624B 752B +BB_142: 768B 816B +BB_143: 832B 896B +BB_144: 912B 976B +BB_145: 992B 1040B +BB_146: 1056B 1168B +BB_147: 1184B 1360B +BB_148: 1376B 1568B +BB_149: 1584B 1632B +BB_150: 1648B 1712B +BB_151: 1728B 1824B +BB_152: 1840B 1856B +BB_153: 1872B 1888B +BB_154: 1904B 1936B +BB_155: 1952B 2112B diff --git a/mir_input/test_mir_input/Activation.perf b/mir_input/test_mir_input/Activation.perf new file mode 100644 index 00000000..c7fa8a9d --- /dev/null +++ b/mir_input/test_mir_input/Activation.perf @@ -0,0 +1,81 @@ +BB_3,488b55c0488b4dc8488d7dd0488d75d8,0.980000 +BB_4,488b7de0f20f114598,1.010000 +BB_5,488b7de048894590,0.990000 +BB_6,488b7de088458f,1.010000 +BB_7,488b5590f20f104598488b7da08a458f0fbec8488d75d0,2.000000 +BB_9,4889c189d048894db88945b4,2.000000 +BB_13,488b7db8,0.470000 +BB_25,488d7dd8488d75e0488d55b0,1.500000 +BB_27,488d7d98488d75d8488d55e0488d8d70ffffff,2.010000 +BB_29,f20f108558ffffff488bbd60ffffff488b55e8488d7598,1.510000 +BB_31,4889c189d048894da88945a4,2.000000 +BB_33,4889c189d048894da88945a4,2.000000 +BB_38,488b7da8,0.470000 +BB_42,554889e54883ec1048897df8488b7df8,4.090000 +BB_47,554889e548897df8488b45f8488b005d,3.960000 +BB_49,488b7de8488b07488945f8,1.050000 +BB_50,488b45e8488b80a8000000488945f8,1.040000 +BB_51,488b45f84883c4205d,2.000000 +BB_52,554889e54088f048897df88845f7488b45f80fb780b5000000c1e80a24030fb6c00fb64df739c80f9dc024010fb6c05d,-1.000000 +BB_58,554889e548897df0488975e8488b45f0488b4de84889085d,4.620000 +BB_59,554889e548897df8488b45f8488945f0,2.990000 +BB_60,488b45f00fbe0083f800,0.990000 +BB_61,488b45f04883c001488945f0,5.270000 +BB_62,488b45f0488b4df84829c85d,1.630000 +BB_63,554889e548897df8488975f0488955e8488b45f8488b4df0488908488b4de8488948085d,6.350000 +BB_65,554889e548897df0488b45f0668b80b0000000668945f8668b45f85d,4.470000 +BB_67,488b45e8668b000fbec04883c4205d,2.290000 +BB_69,554889e548897df8488b45f80fb70083f81a0f9cc024010fb6c05d,3.740000 +BB_74,488b45c04883f800,0.480000 +BB_76,488b45b08b4dbc894df0488945a08b45f48945ac83c0ff83e802,2.990000 +BB_77,488b45a0488b00488945e8,1.070000 +BB_78,488b45a0488b00488945e8,1.070000 +BB_79,488b45a0488b00488945e8,1.080000 +BB_80,48837de8010f94c024018845dff645df01,2.170000 +BB_81,488b45c8488b38488b07488b4010,2.030000 +BB_83,488b45984883f8000f94c024018845df,1.980000 +BB_84,f645df01,0.470000 +BB_85,488b45c8488b00488945904883f800,1.070000 +BB_86,488b7d90488b07,1.010000 +BB_91,554889e548897dd0488b45d0488945f848c745f001000000c745ec04000000488b45f8488945c08b45ec488b4df048894de083c0ff89c148894dc883e804,8.020000 +BB_92,488b4dc0488b45e048f7d8f0480fc101488945d8,18.000000 +BB_93,488b4dc0488b45e048f7d8f0480fc101488945d8,17.990000 +BB_94,488b4dc0488b45e048f7d8f0480fc101488945d8,17.969999 +BB_95,488b4dc0488b45e048f7d8f0480fc101488945d8,17.969999 +BB_96,488b4dc0488b45e048f7d8f0480fc101488945d8,17.980000 +BB_97,488b45d84883e8015d,1.000000 +BB_98,554889e548897dd0488b45d0488945f848c745f001000000c745ec04000000488b45f8488945c08b45ec488b4df048894de083c0ff89c148894dc883e804,8.020000 +BB_99,488b4dc0488b45e048f7d8f0480fc101488945d8,17.969999 +BB_100,488b4dc0488b45e048f7d8f0480fc101488945d8,17.969999 +BB_101,488b4dc0488b45e048f7d8f0480fc101488945d8,17.980000 +BB_102,488b4dc0488b45e048f7d8f0480fc101488945d8,17.969999 +BB_103,488b4dc0488b45e048f7d8f0480fc101488945d8,17.990000 +BB_104,488b45d84883e8015d,1.000000 +BB_105,554889e5897dfc8975f88b45fc2345f85d,4.210000 +BB_108,554889e548897df8488b45f80f57c0f20f11005d,4.230000 +BB_111,554889e548897df8488b45f85d,4.200000 +BB_112,554889e54883ec1048897df8488b4df848894df0b8050000003b01,3.010000 +BB_113,488b4df0b8040000003b01,1.010000 +BB_114,488b4df0b8060000003b01,1.010000 +BB_120,488b45888b4d94894df048898578ffffff8b45f489458483c0ff83e802,3.010000 +BB_121,488b8578ffffff488b00488945e8,1.020000 +BB_122,488b8578ffffff488b00488945e8,1.060000 +BB_123,488b8578ffffff488b00488945e8,1.030000 +BB_124,b00148837de8008845b7,0.980000 +BB_126,488b8568ffffff8b8d74ffffff894dd848898558ffffff8b45dc898564ffffff83c0ff83e802,2.990000 +BB_127,488b8558ffffff488b00488945d0,1.070000 +BB_128,488b8558ffffff488b00488945d0,1.040000 +BB_129,488b8558ffffff488b00488945d0,1.070000 +BB_130,48837dd0000f95c08845b7,1.010000 +BB_131,8a45b734ffa801,2.030000 +BB_137,554889e548897df0488975e8488b45f0488b4de84889085d,4.370000 +BB_138,554889e548897df8488b45f85d,4.330000 +BB_142,488b45b88b4dc4894df0488945a88b45f48945b483c0ff83e802,2.990000 +BB_143,488b45a8488b00488945e8,1.070000 +BB_144,488b45a8488b00488945e8,1.080000 +BB_145,488b45a8488b00488945e8,1.080000 +BB_146,48837de8010f94c024018845dff645df01,2.150000 +BB_147,488b45c8488b38488b07488b4010,1.970000 +BB_149,f645df01,0.470000 +BB_150,488b45c8488b00488945a04883f800,1.030000 +BB_151,488b7da0488b07,0.990000 diff --git a/mir_input/test_mir_input/AdaptiveMaxPooling2d.liveinfo b/mir_input/test_mir_input/AdaptiveMaxPooling2d.mir.liveinfo similarity index 99% rename from mir_input/test_mir_input/AdaptiveMaxPooling2d.liveinfo rename to mir_input/test_mir_input/AdaptiveMaxPooling2d.mir.liveinfo index f01a80e3..301dd184 100644 --- a/mir_input/test_mir_input/AdaptiveMaxPooling2d.liveinfo +++ b/mir_input/test_mir_input/AdaptiveMaxPooling2d.mir.liveinfo @@ -321,7 +321,7 @@ HSI [0B,16r:0)[240r,256r:2)[368r,400r:1) 0@0B-phi 1@368r 2@240r RegMasks: 256r 400r BB_26: 0B 464B _ZNK3c1013integer_rangeIiLb0ELb1EE5beginEv -DIL [0B,16r:0) 0@0B-phi +DIL [0B,32r:0) 0@0B-phi DIH [0B,16r:0) 0@0B-phi HDI [0B,16r:0) 0@0B-phi %0 [16r,160r:0) 0@16r weight:0.000000e+00 @@ -329,6 +329,7 @@ HDI [0B,16r:0) 0@0B-phi %3 [128r,144r:0) 0@128r weight:0.000000e+00 %5 [96r,112r:0) 0@96r weight:0.000000e+00 %6 [80r,96r:0) 0@80r weight:0.000000e+00 +%7 [32r,112r:0) 0@80r weight:0.000000e+00 RegMasks: BB_27: 0B 160B _ZNK3c1013integer_rangeIiLb0ELb1EE3endEv diff --git a/mir_input/test_mir_input/aligneval_O2.bc.mir b/mir_input/test_mir_input/aligneval_O2.bc.mir new file mode 100644 index 00000000..8a41e574 --- /dev/null +++ b/mir_input/test_mir_input/aligneval_O2.bc.mir @@ -0,0 +1,5639 @@ +--- | + ; ModuleID = 'aligneval_O2.bc' + source_filename = "spec_benchmarks/spec/specint2006/456.hmmer/src/aligneval.c" + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + target triple = "x86_64-pc-linux-gnu" + + @.str = private unnamed_addr constant [59 x i8] c"spec_benchmarks/spec/specint2006/456.hmmer/src/aligneval.c\00", align 1 + + ; Function Attrs: nounwind uwtable + define dso_local float @ComparePairAlignments(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, ptr nocapture noundef readonly %3) local_unnamed_addr #0 { + BB_0: + %4 = alloca ptr, align 8 + %5 = alloca ptr, align 8 + %6 = alloca ptr, align 8 + %7 = alloca ptr, align 8 + %8 = alloca i32, align 4 + %9 = alloca i32, align 4 + %10 = bitcast ptr %4 to ptr + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %10) #8 + %11 = bitcast ptr %5 to ptr + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %11) #8 + %12 = bitcast ptr %6 to ptr + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %12) #8 + %13 = bitcast ptr %7 to ptr + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %13) #8 + %14 = bitcast ptr %8 to ptr + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %14) #8 + %15 = bitcast ptr %9 to ptr + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %15) #8 + call fastcc void @make_alilist(ptr noundef %2, ptr noundef %3, ptr noundef nonnull %6, ptr noundef nonnull %8) + call fastcc void @make_alilist(ptr noundef %3, ptr noundef %2, ptr noundef nonnull %7, ptr noundef nonnull %9) + call fastcc void @make_alilist(ptr noundef %0, ptr noundef %1, ptr noundef nonnull %4, ptr noundef nonnull %8) + call fastcc void @make_alilist(ptr noundef %1, ptr noundef %0, ptr noundef nonnull %5, ptr noundef nonnull %9) + %16 = load ptr, ptr %4, align 8, !tbaa !5 + %17 = load ptr, ptr %5, align 8, !tbaa !5 + %18 = load ptr, ptr %6, align 8, !tbaa !5 + %19 = load ptr, ptr %7, align 8, !tbaa !5 + %20 = load i32, ptr %8, align 4, !tbaa !9 + %21 = load i32, ptr %9, align 4, !tbaa !9 + %22 = icmp sgt i32 %20, 0 + br i1 %22, label %BB_1, label %BB_6 + + BB_1: ; preds = %BB_0 + %23 = zext i32 %20 to i64 + %24 = and i64 %23, 1 + %25 = icmp eq i32 %20, 1 + br i1 %25, label %BB_4, label %BB_2 + + BB_2: ; preds = %BB_1 + %26 = and i64 %23, 4294967294 + br label %BB_9 + + BB_3: ; preds = %BB_9 + %27 = fadd float %61, 1.000000e+00 + br label %BB_4 + + BB_4: ; preds = %BB_3, %BB_1 + %28 = phi float [ undef, %BB_1 ], [ %61, %BB_3 ] + %29 = phi float [ undef, %BB_1 ], [ %68, %BB_3 ] + %30 = phi i64 [ 0, %BB_1 ], [ %69, %BB_3 ] + %31 = phi float [ 1.000000e+00, %BB_1 ], [ %27, %BB_3 ] + %32 = phi float [ 0.000000e+00, %BB_1 ], [ %68, %BB_3 ] + %33 = icmp eq i64 %24, 0 + br i1 %33, label %BB_6, label %BB_5 + + BB_5: ; preds = %BB_4 + %34 = getelementptr inbounds i32, ptr %18, i64 %30 + %35 = load i32, ptr %34, align 4, !tbaa !9 + %36 = getelementptr inbounds i32, ptr %16, i64 %30 + %37 = load i32, ptr %36, align 4, !tbaa !9 + %38 = icmp eq i32 %35, %37 + %39 = fadd float %32, 1.000000e+00 + %40 = select i1 %38, float %39, float %32 + br label %BB_6 + + BB_6: ; preds = %BB_5, %BB_4, %BB_0 + %41 = phi float [ 0.000000e+00, %BB_0 ], [ %29, %BB_4 ], [ %40, %BB_5 ] + %42 = phi float [ 0.000000e+00, %BB_0 ], [ %28, %BB_4 ], [ %31, %BB_5 ] + %43 = icmp sgt i32 %21, 0 + br i1 %43, label %BB_7, label %BB_13 + + BB_7: ; preds = %BB_6 + %44 = zext i32 %21 to i64 + %45 = and i64 %44, 1 + %46 = icmp eq i32 %21, 1 + br i1 %46, label %BB_11, label %BB_8 + + BB_8: ; preds = %BB_7 + %47 = and i64 %44, 4294967294 + br label %BB_10 + + BB_9: ; preds = %BB_9, %BB_2 + %48 = phi i64 [ 0, %BB_2 ], [ %69, %BB_9 ] + %49 = phi float [ 0.000000e+00, %BB_2 ], [ %61, %BB_9 ] + %50 = phi float [ 0.000000e+00, %BB_2 ], [ %68, %BB_9 ] + %51 = phi i64 [ 0, %BB_2 ], [ %70, %BB_9 ] + %52 = fadd float %49, 1.000000e+00 + %53 = getelementptr inbounds i32, ptr %18, i64 %48 + %54 = load i32, ptr %53, align 4, !tbaa !9 + %55 = getelementptr inbounds i32, ptr %16, i64 %48 + %56 = load i32, ptr %55, align 4, !tbaa !9 + %57 = icmp eq i32 %54, %56 + %58 = fadd float %50, 1.000000e+00 + %59 = select i1 %57, float %58, float %50 + %60 = or i64 %48, 1 + %61 = fadd float %52, 1.000000e+00 + %62 = getelementptr inbounds i32, ptr %18, i64 %60 + %63 = load i32, ptr %62, align 4, !tbaa !9 + %64 = getelementptr inbounds i32, ptr %16, i64 %60 + %65 = load i32, ptr %64, align 4, !tbaa !9 + %66 = icmp eq i32 %63, %65 + %67 = fadd float %59, 1.000000e+00 + %68 = select i1 %66, float %67, float %59 + %69 = add nuw nsw i64 %48, 2 + %70 = add i64 %51, 2 + %71 = icmp eq i64 %70, %26 + br i1 %71, label %BB_3, label %BB_9 + + BB_10: ; preds = %BB_10, %BB_8 + %72 = phi i64 [ 0, %BB_8 ], [ %93, %BB_10 ] + %73 = phi float [ %42, %BB_8 ], [ %85, %BB_10 ] + %74 = phi float [ %41, %BB_8 ], [ %92, %BB_10 ] + %75 = phi i64 [ 0, %BB_8 ], [ %94, %BB_10 ] + %76 = fadd float %73, 1.000000e+00 + %77 = getelementptr inbounds i32, ptr %17, i64 %72 + %78 = load i32, ptr %77, align 4, !tbaa !9 + %79 = getelementptr inbounds i32, ptr %19, i64 %72 + %80 = load i32, ptr %79, align 4, !tbaa !9 + %81 = icmp eq i32 %78, %80 + %82 = fadd float %74, 1.000000e+00 + %83 = select i1 %81, float %82, float %74 + %84 = or i64 %72, 1 + %85 = fadd float %76, 1.000000e+00 + %86 = getelementptr inbounds i32, ptr %17, i64 %84 + %87 = load i32, ptr %86, align 4, !tbaa !9 + %88 = getelementptr inbounds i32, ptr %19, i64 %84 + %89 = load i32, ptr %88, align 4, !tbaa !9 + %90 = icmp eq i32 %87, %89 + %91 = fadd float %83, 1.000000e+00 + %92 = select i1 %90, float %91, float %83 + %93 = add nuw nsw i64 %72, 2 + %94 = add i64 %75, 2 + %95 = icmp eq i64 %94, %47 + br i1 %95, label %BB_11, label %BB_10 + + BB_11: ; preds = %BB_10, %BB_7 + %96 = phi float [ undef, %BB_7 ], [ %85, %BB_10 ] + %97 = phi float [ undef, %BB_7 ], [ %92, %BB_10 ] + %98 = phi i64 [ 0, %BB_7 ], [ %93, %BB_10 ] + %99 = phi float [ %42, %BB_7 ], [ %85, %BB_10 ] + %100 = phi float [ %41, %BB_7 ], [ %92, %BB_10 ] + %101 = icmp eq i64 %45, 0 + br i1 %101, label %BB_13, label %BB_12 + + BB_12: ; preds = %BB_11 + %102 = fadd float %99, 1.000000e+00 + %103 = getelementptr inbounds i32, ptr %17, i64 %98 + %104 = load i32, ptr %103, align 4, !tbaa !9 + %105 = getelementptr inbounds i32, ptr %19, i64 %98 + %106 = load i32, ptr %105, align 4, !tbaa !9 + %107 = icmp eq i32 %104, %106 + %108 = fadd float %100, 1.000000e+00 + %109 = select i1 %107, float %108, float %100 + br label %BB_13 + + BB_13: ; preds = %BB_12, %BB_11, %BB_6 + %110 = phi float [ %41, %BB_6 ], [ %97, %BB_11 ], [ %109, %BB_12 ] + %111 = phi float [ %42, %BB_6 ], [ %96, %BB_11 ], [ %102, %BB_12 ] + %112 = bitcast ptr %19 to ptr + %113 = bitcast ptr %18 to ptr + %114 = bitcast ptr %17 to ptr + %115 = bitcast ptr %16 to ptr + %116 = fdiv float %110, %111 + tail call void @free(ptr noundef %115) #8 + tail call void @free(ptr noundef %114) #8 + tail call void @free(ptr noundef %113) #8 + tail call void @free(ptr noundef %112) #8 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %15) #8 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %14) #8 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %13) #8 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %12) #8 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %11) #8 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %10) #8 + ret float %116 + } + + ; Function Attrs: nounwind uwtable + define internal fastcc void @make_alilist(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, ptr nocapture noundef writeonly %2, ptr nocapture noundef writeonly %3) unnamed_addr #0 { + BB_14: + %4 = tail call i64 @strlen(ptr noundef nonnull dereferenceable(1) %0) #9 + %5 = shl i64 %4, 2 + %6 = tail call ptr @sre_malloc(ptr noundef @.str, i32 noundef 179, i64 noundef %5) #8 + %7 = bitcast ptr %6 to ptr + br label %BB_15 + + BB_15: ; preds = %BB_21, %BB_14 + %8 = phi i64 [ %26, %BB_21 ], [ 0, %BB_14 ] + %9 = phi i32 [ %21, %BB_21 ], [ 0, %BB_14 ] + %10 = phi i32 [ %25, %BB_21 ], [ 0, %BB_14 ] + %11 = getelementptr inbounds i8, ptr %0, i64 %8 + %12 = load i8, ptr %11, align 1, !tbaa !11 + switch i8 %12, label %BB_16 [ + i8 0, label %BB_22 + i8 32, label %BB_19 + i8 46, label %BB_19 + i8 95, label %BB_19 + i8 45, label %BB_19 + i8 126, label %BB_19 + ] + + BB_16: ; preds = %BB_15 + %13 = getelementptr inbounds i8, ptr %1, i64 %8 + %14 = load i8, ptr %13, align 1, !tbaa !11 + switch i8 %14, label %BB_17 [ + i8 32, label %BB_18 + i8 46, label %BB_18 + i8 95, label %BB_18 + i8 45, label %BB_18 + ] + + BB_17: ; preds = %BB_16 + %15 = icmp eq i8 %14, 126 + %16 = select i1 %15, i32 -1, i32 %10 + br label %BB_18 + + BB_18: ; preds = %BB_17, %BB_16, %BB_16, %BB_16, %BB_16 + %17 = phi i32 [ -1, %BB_16 ], [ %16, %BB_17 ], [ -1, %BB_16 ], [ -1, %BB_16 ], [ -1, %BB_16 ] + %18 = sext i32 %9 to i64 + %19 = getelementptr inbounds i32, ptr %7, i64 %18 + store i32 %17, ptr %19, align 4, !tbaa !9 + %20 = add nsw i32 %9, 1 + br label %BB_19 + + BB_19: ; preds = %BB_18, %BB_15, %BB_15, %BB_15, %BB_15, %BB_15 + %21 = phi i32 [ %20, %BB_18 ], [ %9, %BB_15 ], [ %9, %BB_15 ], [ %9, %BB_15 ], [ %9, %BB_15 ], [ %9, %BB_15 ] + %22 = getelementptr inbounds i8, ptr %1, i64 %8 + %23 = load i8, ptr %22, align 1, !tbaa !11 + switch i8 %23, label %BB_20 [ + i8 32, label %BB_21 + i8 46, label %BB_21 + i8 95, label %BB_21 + i8 45, label %BB_21 + i8 126, label %BB_21 + ] + + BB_20: ; preds = %BB_19 + %24 = add nsw i32 %10, 1 + br label %BB_21 + + BB_21: ; preds = %BB_20, %BB_19, %BB_19, %BB_19, %BB_19, %BB_19 + %25 = phi i32 [ %10, %BB_19 ], [ %24, %BB_20 ], [ %10, %BB_19 ], [ %10, %BB_19 ], [ %10, %BB_19 ], [ %10, %BB_19 ] + %26 = add nuw i64 %8, 1 + br label %BB_15 + + BB_22: ; preds = %BB_15 + store i32 %9, ptr %3, align 4, !tbaa !9 + %27 = bitcast ptr %2 to ptr + store ptr %6, ptr %27, align 8, !tbaa !5 + ret void + } + + ; Function Attrs: mustprogress nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) + declare void @free(ptr nocapture noundef) local_unnamed_addr #1 + + ; Function Attrs: nounwind uwtable + define dso_local float @CompareRefPairAlignments(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, ptr nocapture noundef readonly %3, ptr nocapture noundef readonly %4) local_unnamed_addr #0 { + BB_23: + %5 = alloca ptr, align 8 + %6 = alloca ptr, align 8 + %7 = alloca ptr, align 8 + %8 = alloca ptr, align 8 + %9 = alloca i32, align 4 + %10 = alloca i32, align 4 + %11 = bitcast ptr %5 to ptr + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %11) #8 + %12 = bitcast ptr %6 to ptr + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %12) #8 + %13 = bitcast ptr %7 to ptr + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %13) #8 + %14 = bitcast ptr %8 to ptr + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %14) #8 + %15 = bitcast ptr %9 to ptr + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %15) #8 + %16 = bitcast ptr %10 to ptr + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %16) #8 + call fastcc void @make_ref_alilist(ptr noundef %0, ptr noundef %1, ptr noundef %3, ptr noundef %4, ptr noundef nonnull %7, ptr noundef nonnull %9) + call fastcc void @make_ref_alilist(ptr noundef %0, ptr noundef %2, ptr noundef %4, ptr noundef %3, ptr noundef nonnull %8, ptr noundef nonnull %10) + call fastcc void @make_ref_alilist(ptr noundef %0, ptr noundef %1, ptr noundef %1, ptr noundef %2, ptr noundef nonnull %5, ptr noundef nonnull %9) + call fastcc void @make_ref_alilist(ptr noundef %0, ptr noundef %2, ptr noundef %2, ptr noundef %1, ptr noundef nonnull %6, ptr noundef nonnull %10) + %17 = load ptr, ptr %5, align 8, !tbaa !5 + %18 = load ptr, ptr %6, align 8, !tbaa !5 + %19 = load ptr, ptr %7, align 8, !tbaa !5 + %20 = load ptr, ptr %8, align 8, !tbaa !5 + %21 = load i32, ptr %9, align 4, !tbaa !9 + %22 = load i32, ptr %10, align 4, !tbaa !9 + %23 = icmp sgt i32 %21, 0 + br i1 %23, label %BB_24, label %BB_29 + + BB_24: ; preds = %BB_23 + %24 = zext i32 %21 to i64 + %25 = and i64 %24, 1 + %26 = icmp eq i32 %21, 1 + br i1 %26, label %BB_27, label %BB_25 + + BB_25: ; preds = %BB_24 + %27 = and i64 %24, 4294967294 + br label %BB_32 + + BB_26: ; preds = %BB_32 + %28 = fadd float %62, 1.000000e+00 + br label %BB_27 + + BB_27: ; preds = %BB_26, %BB_24 + %29 = phi float [ undef, %BB_24 ], [ %62, %BB_26 ] + %30 = phi float [ undef, %BB_24 ], [ %69, %BB_26 ] + %31 = phi i64 [ 0, %BB_24 ], [ %70, %BB_26 ] + %32 = phi float [ 1.000000e+00, %BB_24 ], [ %28, %BB_26 ] + %33 = phi float [ 0.000000e+00, %BB_24 ], [ %69, %BB_26 ] + %34 = icmp eq i64 %25, 0 + br i1 %34, label %BB_29, label %BB_28 + + BB_28: ; preds = %BB_27 + %35 = getelementptr inbounds i32, ptr %19, i64 %31 + %36 = load i32, ptr %35, align 4, !tbaa !9 + %37 = getelementptr inbounds i32, ptr %17, i64 %31 + %38 = load i32, ptr %37, align 4, !tbaa !9 + %39 = icmp eq i32 %36, %38 + %40 = fadd float %33, 1.000000e+00 + %41 = select i1 %39, float %40, float %33 + br label %BB_29 + + BB_29: ; preds = %BB_28, %BB_27, %BB_23 + %42 = phi float [ 0.000000e+00, %BB_23 ], [ %30, %BB_27 ], [ %41, %BB_28 ] + %43 = phi float [ 0.000000e+00, %BB_23 ], [ %29, %BB_27 ], [ %32, %BB_28 ] + %44 = icmp sgt i32 %22, 0 + br i1 %44, label %BB_30, label %BB_36 + + BB_30: ; preds = %BB_29 + %45 = zext i32 %22 to i64 + %46 = and i64 %45, 1 + %47 = icmp eq i32 %22, 1 + br i1 %47, label %BB_34, label %BB_31 + + BB_31: ; preds = %BB_30 + %48 = and i64 %45, 4294967294 + br label %BB_33 + + BB_32: ; preds = %BB_32, %BB_25 + %49 = phi i64 [ 0, %BB_25 ], [ %70, %BB_32 ] + %50 = phi float [ 0.000000e+00, %BB_25 ], [ %62, %BB_32 ] + %51 = phi float [ 0.000000e+00, %BB_25 ], [ %69, %BB_32 ] + %52 = phi i64 [ 0, %BB_25 ], [ %71, %BB_32 ] + %53 = fadd float %50, 1.000000e+00 + %54 = getelementptr inbounds i32, ptr %19, i64 %49 + %55 = load i32, ptr %54, align 4, !tbaa !9 + %56 = getelementptr inbounds i32, ptr %17, i64 %49 + %57 = load i32, ptr %56, align 4, !tbaa !9 + %58 = icmp eq i32 %55, %57 + %59 = fadd float %51, 1.000000e+00 + %60 = select i1 %58, float %59, float %51 + %61 = or i64 %49, 1 + %62 = fadd float %53, 1.000000e+00 + %63 = getelementptr inbounds i32, ptr %19, i64 %61 + %64 = load i32, ptr %63, align 4, !tbaa !9 + %65 = getelementptr inbounds i32, ptr %17, i64 %61 + %66 = load i32, ptr %65, align 4, !tbaa !9 + %67 = icmp eq i32 %64, %66 + %68 = fadd float %60, 1.000000e+00 + %69 = select i1 %67, float %68, float %60 + %70 = add nuw nsw i64 %49, 2 + %71 = add i64 %52, 2 + %72 = icmp eq i64 %71, %27 + br i1 %72, label %BB_26, label %BB_32 + + BB_33: ; preds = %BB_33, %BB_31 + %73 = phi i64 [ 0, %BB_31 ], [ %94, %BB_33 ] + %74 = phi float [ %43, %BB_31 ], [ %86, %BB_33 ] + %75 = phi float [ %42, %BB_31 ], [ %93, %BB_33 ] + %76 = phi i64 [ 0, %BB_31 ], [ %95, %BB_33 ] + %77 = fadd float %74, 1.000000e+00 + %78 = getelementptr inbounds i32, ptr %18, i64 %73 + %79 = load i32, ptr %78, align 4, !tbaa !9 + %80 = getelementptr inbounds i32, ptr %20, i64 %73 + %81 = load i32, ptr %80, align 4, !tbaa !9 + %82 = icmp eq i32 %79, %81 + %83 = fadd float %75, 1.000000e+00 + %84 = select i1 %82, float %83, float %75 + %85 = or i64 %73, 1 + %86 = fadd float %77, 1.000000e+00 + %87 = getelementptr inbounds i32, ptr %18, i64 %85 + %88 = load i32, ptr %87, align 4, !tbaa !9 + %89 = getelementptr inbounds i32, ptr %20, i64 %85 + %90 = load i32, ptr %89, align 4, !tbaa !9 + %91 = icmp eq i32 %88, %90 + %92 = fadd float %84, 1.000000e+00 + %93 = select i1 %91, float %92, float %84 + %94 = add nuw nsw i64 %73, 2 + %95 = add i64 %76, 2 + %96 = icmp eq i64 %95, %48 + br i1 %96, label %BB_34, label %BB_33 + + BB_34: ; preds = %BB_33, %BB_30 + %97 = phi float [ undef, %BB_30 ], [ %86, %BB_33 ] + %98 = phi float [ undef, %BB_30 ], [ %93, %BB_33 ] + %99 = phi i64 [ 0, %BB_30 ], [ %94, %BB_33 ] + %100 = phi float [ %43, %BB_30 ], [ %86, %BB_33 ] + %101 = phi float [ %42, %BB_30 ], [ %93, %BB_33 ] + %102 = icmp eq i64 %46, 0 + br i1 %102, label %BB_36, label %BB_35 + + BB_35: ; preds = %BB_34 + %103 = fadd float %100, 1.000000e+00 + %104 = getelementptr inbounds i32, ptr %18, i64 %99 + %105 = load i32, ptr %104, align 4, !tbaa !9 + %106 = getelementptr inbounds i32, ptr %20, i64 %99 + %107 = load i32, ptr %106, align 4, !tbaa !9 + %108 = icmp eq i32 %105, %107 + %109 = fadd float %101, 1.000000e+00 + %110 = select i1 %108, float %109, float %101 + br label %BB_36 + + BB_36: ; preds = %BB_35, %BB_34, %BB_29 + %111 = phi float [ %42, %BB_29 ], [ %98, %BB_34 ], [ %110, %BB_35 ] + %112 = phi float [ %43, %BB_29 ], [ %97, %BB_34 ], [ %103, %BB_35 ] + %113 = bitcast ptr %20 to ptr + %114 = bitcast ptr %19 to ptr + %115 = bitcast ptr %18 to ptr + %116 = bitcast ptr %17 to ptr + %117 = fdiv float %111, %112 + tail call void @free(ptr noundef %116) #8 + tail call void @free(ptr noundef %115) #8 + tail call void @free(ptr noundef %114) #8 + tail call void @free(ptr noundef %113) #8 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %16) #8 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %15) #8 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %14) #8 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %13) #8 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %12) #8 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %11) #8 + ret float %117 + } + + ; Function Attrs: nounwind uwtable + define internal fastcc void @make_ref_alilist(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, ptr nocapture noundef readonly %3, ptr nocapture noundef writeonly %4, ptr nocapture noundef writeonly %5) unnamed_addr #0 { + BB_37: + %6 = tail call i64 @strlen(ptr noundef nonnull dereferenceable(1) %2) #9 + %7 = shl i64 %6, 2 + %8 = tail call ptr @sre_malloc(ptr noundef @.str, i32 noundef 236, i64 noundef %7) #8 + %9 = tail call i64 @strlen(ptr noundef nonnull dereferenceable(1) %2) #9 + %10 = shl i64 %9, 2 + %11 = tail call ptr @sre_malloc(ptr noundef @.str, i32 noundef 237, i64 noundef %10) #8 + %12 = bitcast ptr %11 to ptr + br label %BB_38 + + BB_38: ; preds = %BB_41, %BB_37 + %13 = phi i64 [ %26, %BB_41 ], [ 0, %BB_37 ] + %14 = phi i32 [ %25, %BB_41 ], [ 0, %BB_37 ] + %15 = getelementptr inbounds i8, ptr %1, i64 %13 + %16 = load i8, ptr %15, align 1, !tbaa !11 + switch i8 %16, label %BB_40 [ + i8 0, label %BB_39 + i8 32, label %BB_41 + i8 46, label %BB_41 + i8 95, label %BB_41 + i8 45, label %BB_41 + i8 126, label %BB_41 + ] + + BB_39: ; preds = %BB_38 + %17 = bitcast ptr %8 to ptr + br label %BB_42 + + BB_40: ; preds = %BB_38 + %18 = getelementptr inbounds i32, ptr %0, i64 %13 + %19 = load i32, ptr %18, align 4, !tbaa !9 + %20 = icmp ne i32 %19, 0 + %21 = zext i1 %20 to i32 + %22 = sext i32 %14 to i64 + %23 = getelementptr inbounds i32, ptr %12, i64 %22 + store i32 %21, ptr %23, align 4, !tbaa !9 + %24 = add nsw i32 %14, 1 + br label %BB_41 + + BB_41: ; preds = %BB_40, %BB_38, %BB_38, %BB_38, %BB_38, %BB_38 + %25 = phi i32 [ %24, %BB_40 ], [ %14, %BB_38 ], [ %14, %BB_38 ], [ %14, %BB_38 ], [ %14, %BB_38 ], [ %14, %BB_38 ] + %26 = add nuw i64 %13, 1 + br label %BB_38 + + BB_42: ; preds = %BB_51, %BB_39 + %27 = phi i64 [ 0, %BB_39 ], [ %54, %BB_51 ] + %28 = phi i32 [ 0, %BB_39 ], [ %49, %BB_51 ] + %29 = phi i32 [ 0, %BB_39 ], [ %53, %BB_51 ] + %30 = phi i32 [ 0, %BB_39 ], [ %47, %BB_51 ] + %31 = getelementptr inbounds i8, ptr %2, i64 %27 + %32 = load i8, ptr %31, align 1, !tbaa !11 + switch i8 %32, label %BB_43 [ + i8 0, label %BB_52 + i8 32, label %BB_47 + i8 46, label %BB_47 + i8 95, label %BB_47 + i8 45, label %BB_47 + i8 126, label %BB_47 + ] + + BB_43: ; preds = %BB_42 + %33 = sext i32 %28 to i64 + %34 = getelementptr inbounds i32, ptr %12, i64 %33 + %35 = load i32, ptr %34, align 4, !tbaa !9 + %36 = icmp eq i32 %35, 0 + br i1 %36, label %BB_47, label %BB_44 + + BB_44: ; preds = %BB_43 + %37 = getelementptr inbounds i8, ptr %3, i64 %27 + %38 = load i8, ptr %37, align 1, !tbaa !11 + switch i8 %38, label %BB_45 [ + i8 32, label %BB_46 + i8 46, label %BB_46 + i8 95, label %BB_46 + i8 45, label %BB_46 + ] + + BB_45: ; preds = %BB_44 + %39 = icmp eq i8 %38, 126 + %40 = select i1 %39, i32 -1, i32 %29 + br label %BB_46 + + BB_46: ; preds = %BB_45, %BB_44, %BB_44, %BB_44, %BB_44 + %41 = phi i32 [ -1, %BB_44 ], [ %40, %BB_45 ], [ -1, %BB_44 ], [ -1, %BB_44 ], [ -1, %BB_44 ] + %42 = sext i32 %30 to i64 + %43 = getelementptr inbounds i32, ptr %17, i64 %42 + store i32 %41, ptr %43, align 4, !tbaa !9 + %44 = add nsw i32 %30, 1 + %45 = load i8, ptr %31, align 1, !tbaa !11 + br label %BB_47 + + BB_47: ; preds = %BB_46, %BB_43, %BB_42, %BB_42, %BB_42, %BB_42, %BB_42 + %46 = phi i8 [ %32, %BB_42 ], [ %32, %BB_42 ], [ %32, %BB_42 ], [ %32, %BB_42 ], [ %32, %BB_42 ], [ %32, %BB_43 ], [ %45, %BB_46 ] + %47 = phi i32 [ %30, %BB_42 ], [ %30, %BB_42 ], [ %30, %BB_42 ], [ %30, %BB_42 ], [ %30, %BB_42 ], [ %30, %BB_43 ], [ %44, %BB_46 ] + switch i8 %46, label %BB_48 [ + i8 32, label %BB_49 + i8 46, label %BB_49 + i8 95, label %BB_49 + i8 45, label %BB_49 + i8 126, label %BB_49 + ] + + BB_48: ; preds = %BB_47 + %48 = add nsw i32 %28, 1 + br label %BB_49 + + BB_49: ; preds = %BB_48, %BB_47, %BB_47, %BB_47, %BB_47, %BB_47 + %49 = phi i32 [ %28, %BB_47 ], [ %48, %BB_48 ], [ %28, %BB_47 ], [ %28, %BB_47 ], [ %28, %BB_47 ], [ %28, %BB_47 ] + %50 = getelementptr inbounds i8, ptr %3, i64 %27 + %51 = load i8, ptr %50, align 1, !tbaa !11 + switch i8 %51, label %BB_50 [ + i8 32, label %BB_51 + i8 46, label %BB_51 + i8 95, label %BB_51 + i8 45, label %BB_51 + i8 126, label %BB_51 + ] + + BB_50: ; preds = %BB_49 + %52 = add nsw i32 %29, 1 + br label %BB_51 + + BB_51: ; preds = %BB_50, %BB_49, %BB_49, %BB_49, %BB_49, %BB_49 + %53 = phi i32 [ %29, %BB_49 ], [ %52, %BB_50 ], [ %29, %BB_49 ], [ %29, %BB_49 ], [ %29, %BB_49 ], [ %29, %BB_49 ] + %54 = add nuw i64 %27, 1 + br label %BB_42 + + BB_52: ; preds = %BB_42 + tail call void @free(ptr noundef %11) #8 + store i32 %30, ptr %5, align 4, !tbaa !9 + %55 = bitcast ptr %4 to ptr + store ptr %8, ptr %55, align 8, !tbaa !5 + ret void + } + + ; Function Attrs: nounwind uwtable + define dso_local float @CompareMultAlignments(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, i32 noundef %2) local_unnamed_addr #0 { + BB_53: + %3 = icmp sgt i32 %2, 0 + br i1 %3, label %BB_54, label %BB_60 + + BB_54: ; preds = %BB_53 + %4 = zext i32 %2 to i64 + %5 = zext i32 %2 to i64 + br label %BB_56 + + BB_55: ; preds = %BB_59, %BB_56 + %6 = phi float [ %11, %BB_56 ], [ %26, %BB_59 ] + %7 = add nuw nsw i64 %10, 1 + %8 = icmp eq i64 %12, %5 + br i1 %8, label %BB_60, label %BB_56 + + BB_56: ; preds = %BB_55, %BB_54 + %9 = phi i64 [ 0, %BB_54 ], [ %12, %BB_55 ] + %10 = phi i64 [ 1, %BB_54 ], [ %7, %BB_55 ] + %11 = phi float [ 0.000000e+00, %BB_54 ], [ %6, %BB_55 ] + %12 = add nuw nsw i64 %9, 1 + %13 = icmp ult i64 %12, %4 + br i1 %13, label %BB_57, label %BB_55 + + BB_57: ; preds = %BB_56 + %14 = getelementptr inbounds ptr, ptr %0, i64 %9 + %15 = getelementptr inbounds ptr, ptr %1, i64 %9 + br label %BB_58 + + BB_58: ; preds = %BB_59, %BB_57 + %16 = phi i64 [ %10, %BB_57 ], [ %27, %BB_59 ] + %17 = phi float [ %11, %BB_57 ], [ %26, %BB_59 ] + %18 = load ptr, ptr %14, align 8, !tbaa !5 + %19 = getelementptr inbounds ptr, ptr %0, i64 %16 + %20 = load ptr, ptr %19, align 8, !tbaa !5 + %21 = load ptr, ptr %15, align 8, !tbaa !5 + %22 = getelementptr inbounds ptr, ptr %1, i64 %16 + %23 = load ptr, ptr %22, align 8, !tbaa !5 + %24 = tail call float @ComparePairAlignments(ptr noundef %18, ptr noundef %20, ptr noundef %21, ptr noundef %23) + %25 = fcmp olt float %24, 0.000000e+00 + br i1 %25, label %BB_61, label %BB_59 + + BB_59: ; preds = %BB_58 + %26 = fadd float %17, %24 + %27 = add nuw nsw i64 %16, 1 + %28 = icmp eq i64 %27, %5 + br i1 %28, label %BB_55, label %BB_58 + + BB_60: ; preds = %BB_55, %BB_53 + %29 = phi float [ 0.000000e+00, %BB_53 ], [ %6, %BB_55 ] + %30 = fpext float %29 to double + %31 = fmul double %30, 2.000000e+00 + %32 = sitofp i32 %2 to float + %33 = fpext float %32 to double + %34 = fadd double %33, -1.000000e+00 + %35 = fmul double %34, %33 + %36 = fdiv double %31, %35 + %37 = fptrunc double %36 to float + br label %BB_61 + + BB_61: ; preds = %BB_60, %BB_58 + %38 = phi float [ %37, %BB_60 ], [ -1.000000e+00, %BB_58 ] + ret float %38 + } + + ; Function Attrs: nounwind uwtable + define dso_local float @CompareRefMultAlignments(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1, ptr nocapture noundef readonly %2, i32 noundef %3) local_unnamed_addr #0 { + BB_62: + %4 = icmp sgt i32 %3, 0 + br i1 %4, label %BB_63, label %BB_69 + + BB_63: ; preds = %BB_62 + %5 = zext i32 %3 to i64 + %6 = zext i32 %3 to i64 + br label %BB_65 + + BB_64: ; preds = %BB_68, %BB_65 + %7 = phi float [ %12, %BB_65 ], [ %27, %BB_68 ] + %8 = add nuw nsw i64 %11, 1 + %9 = icmp eq i64 %13, %6 + br i1 %9, label %BB_69, label %BB_65 + + BB_65: ; preds = %BB_64, %BB_63 + %10 = phi i64 [ 0, %BB_63 ], [ %13, %BB_64 ] + %11 = phi i64 [ 1, %BB_63 ], [ %8, %BB_64 ] + %12 = phi float [ 0.000000e+00, %BB_63 ], [ %7, %BB_64 ] + %13 = add nuw nsw i64 %10, 1 + %14 = icmp ult i64 %13, %5 + br i1 %14, label %BB_66, label %BB_64 + + BB_66: ; preds = %BB_65 + %15 = getelementptr inbounds ptr, ptr %1, i64 %10 + %16 = getelementptr inbounds ptr, ptr %2, i64 %10 + br label %BB_67 + + BB_67: ; preds = %BB_68, %BB_66 + %17 = phi i64 [ %11, %BB_66 ], [ %28, %BB_68 ] + %18 = phi float [ %12, %BB_66 ], [ %27, %BB_68 ] + %19 = load ptr, ptr %15, align 8, !tbaa !5 + %20 = getelementptr inbounds ptr, ptr %1, i64 %17 + %21 = load ptr, ptr %20, align 8, !tbaa !5 + %22 = load ptr, ptr %16, align 8, !tbaa !5 + %23 = getelementptr inbounds ptr, ptr %2, i64 %17 + %24 = load ptr, ptr %23, align 8, !tbaa !5 + %25 = tail call float @CompareRefPairAlignments(ptr noundef %0, ptr noundef %19, ptr noundef %21, ptr noundef %22, ptr noundef %24) + %26 = fcmp olt float %25, 0.000000e+00 + br i1 %26, label %BB_70, label %BB_68 + + BB_68: ; preds = %BB_67 + %27 = fadd float %18, %25 + %28 = add nuw nsw i64 %17, 1 + %29 = icmp eq i64 %28, %6 + br i1 %29, label %BB_64, label %BB_67 + + BB_69: ; preds = %BB_64, %BB_62 + %30 = phi float [ 0.000000e+00, %BB_62 ], [ %7, %BB_64 ] + %31 = fpext float %30 to double + %32 = fmul double %31, 2.000000e+00 + %33 = sitofp i32 %3 to float + %34 = fpext float %33 to double + %35 = fadd double %34, -1.000000e+00 + %36 = fmul double %35, %34 + %37 = fdiv double %32, %36 + %38 = fptrunc double %37 to float + br label %BB_70 + + BB_70: ; preds = %BB_69, %BB_67 + %39 = phi float [ %38, %BB_69 ], [ -1.000000e+00, %BB_67 ] + ret float %39 + } + + ; Function Attrs: nofree norecurse nosync nounwind memory(read) uwtable + define dso_local float @PairwiseIdentity(ptr nocapture noundef readonly %0, ptr nocapture noundef readonly %1) local_unnamed_addr #2 { + BB_71: + %2 = load i8, ptr %0, align 1, !tbaa !11 + %3 = icmp eq i8 %2, 0 + br i1 %3, label %BB_78, label %BB_72 + + BB_72: ; preds = %BB_77, %BB_71 + %4 = phi i64 [ %20, %BB_77 ], [ 0, %BB_71 ] + %5 = phi i8 [ %22, %BB_77 ], [ %2, %BB_71 ] + %6 = phi i32 [ %19, %BB_77 ], [ 0, %BB_71 ] + %7 = phi i32 [ %17, %BB_77 ], [ 0, %BB_71 ] + %8 = phi i32 [ %16, %BB_77 ], [ 0, %BB_71 ] + %9 = getelementptr inbounds i8, ptr %1, i64 %4 + %10 = load i8, ptr %9, align 1, !tbaa !11 + %11 = icmp eq i8 %10, 0 + br i1 %11, label %BB_78, label %BB_73 + + BB_73: ; preds = %BB_72 + switch i8 %5, label %BB_74 [ + i8 32, label %BB_75 + i8 46, label %BB_75 + i8 95, label %BB_75 + i8 45, label %BB_75 + i8 126, label %BB_75 + ] + + BB_74: ; preds = %BB_73 + %12 = add nsw i32 %7, 1 + %13 = icmp eq i8 %5, %10 + %14 = zext i1 %13 to i32 + %15 = add nsw i32 %8, %14 + br label %BB_75 + + BB_75: ; preds = %BB_74, %BB_73, %BB_73, %BB_73, %BB_73, %BB_73 + %16 = phi i32 [ %8, %BB_73 ], [ %8, %BB_73 ], [ %8, %BB_73 ], [ %8, %BB_73 ], [ %8, %BB_73 ], [ %15, %BB_74 ] + %17 = phi i32 [ %7, %BB_73 ], [ %7, %BB_73 ], [ %7, %BB_73 ], [ %7, %BB_73 ], [ %7, %BB_73 ], [ %12, %BB_74 ] + switch i8 %10, label %BB_76 [ + i8 32, label %BB_77 + i8 46, label %BB_77 + i8 95, label %BB_77 + i8 45, label %BB_77 + i8 126, label %BB_77 + ] + + BB_76: ; preds = %BB_75 + %18 = add nsw i32 %6, 1 + br label %BB_77 + + BB_77: ; preds = %BB_76, %BB_75, %BB_75, %BB_75, %BB_75, %BB_75 + %19 = phi i32 [ %6, %BB_75 ], [ %18, %BB_76 ], [ %6, %BB_75 ], [ %6, %BB_75 ], [ %6, %BB_75 ], [ %6, %BB_75 ] + %20 = add nuw i64 %4, 1 + %21 = getelementptr inbounds i8, ptr %0, i64 %20 + %22 = load i8, ptr %21, align 1, !tbaa !11 + %23 = icmp eq i8 %22, 0 + br i1 %23, label %BB_78, label %BB_72 + + BB_78: ; preds = %BB_77, %BB_72, %BB_71 + %24 = phi i32 [ 0, %BB_71 ], [ %16, %BB_77 ], [ %8, %BB_72 ] + %25 = phi i32 [ 0, %BB_71 ], [ %17, %BB_77 ], [ %7, %BB_72 ] + %26 = phi i32 [ 0, %BB_71 ], [ %19, %BB_77 ], [ %6, %BB_72 ] + %27 = icmp slt i32 %26, %25 + %28 = select i1 %27, i32 %26, i32 %25 + %29 = icmp eq i32 %28, 0 + br i1 %29, label %BB_80, label %BB_79 + + BB_79: ; preds = %BB_78 + %30 = sitofp i32 %24 to float + %31 = sitofp i32 %28 to float + %32 = fdiv float %30, %31 + br label %BB_80 + + BB_80: ; preds = %BB_79, %BB_78 + %33 = phi float [ %32, %BB_79 ], [ 0.000000e+00, %BB_78 ] + ret float %33 + } + + ; Function Attrs: nounwind uwtable + define dso_local float @AlignmentIdentityBySampling(ptr nocapture noundef readonly %0, i32 noundef %1, i32 noundef %2, i32 noundef %3) local_unnamed_addr #0 { + BB_81: + %4 = icmp slt i32 %2, 2 + br i1 %4, label %BB_97, label %BB_82 + + BB_82: ; preds = %BB_81 + %5 = icmp sgt i32 %3, 0 + br i1 %5, label %BB_83, label %BB_96 + + BB_83: ; preds = %BB_82 + %6 = sitofp i32 %2 to double + br label %BB_84 + + BB_84: ; preds = %BB_95, %BB_83 + %7 = phi float [ 0.000000e+00, %BB_83 ], [ %54, %BB_95 ] + %8 = phi i32 [ 0, %BB_83 ], [ %55, %BB_95 ] + %9 = tail call double @sre_random() #8 + %10 = fmul double %9, %6 + %11 = fptosi double %10 to i32 + br label %BB_85 + + BB_85: ; preds = %BB_85, %BB_84 + %12 = tail call double @sre_random() #8 + %13 = fmul double %12, %6 + %14 = fptosi double %13 to i32 + %15 = icmp eq i32 %14, %11 + br i1 %15, label %BB_85, label %BB_86 + + BB_86: ; preds = %BB_85 + %16 = sext i32 %11 to i64 + %17 = getelementptr inbounds ptr, ptr %0, i64 %16 + %18 = load ptr, ptr %17, align 8, !tbaa !5 + %19 = sext i32 %14 to i64 + %20 = getelementptr inbounds ptr, ptr %0, i64 %19 + %21 = load ptr, ptr %20, align 8, !tbaa !5 + %22 = load i8, ptr %18, align 1, !tbaa !11 + %23 = icmp eq i8 %22, 0 + br i1 %23, label %BB_93, label %BB_87 + + BB_87: ; preds = %BB_92, %BB_86 + %24 = phi i64 [ %40, %BB_92 ], [ 0, %BB_86 ] + %25 = phi i8 [ %42, %BB_92 ], [ %22, %BB_86 ] + %26 = phi i32 [ %39, %BB_92 ], [ 0, %BB_86 ] + %27 = phi i32 [ %37, %BB_92 ], [ 0, %BB_86 ] + %28 = phi i32 [ %36, %BB_92 ], [ 0, %BB_86 ] + %29 = getelementptr inbounds i8, ptr %21, i64 %24 + %30 = load i8, ptr %29, align 1, !tbaa !11 + %31 = icmp eq i8 %30, 0 + br i1 %31, label %BB_93, label %BB_88 + + BB_88: ; preds = %BB_87 + switch i8 %25, label %BB_89 [ + i8 32, label %BB_90 + i8 46, label %BB_90 + i8 95, label %BB_90 + i8 45, label %BB_90 + i8 126, label %BB_90 + ] + + BB_89: ; preds = %BB_88 + %32 = add nsw i32 %27, 1 + %33 = icmp eq i8 %25, %30 + %34 = zext i1 %33 to i32 + %35 = add nsw i32 %28, %34 + br label %BB_90 + + BB_90: ; preds = %BB_89, %BB_88, %BB_88, %BB_88, %BB_88, %BB_88 + %36 = phi i32 [ %28, %BB_88 ], [ %28, %BB_88 ], [ %28, %BB_88 ], [ %28, %BB_88 ], [ %28, %BB_88 ], [ %35, %BB_89 ] + %37 = phi i32 [ %27, %BB_88 ], [ %27, %BB_88 ], [ %27, %BB_88 ], [ %27, %BB_88 ], [ %27, %BB_88 ], [ %32, %BB_89 ] + switch i8 %30, label %BB_91 [ + i8 32, label %BB_92 + i8 46, label %BB_92 + i8 95, label %BB_92 + i8 45, label %BB_92 + i8 126, label %BB_92 + ] + + BB_91: ; preds = %BB_90 + %38 = add nsw i32 %26, 1 + br label %BB_92 + + BB_92: ; preds = %BB_91, %BB_90, %BB_90, %BB_90, %BB_90, %BB_90 + %39 = phi i32 [ %26, %BB_90 ], [ %38, %BB_91 ], [ %26, %BB_90 ], [ %26, %BB_90 ], [ %26, %BB_90 ], [ %26, %BB_90 ] + %40 = add nuw i64 %24, 1 + %41 = getelementptr inbounds i8, ptr %18, i64 %40 + %42 = load i8, ptr %41, align 1, !tbaa !11 + %43 = icmp eq i8 %42, 0 + br i1 %43, label %BB_93, label %BB_87 + + BB_93: ; preds = %BB_92, %BB_87, %BB_86 + %44 = phi i32 [ 0, %BB_86 ], [ %28, %BB_87 ], [ %36, %BB_92 ] + %45 = phi i32 [ 0, %BB_86 ], [ %27, %BB_87 ], [ %37, %BB_92 ] + %46 = phi i32 [ 0, %BB_86 ], [ %26, %BB_87 ], [ %39, %BB_92 ] + %47 = icmp slt i32 %46, %45 + %48 = select i1 %47, i32 %46, i32 %45 + %49 = icmp eq i32 %48, 0 + br i1 %49, label %BB_95, label %BB_94 + + BB_94: ; preds = %BB_93 + %50 = sitofp i32 %44 to float + %51 = sitofp i32 %48 to float + %52 = fdiv float %50, %51 + br label %BB_95 + + BB_95: ; preds = %BB_94, %BB_93 + %53 = phi float [ %52, %BB_94 ], [ 0.000000e+00, %BB_93 ] + %54 = fadd float %7, %53 + %55 = add nuw nsw i32 %8, 1 + %56 = icmp eq i32 %55, %3 + br i1 %56, label %BB_96, label %BB_84 + + BB_96: ; preds = %BB_95, %BB_82 + %57 = phi float [ 0.000000e+00, %BB_82 ], [ %54, %BB_95 ] + %58 = sitofp i32 %3 to float + %59 = fdiv float %57, %58 + br label %BB_97 + + BB_97: ; preds = %BB_96, %BB_81 + %60 = phi float [ %59, %BB_96 ], [ 1.000000e+00, %BB_81 ] + ret float %60 + } + + declare double @sre_random() local_unnamed_addr #3 + + ; Function Attrs: nounwind uwtable + define dso_local ptr @MajorityRuleConsensus(ptr nocapture noundef readonly %0, i32 noundef %1, i32 noundef %2) local_unnamed_addr #0 { + BB_98: + %3 = alloca [27 x i32], align 16 + %4 = bitcast ptr %3 to ptr + call void @llvm.lifetime.start.p0(i64 108, ptr nonnull %4) #8 + %5 = add nsw i32 %2, 1 + %6 = sext i32 %5 to i64 + %7 = tail call ptr @sre_malloc(ptr noundef @.str, i32 noundef 485, i64 noundef %6) #8 + %8 = icmp sgt i32 %2, 0 + br i1 %8, label %BB_99, label %BB_110 + + BB_99: ; preds = %BB_98 + %9 = icmp sgt i32 %1, 0 + %10 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 26 + %11 = sitofp i32 %1 to float + %12 = zext i32 %2 to i64 + %13 = zext i32 %1 to i64 + %14 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 0 + %15 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 1 + %16 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 2 + %17 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 3 + %18 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 4 + %19 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 5 + %20 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 6 + %21 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 7 + %22 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 8 + %23 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 9 + %24 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 10 + %25 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 11 + %26 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 12 + %27 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 13 + %28 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 14 + %29 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 15 + %30 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 16 + %31 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 17 + %32 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 18 + %33 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 19 + %34 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 20 + %35 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 21 + %36 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 22 + %37 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 23 + %38 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 24 + %39 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 25 + br label %BB_100 + + BB_100: ; preds = %BB_109, %BB_99 + %40 = phi i64 [ 0, %BB_99 ], [ %179, %BB_109 ] + %41 = phi i32 [ 0, %BB_99 ], [ %178, %BB_109 ] + call void @llvm.memset.p0.i64(ptr noundef nonnull align 16 dereferenceable(108) %4, i8 0, i64 108, i1 false), !tbaa !9 + br i1 %9, label %BB_101, label %BB_107 + + BB_101: ; preds = %BB_100 + %42 = tail call ptr @__ctype_b_loc() #10 + %43 = load ptr, ptr %42, align 8, !tbaa !5 + br label %BB_102 + + BB_102: ; preds = %BB_105, %BB_101 + %44 = phi i64 [ 0, %BB_101 ], [ %65, %BB_105 ] + %45 = getelementptr inbounds ptr, ptr %0, i64 %44 + %46 = load ptr, ptr %45, align 8, !tbaa !5 + %47 = getelementptr inbounds i8, ptr %46, i64 %40 + %48 = load i8, ptr %47, align 1, !tbaa !11 + %49 = sext i8 %48 to i64 + %50 = getelementptr inbounds i16, ptr %43, i64 %49 + %51 = load i16, ptr %50, align 2, !tbaa !12 + %52 = and i16 %51, 1024 + %53 = icmp eq i16 %52, 0 + br i1 %53, label %BB_104, label %BB_103 + + BB_103: ; preds = %BB_102 + %54 = tail call ptr @__ctype_toupper_loc() #10 + %55 = load ptr, ptr %54, align 8, !tbaa !5 + %56 = getelementptr inbounds i32, ptr %55, i64 %49 + %57 = load i32, ptr %56, align 4, !tbaa !9 + %58 = add nsw i32 %57, -65 + %59 = sext i32 %58 to i64 + %60 = getelementptr inbounds [27 x i32], ptr %3, i64 0, i64 %59 + %61 = load i32, ptr %60, align 4, !tbaa !9 + %62 = add nsw i32 %61, 1 + store i32 %62, ptr %60, align 4, !tbaa !9 + br label %BB_105 + + BB_104: ; preds = %BB_102 + %63 = load i32, ptr %10, align 8, !tbaa !9 + %64 = add nsw i32 %63, 1 + store i32 %64, ptr %10, align 8, !tbaa !9 + br label %BB_105 + + BB_105: ; preds = %BB_104, %BB_103 + %65 = add nuw nsw i64 %44, 1 + %66 = icmp eq i64 %65, %13 + br i1 %66, label %BB_106, label %BB_102 + + BB_106: ; preds = %BB_105 + %67 = load i32, ptr %10, align 8, !tbaa !9 + br label %BB_107 + + BB_107: ; preds = %BB_106, %BB_100 + %68 = phi i32 [ %67, %BB_106 ], [ 0, %BB_100 ] + %69 = sitofp i32 %68 to float + %70 = fdiv float %69, %11 + %71 = fcmp ugt float %70, 5.000000e-01 + br i1 %71, label %BB_109, label %BB_108 + + BB_108: ; preds = %BB_107 + %72 = load i32, ptr %14, align 16, !tbaa !9 + %73 = icmp sgt i32 %72, -1 + %74 = select i1 %73, i32 %72, i32 -1 + %75 = load i32, ptr %15, align 4, !tbaa !9 + %76 = icmp sgt i32 %75, %74 + %77 = select i1 %76, i32 %75, i32 %74 + %78 = load i32, ptr %16, align 8, !tbaa !9 + %79 = icmp sgt i32 %78, %77 + %80 = select i1 %79, i32 %78, i32 %77 + %81 = load i32, ptr %17, align 4, !tbaa !9 + %82 = icmp sgt i32 %81, %80 + %83 = select i1 %82, i32 %81, i32 %80 + %84 = load i32, ptr %18, align 16, !tbaa !9 + %85 = icmp sgt i32 %84, %83 + %86 = select i1 %85, i32 %84, i32 %83 + %87 = load i32, ptr %19, align 4, !tbaa !9 + %88 = icmp sgt i32 %87, %86 + %89 = select i1 %88, i32 %87, i32 %86 + %90 = load i32, ptr %20, align 8, !tbaa !9 + %91 = icmp sgt i32 %90, %89 + %92 = select i1 %91, i32 %90, i32 %89 + %93 = load i32, ptr %21, align 4, !tbaa !9 + %94 = icmp sgt i32 %93, %92 + %95 = select i1 %94, i32 %93, i32 %92 + %96 = load i32, ptr %22, align 16, !tbaa !9 + %97 = icmp sgt i32 %96, %95 + %98 = select i1 %97, i32 %96, i32 %95 + %99 = load i32, ptr %23, align 4, !tbaa !9 + %100 = icmp sgt i32 %99, %98 + %101 = select i1 %100, i32 %99, i32 %98 + %102 = load i32, ptr %24, align 8, !tbaa !9 + %103 = icmp sgt i32 %102, %101 + %104 = select i1 %103, i32 %102, i32 %101 + %105 = load i32, ptr %25, align 4, !tbaa !9 + %106 = icmp sgt i32 %105, %104 + %107 = select i1 %106, i32 %105, i32 %104 + %108 = load i32, ptr %26, align 16, !tbaa !9 + %109 = icmp sgt i32 %108, %107 + %110 = select i1 %109, i32 %108, i32 %107 + %111 = load i32, ptr %27, align 4, !tbaa !9 + %112 = icmp sgt i32 %111, %110 + %113 = select i1 %112, i32 %111, i32 %110 + %114 = load i32, ptr %28, align 8, !tbaa !9 + %115 = icmp sgt i32 %114, %113 + %116 = select i1 %115, i32 %114, i32 %113 + %117 = load i32, ptr %29, align 4, !tbaa !9 + %118 = icmp sgt i32 %117, %116 + %119 = select i1 %118, i32 %117, i32 %116 + %120 = load i32, ptr %30, align 16, !tbaa !9 + %121 = icmp sgt i32 %120, %119 + %122 = select i1 %121, i32 %120, i32 %119 + %123 = load i32, ptr %31, align 4, !tbaa !9 + %124 = icmp sgt i32 %123, %122 + %125 = select i1 %124, i32 %123, i32 %122 + %126 = load i32, ptr %32, align 8, !tbaa !9 + %127 = icmp sgt i32 %126, %125 + %128 = select i1 %127, i32 %126, i32 %125 + %129 = load i32, ptr %33, align 4, !tbaa !9 + %130 = icmp sgt i32 %129, %128 + %131 = select i1 %130, i32 %129, i32 %128 + %132 = load i32, ptr %34, align 16, !tbaa !9 + %133 = icmp sgt i32 %132, %131 + %134 = select i1 %133, i32 %132, i32 %131 + %135 = load i32, ptr %35, align 4, !tbaa !9 + %136 = icmp sgt i32 %135, %134 + %137 = select i1 %136, i32 %135, i32 %134 + %138 = load i32, ptr %36, align 8, !tbaa !9 + %139 = icmp sgt i32 %138, %137 + %140 = select i1 %139, i32 %138, i32 %137 + %141 = load i32, ptr %37, align 4, !tbaa !9 + %142 = icmp sgt i32 %141, %140 + %143 = select i1 %142, i32 %141, i32 %140 + %144 = load i32, ptr %38, align 16, !tbaa !9 + %145 = icmp sgt i32 %144, %143 + %146 = select i1 %145, i32 %144, i32 %143 + %147 = load i32, ptr %39, align 4, !tbaa !9 + %148 = icmp sgt i32 %147, %146 + %149 = select i1 %73, i8 65, i8 64 + %150 = select i1 %76, i8 66, i8 %149 + %151 = select i1 %79, i8 67, i8 %150 + %152 = select i1 %82, i8 68, i8 %151 + %153 = select i1 %85, i8 69, i8 %152 + %154 = select i1 %88, i8 70, i8 %153 + %155 = select i1 %91, i8 71, i8 %154 + %156 = select i1 %94, i8 72, i8 %155 + %157 = select i1 %97, i8 73, i8 %156 + %158 = select i1 %100, i8 74, i8 %157 + %159 = select i1 %103, i8 75, i8 %158 + %160 = select i1 %106, i8 76, i8 %159 + %161 = select i1 %109, i8 77, i8 %160 + %162 = select i1 %112, i8 78, i8 %161 + %163 = select i1 %115, i8 79, i8 %162 + %164 = select i1 %118, i8 80, i8 %163 + %165 = select i1 %121, i8 81, i8 %164 + %166 = select i1 %124, i8 82, i8 %165 + %167 = select i1 %127, i8 83, i8 %166 + %168 = select i1 %130, i8 84, i8 %167 + %169 = select i1 %133, i8 85, i8 %168 + %170 = select i1 %136, i8 86, i8 %169 + %171 = select i1 %139, i8 87, i8 %170 + %172 = select i1 %142, i8 88, i8 %171 + %173 = select i1 %145, i8 89, i8 %172 + %174 = select i1 %148, i8 90, i8 %173 + %175 = add nsw i32 %41, 1 + %176 = sext i32 %41 to i64 + %177 = getelementptr inbounds i8, ptr %7, i64 %176 + store i8 %174, ptr %177, align 1, !tbaa !11 + br label %BB_109 + + BB_109: ; preds = %BB_108, %BB_107 + %178 = phi i32 [ %175, %BB_108 ], [ %41, %BB_107 ] + %179 = add nuw nsw i64 %40, 1 + %180 = icmp eq i64 %179, %12 + br i1 %180, label %BB_110, label %BB_100 + + BB_110: ; preds = %BB_109, %BB_98 + %181 = phi i32 [ 0, %BB_98 ], [ %178, %BB_109 ] + %182 = sext i32 %181 to i64 + %183 = getelementptr inbounds i8, ptr %7, i64 %182 + store i8 0, ptr %183, align 1, !tbaa !11 + call void @llvm.lifetime.end.p0(i64 108, ptr nonnull %4) #8 + ret ptr %7 + } + + declare ptr @sre_malloc(ptr noundef, i32 noundef, i64 noundef) local_unnamed_addr #3 + + ; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none) + declare ptr @__ctype_b_loc() local_unnamed_addr #4 + + ; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none) + declare ptr @__ctype_toupper_loc() local_unnamed_addr #4 + + ; Function Attrs: mustprogress nofree nounwind willreturn memory(argmem: read) + declare i64 @strlen(ptr nocapture noundef) local_unnamed_addr #5 + + ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) + declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #6 + + ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) + declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #6 + + ; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write) + declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #7 + + attributes #0 = { nounwind uwtable "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #1 = { mustprogress nounwind willreturn memory(argmem: readwrite, inaccessiblemem: readwrite) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #2 = { nofree norecurse nosync nounwind memory(read) uwtable "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #3 = { "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #4 = { mustprogress nofree nosync nounwind willreturn memory(none) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #5 = { mustprogress nofree nounwind willreturn memory(argmem: read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" } + attributes #6 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) } + attributes #7 = { nocallback nofree nounwind willreturn memory(argmem: write) } + attributes #8 = { nounwind } + attributes #9 = { nounwind willreturn memory(read) } + attributes #10 = { nounwind willreturn memory(none) } + + !llvm.module.flags = !{!0, !1, !2, !3} + !llvm.ident = !{!4} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{i32 8, !"PIC Level", i32 2} + !2 = !{i32 7, !"PIE Level", i32 2} + !3 = !{i32 7, !"uwtable", i32 1} + !4 = !{!"Ubuntu clang version 14.0.0-1ubuntu1.1"} + !5 = !{!6, !6, i64 0} + !6 = !{!"any pointer", !7, i64 0} + !7 = !{!"omnipotent char", !8, i64 0} + !8 = !{!"Simple C/C++ TBAA"} + !9 = !{!10, !10, i64 0} + !10 = !{!"int", !7, i64 0} + !11 = !{!7, !7, i64 0} + !12 = !{!13, !13, i64 0} + !13 = !{!"short", !7, i64 0} + +... +--- +name: ComparePairAlignments +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr32, preferred-register: '' } + - { id: 11, class: gr32, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: fr32, preferred-register: '' } + - { id: 16, class: fr32, preferred-register: '' } + - { id: 17, class: fr32, preferred-register: '' } + - { id: 18, class: gr64_nosp, preferred-register: '' } + - { id: 19, class: fr32, preferred-register: '' } + - { id: 20, class: fr32, preferred-register: '' } + - { id: 21, class: fr32, preferred-register: '' } + - { id: 22, class: fr32, preferred-register: '' } + - { id: 23, class: fr32, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64_nosp, preferred-register: '' } + - { id: 28, class: fr32, preferred-register: '' } + - { id: 29, class: fr32, preferred-register: '' } + - { id: 30, class: gr64, preferred-register: '' } + - { id: 31, class: fr32, preferred-register: '' } + - { id: 32, class: fr32, preferred-register: '' } + - { id: 33, class: gr64, preferred-register: '' } + - { id: 34, class: gr64, preferred-register: '' } + - { id: 35, class: gr64_nosp, preferred-register: '' } + - { id: 36, class: fr32, preferred-register: '' } + - { id: 37, class: fr32, preferred-register: '' } + - { id: 38, class: gr64, preferred-register: '' } + - { id: 39, class: fr32, preferred-register: '' } + - { id: 40, class: fr32, preferred-register: '' } + - { id: 41, class: gr64, preferred-register: '' } + - { id: 42, class: gr64, preferred-register: '' } + - { id: 43, class: fr32, preferred-register: '' } + - { id: 44, class: fr32, preferred-register: '' } + - { id: 45, class: gr64_nosp, preferred-register: '' } + - { id: 46, class: fr32, preferred-register: '' } + - { id: 47, class: fr32, preferred-register: '' } + - { id: 48, class: fr32, preferred-register: '' } + - { id: 49, class: fr32, preferred-register: '' } + - { id: 50, class: fr32, preferred-register: '' } + - { id: 51, class: fr32, preferred-register: '' } + - { id: 52, class: gr64, preferred-register: '' } + - { id: 53, class: gr64, preferred-register: '' } + - { id: 54, class: gr64, preferred-register: '' } + - { id: 55, class: gr64, preferred-register: '' } + - { id: 56, class: gr64, preferred-register: '' } + - { id: 57, class: gr64, preferred-register: '' } + - { id: 58, class: gr64, preferred-register: '' } + - { id: 59, class: gr64, preferred-register: '' } + - { id: 60, class: fr32, preferred-register: '' } + - { id: 61, class: gr32, preferred-register: '' } + - { id: 62, class: gr32, preferred-register: '' } + - { id: 63, class: gr64, preferred-register: '' } + - { id: 64, class: gr64, preferred-register: '' } + - { id: 65, class: gr64, preferred-register: '' } + - { id: 66, class: gr64, preferred-register: '' } + - { id: 67, class: gr64, preferred-register: '' } + - { id: 68, class: gr64, preferred-register: '' } + - { id: 69, class: gr64, preferred-register: '' } + - { id: 70, class: gr64, preferred-register: '' } + - { id: 71, class: gr64, preferred-register: '' } + - { id: 72, class: gr64, preferred-register: '' } + - { id: 73, class: gr64, preferred-register: '' } + - { id: 74, class: gr64, preferred-register: '' } + - { id: 75, class: gr64, preferred-register: '' } + - { id: 76, class: gr64, preferred-register: '' } + - { id: 77, class: gr64, preferred-register: '' } + - { id: 78, class: gr64, preferred-register: '' } + - { id: 79, class: gr64, preferred-register: '' } + - { id: 80, class: gr64, preferred-register: '' } + - { id: 81, class: fr32, preferred-register: '' } + - { id: 82, class: gr32, preferred-register: '' } + - { id: 83, class: gr64, preferred-register: '' } + - { id: 84, class: fr32, preferred-register: '' } + - { id: 85, class: fr32, preferred-register: '' } + - { id: 86, class: gr64, preferred-register: '' } + - { id: 87, class: gr32, preferred-register: '' } + - { id: 88, class: gr64, preferred-register: '' } + - { id: 89, class: gr32, preferred-register: '' } + - { id: 90, class: gr64, preferred-register: '' } + - { id: 91, class: fr32, preferred-register: '' } + - { id: 92, class: gr64, preferred-register: '' } + - { id: 93, class: gr64, preferred-register: '' } + - { id: 94, class: gr64, preferred-register: '' } + - { id: 95, class: gr64, preferred-register: '' } + - { id: 96, class: gr32, preferred-register: '' } + - { id: 97, class: gr32, preferred-register: '' } + - { id: 98, class: fr32, preferred-register: '' } + - { id: 99, class: fr32, preferred-register: '' } + - { id: 100, class: fr32, preferred-register: '' } + - { id: 101, class: fr32, preferred-register: '' } + - { id: 102, class: fr32, preferred-register: '' } + - { id: 103, class: gr64_nosp, preferred-register: '' } + - { id: 104, class: gr32, preferred-register: '' } + - { id: 105, class: gr32, preferred-register: '' } + - { id: 106, class: fr32, preferred-register: '' } + - { id: 107, class: fr32, preferred-register: '' } + - { id: 108, class: fr32, preferred-register: '' } + - { id: 109, class: gr64_nosp, preferred-register: '' } + - { id: 110, class: gr32, preferred-register: '' } + - { id: 111, class: gr32, preferred-register: '' } + - { id: 112, class: fr32, preferred-register: '' } + - { id: 113, class: fr32, preferred-register: '' } + - { id: 114, class: fr32, preferred-register: '' } + - { id: 115, class: fr32, preferred-register: '' } + - { id: 116, class: gr32, preferred-register: '' } + - { id: 117, class: gr32, preferred-register: '' } + - { id: 118, class: fr32, preferred-register: '' } + - { id: 119, class: fr32, preferred-register: '' } + - { id: 120, class: fr32, preferred-register: '' } + - { id: 121, class: fr32, preferred-register: '' } + - { id: 122, class: gr32, preferred-register: '' } + - { id: 123, class: gr32, preferred-register: '' } + - { id: 124, class: fr32, preferred-register: '' } + - { id: 125, class: fr32, preferred-register: '' } + - { id: 126, class: fr32, preferred-register: '' } + - { id: 127, class: fr32, preferred-register: '' } + - { id: 128, class: gr32, preferred-register: '' } + - { id: 129, class: gr32, preferred-register: '' } + - { id: 130, class: fr32, preferred-register: '' } + - { id: 131, class: gr32, preferred-register: '' } + - { id: 132, class: gr64, preferred-register: '' } + - { id: 133, class: gr64, preferred-register: '' } + - { id: 134, class: gr32, preferred-register: '' } + - { id: 135, class: gr64, preferred-register: '' } + - { id: 136, class: gr32, preferred-register: '' } + - { id: 137, class: gr64, preferred-register: '' } + - { id: 138, class: gr64, preferred-register: '' } + - { id: 139, class: gr64, preferred-register: '' } + - { id: 140, class: gr64, preferred-register: '' } + - { id: 141, class: gr64, preferred-register: '' } + - { id: 142, class: gr32, preferred-register: '' } + - { id: 143, class: gr32, preferred-register: '' } + - { id: 144, class: fr32, preferred-register: '' } + - { id: 145, class: fr32, preferred-register: '' } + - { id: 146, class: fr32, preferred-register: '' } + - { id: 147, class: fr32, preferred-register: '' } + - { id: 148, class: fr32, preferred-register: '' } + - { id: 149, class: gr64_nosp, preferred-register: '' } + - { id: 150, class: gr32, preferred-register: '' } + - { id: 151, class: gr32, preferred-register: '' } + - { id: 152, class: fr32, preferred-register: '' } + - { id: 153, class: fr32, preferred-register: '' } + - { id: 154, class: fr32, preferred-register: '' } + - { id: 155, class: gr64_nosp, preferred-register: '' } + - { id: 156, class: gr32, preferred-register: '' } + - { id: 157, class: gr32, preferred-register: '' } + - { id: 158, class: fr32, preferred-register: '' } + - { id: 159, class: fr32, preferred-register: '' } + - { id: 160, class: fr32, preferred-register: '' } + - { id: 161, class: fr32, preferred-register: '' } + - { id: 162, class: gr32, preferred-register: '' } + - { id: 163, class: gr32, preferred-register: '' } + - { id: 164, class: fr32, preferred-register: '' } + - { id: 165, class: fr32, preferred-register: '' } + - { id: 166, class: gr32, preferred-register: '' } + - { id: 167, class: gr32, preferred-register: '' } + - { id: 168, class: fr32, preferred-register: '' } + - { id: 169, class: fr32, preferred-register: '' } + - { id: 170, class: fr32, preferred-register: '' } + - { id: 171, class: fr32, preferred-register: '' } + - { id: 172, class: gr32, preferred-register: '' } + - { id: 173, class: gr32, preferred-register: '' } + - { id: 174, class: fr32, preferred-register: '' } + - { id: 175, class: fr32, preferred-register: '' } + - { id: 176, class: fr32, preferred-register: '' } + - { id: 177, class: gr64, preferred-register: '' } + - { id: 178, class: gr64, preferred-register: '' } + - { id: 179, class: gr64, preferred-register: '' } + - { id: 180, class: gr64, preferred-register: '' } + - { id: 181, class: fr32, preferred-register: '' } + - { id: 182, class: fr32, preferred-register: '' } + - { id: 183, class: fr32, preferred-register: '' } + - { id: 184, class: gr64_nosp, preferred-register: '' } + - { id: 185, class: fr32, preferred-register: '' } + - { id: 186, class: fr32, preferred-register: '' } + - { id: 187, class: fr32, preferred-register: '' } + - { id: 188, class: fr32, preferred-register: '' } + - { id: 189, class: fr32, preferred-register: '' } + - { id: 190, class: gr64_nosp, preferred-register: '' } + - { id: 191, class: fr32, preferred-register: '' } + - { id: 192, class: fr32, preferred-register: '' } + - { id: 193, class: gr64, preferred-register: '' } + - { id: 194, class: fr32, preferred-register: '' } + - { id: 195, class: fr32, preferred-register: '' } + - { id: 196, class: gr64_nosp, preferred-register: '' } + - { id: 197, class: fr32, preferred-register: '' } + - { id: 198, class: fr32, preferred-register: '' } + - { id: 199, class: gr64, preferred-register: '' } + - { id: 200, class: fr32, preferred-register: '' } + - { id: 201, class: fr32, preferred-register: '' } + - { id: 202, class: fr32, preferred-register: '' } + - { id: 203, class: fr32, preferred-register: '' } + - { id: 204, class: gr64_nosp, preferred-register: '' } + - { id: 205, class: fr32, preferred-register: '' } + - { id: 206, class: fr32, preferred-register: '' } + - { id: 207, class: fr32, preferred-register: '' } + - { id: 208, class: fr32, preferred-register: '' } + - { id: 209, class: fr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%52' } + - { reg: '$rsi', virtual-reg: '%54' } + - { reg: '$rdx', virtual-reg: '%56' } + - { reg: '$rcx', virtual-reg: '%58' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: + - id: 0 + value: 'float 1.000000e+00' + alignment: 4 + isTargetSpecific: false +machineFunctionInfo: {} +body: | + bb.0.BB_0: + successors: %bb.6(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $rsi, $rdx, $rcx + + %58:gr64 = COPY $rcx + %56:gr64 = COPY $rdx + %54:gr64 = COPY $rsi + %52:gr64 = COPY $rdi + %53:gr64 = COPY killed %52 + %55:gr64 = COPY killed %54 + %57:gr64 = COPY killed %56 + %59:gr64 = COPY killed %58 + %80:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %79:gr64 = LEA64r %stack.1, 1, $noreg, 0, $noreg + %78:gr64 = LEA64r %stack.2, 1, $noreg, 0, $noreg + %77:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + %76:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + %75:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + %73:gr64 = LEA64r %stack.2, 1, $noreg, 0, $noreg + %74:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %57 + $rsi = COPY %59 + $rdx = COPY %73 + $rcx = COPY %74 + CALL64pcrel32 @make_alilist, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %71:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + %72:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %59 + $rsi = COPY %57 + $rdx = COPY %71 + $rcx = COPY %72 + CALL64pcrel32 @make_alilist, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %69:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %70:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %53 + $rsi = COPY %55 + $rdx = COPY %69 + $rcx = COPY %70 + CALL64pcrel32 @make_alilist, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %67:gr64 = LEA64r %stack.1, 1, $noreg, 0, $noreg + %68:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %55 + $rsi = COPY %53 + $rdx = COPY %67 + $rcx = COPY %68 + CALL64pcrel32 @make_alilist, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %66:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.4, !tbaa !5) + %65:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5, !tbaa !5) + %64:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.6, !tbaa !5) + %63:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %ir.7, !tbaa !5) + %62:gr32 = MOV32rm %stack.4, 1, $noreg, 0, $noreg :: (load (s32) from %ir.8, !tbaa !9) + %61:gr32 = MOV32rm %stack.5, 1, $noreg, 0, $noreg :: (load (s32) from %ir.9, !tbaa !9) + %60:fr32 = FsFLD0SS + CMP32ri %62, 0, implicit-def $eflags + %188:fr32 = COPY %60 + %189:fr32 = COPY %60 + JCC_1 %bb.6, 14, implicit $eflags + + bb.1.BB_1: + successors: %bb.4(0x40000000), %bb.2(0x40000000) + + %87:gr32 = MOV32rr %62 + %88:gr64 = SUBREG_TO_REG 0, %87, %subreg.sub_32bit + %86:gr64 = AND64ri32 %88, 1, implicit-def $eflags + %82:gr32 = MOV32r0 implicit-def $eflags + %83:gr64 = SUBREG_TO_REG 0, %82, %subreg.sub_32bit + %84:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %85:fr32 = FsFLD0SS + CMP32ri %62, 1, implicit-def $eflags + %182:fr32 = IMPLICIT_DEF + %183:fr32 = IMPLICIT_DEF + %184:gr64_nosp = COPY %83 + %185:fr32 = COPY %84 + %186:fr32 = COPY %85 + JCC_1 %bb.4, 4, implicit $eflags + + bb.2.BB_2: + successors: %bb.9(0x80000000) + + %92:gr64 = MOV64ri 4294967294 + %93:gr64 = AND64rr %88, %92, implicit-def $eflags + %89:gr32 = MOV32r0 implicit-def $eflags + %90:gr64 = SUBREG_TO_REG 0, %89, %subreg.sub_32bit + %91:fr32 = FsFLD0SS + %190:gr64_nosp = COPY %90 + %191:fr32 = COPY %91 + %192:fr32 = COPY %91 + %193:gr64 = COPY %90 + JMP_1 %bb.9 + + bb.3.BB_3: + successors: %bb.4(0x80000000) + + %120:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %121:fr32 = ADDSSrr %108, %120, implicit $mxcsr + %182:fr32 = COPY %108 + %183:fr32 = COPY %100 + %184:gr64_nosp = COPY %95 + %185:fr32 = COPY %121 + %186:fr32 = COPY %100 + + bb.4.BB_4: + successors: %bb.6(0x40000000), %bb.5(0x40000000) + + %20:fr32 = COPY %186 + %19:fr32 = COPY %185 + %18:gr64_nosp = COPY %184 + %17:fr32 = COPY %183 + %16:fr32 = COPY %182 + CMP64ri32 %86, 0, implicit-def $eflags + %188:fr32 = COPY %17 + %189:fr32 = COPY %16 + JCC_1 %bb.6, 4, implicit $eflags + + bb.5.BB_5: + successors: %bb.14(0x40000000), %bb.15(0x40000000) + + %129:gr32 = MOV32rm %64, 4, %18, 0, $noreg :: (load (s32) from %ir.34, !tbaa !9) + %128:gr32 = MOV32rm %66, 4, %18, 0, $noreg :: (load (s32) from %ir.36, !tbaa !9) + %126:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %127:fr32 = ADDSSrr %20, %126, implicit $mxcsr + CMP32rr %129, %128, implicit-def $eflags + %187:fr32 = COPY %127 + JCC_1 %bb.15, 4, implicit $eflags + + bb.14.BB_5: + successors: %bb.15(0x80000000) + + %187:fr32 = COPY %20 + + bb.15.BB_5: + successors: %bb.6(0x80000000) + + %125:fr32 = COPY %187 + %188:fr32 = COPY %125 + %189:fr32 = COPY %19 + + bb.6.BB_6: + successors: %bb.13(0x40000000), %bb.7(0x40000000) + + %23:fr32 = COPY %189 + %22:fr32 = COPY %188 + CMP32ri %61, 0, implicit-def $eflags + %208:fr32 = COPY %22 + %209:fr32 = COPY %23 + JCC_1 %bb.13, 14, implicit $eflags + + bb.7.BB_7: + successors: %bb.11(0x40000000), %bb.8(0x40000000) + + %134:gr32 = MOV32rr %61 + %135:gr64 = SUBREG_TO_REG 0, %134, %subreg.sub_32bit + %133:gr64 = AND64ri32 %135, 1, implicit-def $eflags + %131:gr32 = MOV32r0 implicit-def $eflags + %132:gr64 = SUBREG_TO_REG 0, %131, %subreg.sub_32bit + CMP32ri %61, 1, implicit-def $eflags + %202:fr32 = IMPLICIT_DEF + %203:fr32 = IMPLICIT_DEF + %204:gr64_nosp = COPY %132 + %205:fr32 = COPY %23 + %206:fr32 = COPY %22 + JCC_1 %bb.11, 4, implicit $eflags + + bb.8.BB_8: + successors: %bb.10(0x80000000) + + %138:gr64 = MOV64ri 4294967294 + %139:gr64 = AND64rr %135, %138, implicit-def $eflags + %136:gr32 = MOV32r0 implicit-def $eflags + %137:gr64 = SUBREG_TO_REG 0, %136, %subreg.sub_32bit + %196:gr64_nosp = COPY %137 + %197:fr32 = COPY %23 + %198:fr32 = COPY %22 + %199:gr64 = COPY %137 + JMP_1 %bb.10 + + bb.9.BB_9: + successors: %bb.16(0x40000000), %bb.17(0x40000000) + + %30:gr64 = COPY %193 + %29:fr32 = COPY %192 + %28:fr32 = COPY %191 + %27:gr64_nosp = COPY %190 + %118:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %119:fr32 = ADDSSrr %28, %118, implicit $mxcsr + %117:gr32 = MOV32rm %64, 4, %27, 0, $noreg :: (load (s32) from %ir.53, !tbaa !9) + %116:gr32 = MOV32rm %66, 4, %27, 0, $noreg :: (load (s32) from %ir.55, !tbaa !9) + %114:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %115:fr32 = ADDSSrr %29, %114, implicit $mxcsr + CMP32rr %117, %116, implicit-def $eflags + %194:fr32 = COPY %115 + JCC_1 %bb.17, 4, implicit $eflags + + bb.16.BB_9: + successors: %bb.17(0x80000000) + + %194:fr32 = COPY %29 + + bb.17.BB_9: + successors: %bb.18(0x40000000), %bb.19(0x40000000) + + %113:fr32 = COPY %194 + %109:gr64_nosp = OR64ri32 %27, 1, implicit-def $eflags + %107:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %108:fr32 = ADDSSrr %119, %107, implicit $mxcsr + %105:gr32 = MOV32rm %64, 4, %109, 0, $noreg :: (load (s32) from %ir.62, !tbaa !9) + %104:gr32 = MOV32rm %66, 4, %109, 0, $noreg :: (load (s32) from %ir.64, !tbaa !9) + %101:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %102:fr32 = ADDSSrr %113, %101, implicit $mxcsr + CMP32rr %105, %104, implicit-def $eflags + %195:fr32 = COPY %102 + JCC_1 %bb.19, 4, implicit $eflags + + bb.18.BB_9: + successors: %bb.19(0x80000000) + + %195:fr32 = COPY %113 + + bb.19.BB_9: + successors: %bb.3(0x40000000), %bb.9(0x40000000) + + %100:fr32 = COPY %195 + %95:gr64 = ADD64ri32 %27, 2, implicit-def $eflags + %94:gr64 = ADD64ri32 %30, 2, implicit-def $eflags + CMP64rr %94, %93, implicit-def $eflags + %190:gr64_nosp = COPY %95 + %191:fr32 = COPY %108 + %192:fr32 = COPY %100 + %193:gr64 = COPY %94 + JCC_1 %bb.3, 4, implicit $eflags + JMP_1 %bb.9 + + bb.10.BB_10: + successors: %bb.20(0x40000000), %bb.21(0x40000000) + + %38:gr64 = COPY %199 + %37:fr32 = COPY %198 + %36:fr32 = COPY %197 + %35:gr64_nosp = COPY %196 + %164:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %165:fr32 = ADDSSrr %36, %164, implicit $mxcsr + %163:gr32 = MOV32rm %65, 4, %35, 0, $noreg :: (load (s32) from %ir.77, !tbaa !9) + %162:gr32 = MOV32rm %63, 4, %35, 0, $noreg :: (load (s32) from %ir.79, !tbaa !9) + %160:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %161:fr32 = ADDSSrr %37, %160, implicit $mxcsr + CMP32rr %163, %162, implicit-def $eflags + %200:fr32 = COPY %161 + JCC_1 %bb.21, 4, implicit $eflags + + bb.20.BB_10: + successors: %bb.21(0x80000000) + + %200:fr32 = COPY %37 + + bb.21.BB_10: + successors: %bb.22(0x40000000), %bb.23(0x40000000) + + %159:fr32 = COPY %200 + %155:gr64_nosp = OR64ri32 %35, 1, implicit-def $eflags + %153:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %154:fr32 = ADDSSrr %165, %153, implicit $mxcsr + %151:gr32 = MOV32rm %65, 4, %155, 0, $noreg :: (load (s32) from %ir.86, !tbaa !9) + %150:gr32 = MOV32rm %63, 4, %155, 0, $noreg :: (load (s32) from %ir.88, !tbaa !9) + %147:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %148:fr32 = ADDSSrr %159, %147, implicit $mxcsr + CMP32rr %151, %150, implicit-def $eflags + %201:fr32 = COPY %148 + JCC_1 %bb.23, 4, implicit $eflags + + bb.22.BB_10: + successors: %bb.23(0x80000000) + + %201:fr32 = COPY %159 + + bb.23.BB_10: + successors: %bb.10(0x40000000), %bb.11(0x40000000) + + %146:fr32 = COPY %201 + %141:gr64 = ADD64ri32 %35, 2, implicit-def $eflags + %140:gr64 = ADD64ri32 %38, 2, implicit-def $eflags + CMP64rr %140, %139, implicit-def $eflags + %196:gr64_nosp = COPY %141 + %197:fr32 = COPY %154 + %198:fr32 = COPY %146 + %199:gr64 = COPY %140 + %202:fr32 = COPY %154 + %203:fr32 = COPY %146 + %204:gr64_nosp = COPY %141 + %205:fr32 = COPY %154 + %206:fr32 = COPY %146 + JCC_1 %bb.10, 5, implicit $eflags + + bb.11.BB_11: + successors: %bb.13(0x40000000), %bb.12(0x40000000) + + %47:fr32 = COPY %206 + %46:fr32 = COPY %205 + %45:gr64_nosp = COPY %204 + %44:fr32 = COPY %203 + %43:fr32 = COPY %202 + CMP64ri32 %133, 0, implicit-def $eflags + %208:fr32 = COPY %44 + %209:fr32 = COPY %43 + JCC_1 %bb.13, 4, implicit $eflags + + bb.12.BB_12: + successors: %bb.24(0x40000000), %bb.25(0x40000000) + + %174:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %175:fr32 = ADDSSrr %46, %174, implicit $mxcsr + %173:gr32 = MOV32rm %65, 4, %45, 0, $noreg :: (load (s32) from %ir.103, !tbaa !9) + %172:gr32 = MOV32rm %63, 4, %45, 0, $noreg :: (load (s32) from %ir.105, !tbaa !9) + %170:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %171:fr32 = ADDSSrr %47, %170, implicit $mxcsr + CMP32rr %173, %172, implicit-def $eflags + %207:fr32 = COPY %171 + JCC_1 %bb.25, 4, implicit $eflags + + bb.24.BB_12: + successors: %bb.25(0x80000000) + + %207:fr32 = COPY %47 + + bb.25.BB_12: + successors: %bb.13(0x80000000) + + %169:fr32 = COPY %207 + %208:fr32 = COPY %169 + %209:fr32 = COPY %175 + + bb.13.BB_13: + %51:fr32 = COPY %209 + %50:fr32 = COPY %208 + %181:fr32 = DIVSSrr %50, %51, implicit $mxcsr + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %66 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %65 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %64 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %63 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $xmm0 = COPY %181 + RET64 implicit $xmm0 + +... +--- +name: make_alilist +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64_nosp, preferred-register: '' } + - { id: 3, class: gr32, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr8, preferred-register: '' } + - { id: 6, class: gr32, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr32, preferred-register: '' } + - { id: 9, class: gr32, preferred-register: '' } + - { id: 10, class: gr32, preferred-register: '' } + - { id: 11, class: gr32, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr32, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr32, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr32, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr8, preferred-register: '' } + - { id: 28, class: gr8, preferred-register: '' } + - { id: 29, class: gr8, preferred-register: '' } + - { id: 30, class: gr8, preferred-register: '' } + - { id: 31, class: gr8, preferred-register: '' } + - { id: 32, class: gr8, preferred-register: '' } + - { id: 33, class: gr32, preferred-register: '' } + - { id: 34, class: gr32, preferred-register: '' } + - { id: 35, class: gr8, preferred-register: '' } + - { id: 36, class: gr8, preferred-register: '' } + - { id: 37, class: gr8, preferred-register: '' } + - { id: 38, class: gr8, preferred-register: '' } + - { id: 39, class: gr32, preferred-register: '' } + - { id: 40, class: gr32, preferred-register: '' } + - { id: 41, class: gr32, preferred-register: '' } + - { id: 42, class: gr64_nosp, preferred-register: '' } + - { id: 43, class: gr64_nosp, preferred-register: '' } + - { id: 44, class: gr8, preferred-register: '' } + - { id: 45, class: gr8, preferred-register: '' } + - { id: 46, class: gr8, preferred-register: '' } + - { id: 47, class: gr8, preferred-register: '' } + - { id: 48, class: gr8, preferred-register: '' } + - { id: 49, class: gr8, preferred-register: '' } + - { id: 50, class: gr32, preferred-register: '' } + - { id: 51, class: gr64, preferred-register: '' } + - { id: 52, class: gr64_nosp, preferred-register: '' } + - { id: 53, class: gr32, preferred-register: '' } + - { id: 54, class: gr32, preferred-register: '' } + - { id: 55, class: gr32, preferred-register: '' } + - { id: 56, class: gr32, preferred-register: '' } + - { id: 57, class: gr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%13' } + - { reg: '$rsi', virtual-reg: '%14' } + - { reg: '$rdx', virtual-reg: '%15' } + - { reg: '$rcx', virtual-reg: '%16' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_14: + successors: %bb.1(0x80000000) + liveins: $rdi, $rsi, $rdx, $rcx + + %16:gr64 = COPY $rcx + %15:gr64 = COPY $rdx + %14:gr64 = COPY $rsi + %13:gr64 = COPY $rdi + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %13 + CALL64pcrel32 target-flags(x86-plt) @strlen, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %26:gr64 = COPY $rax + %24:gr64 = COPY %26 + %25:gr64 = SHL64ri %24, 2, implicit-def $eflags + %20:gr64 = MOV64ri @.str + %21:gr32 = MOV32ri 179 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %20 + $esi = COPY %21 + $rdx = COPY %25 + CALL64pcrel32 target-flags(x86-plt) @sre_malloc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit $rdx, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %23:gr64 = COPY $rax + %17:gr32 = MOV32r0 implicit-def $eflags + %18:gr64 = SUBREG_TO_REG 0, %17, %subreg.sub_32bit + %19:gr32 = MOV32r0 implicit-def $eflags + %52:gr64_nosp = COPY %18 + %53:gr32 = COPY %19 + %54:gr32 = COPY %19 + + bb.1.BB_15: + successors: %bb.8(0x40000000), %bb.9(0x40000000) + + %4:gr32 = COPY %54 + %3:gr32 = COPY %53 + %2:gr64_nosp = COPY %52 + %27:gr8 = MOV8rm %13, 1, %2, 0, $noreg :: (load (s8) from %ir.11, !tbaa !11) + TEST8rr %27, %27, implicit-def $eflags + JCC_1 %bb.8, 4, implicit $eflags + JMP_1 %bb.9 + + bb.9.BB_15: + successors: %bb.5(0x40000000), %bb.10(0x40000000) + + %28:gr8 = SUB8ri %27, 32, implicit-def $eflags + %56:gr32 = COPY %3 + JCC_1 %bb.5, 4, implicit $eflags + JMP_1 %bb.10 + + bb.10.BB_15: + successors: %bb.5(0x40000000), %bb.11(0x40000000) + + %29:gr8 = ADD8ri %27, -45, implicit-def dead $eflags + %30:gr8 = SUB8ri %29, 2, implicit-def $eflags + %56:gr32 = COPY %3 + JCC_1 %bb.5, 2, implicit $eflags + JMP_1 %bb.11 + + bb.11.BB_15: + successors: %bb.5(0x40000000), %bb.12(0x40000000) + + %31:gr8 = SUB8ri %27, 95, implicit-def $eflags + %56:gr32 = COPY %3 + JCC_1 %bb.5, 4, implicit $eflags + JMP_1 %bb.12 + + bb.12.BB_15: + successors: %bb.5(0x40000000), %bb.2(0x40000000) + + %32:gr8 = SUB8ri %27, 126, implicit-def $eflags + %56:gr32 = COPY %3 + JCC_1 %bb.5, 4, implicit $eflags + JMP_1 %bb.2 + + bb.2.BB_16: + successors: %bb.4(0x40000000), %bb.13(0x40000000) + + %5:gr8 = MOV8rm %14, 1, %2, 0, $noreg :: (load (s8) from %ir.13, !tbaa !11) + %34:gr32 = MOV32ri -1 + %35:gr8 = SUB8ri %5, 32, implicit-def $eflags + %55:gr32 = COPY %34 + JCC_1 %bb.4, 4, implicit $eflags + JMP_1 %bb.13 + + bb.13.BB_16: + successors: %bb.4(0x40000000), %bb.14(0x40000000) + + %36:gr8 = ADD8ri %5, -45, implicit-def dead $eflags + %37:gr8 = SUB8ri %36, 2, implicit-def $eflags + %55:gr32 = COPY %34 + JCC_1 %bb.4, 2, implicit $eflags + JMP_1 %bb.14 + + bb.14.BB_16: + successors: %bb.4(0x40000000), %bb.3(0x40000000) + + %38:gr8 = SUB8ri %5, 95, implicit-def $eflags + %55:gr32 = COPY %34 + JCC_1 %bb.4, 4, implicit $eflags + JMP_1 %bb.3 + + bb.3.BB_17: + successors: %bb.4(0x80000000) + + %39:gr32 = MOV32ri 4294967295 + CMP8ri %5, 126, implicit-def $eflags + %40:gr32 = CMOV32rr %4, %39, 4, implicit $eflags + %55:gr32 = COPY %40 + + bb.4.BB_18: + successors: %bb.5(0x80000000) + + %7:gr32 = COPY %55 + %43:gr64_nosp = MOVSX64rr32 %3 + MOV32mr %23, 4, %43, 0, $noreg, %7 :: (store (s32) into %ir.19, !tbaa !9) + %41:gr32 = ADD32ri %3, 1, implicit-def $eflags + %56:gr32 = COPY %41 + + bb.5.BB_19: + successors: %bb.7(0x40000000), %bb.15(0x40000000) + + %9:gr32 = COPY %56 + %44:gr8 = MOV8rm %14, 1, %2, 0, $noreg :: (load (s8) from %ir.22, !tbaa !11) + %45:gr8 = SUB8ri %44, 32, implicit-def $eflags + %57:gr32 = COPY %4 + JCC_1 %bb.7, 4, implicit $eflags + JMP_1 %bb.15 + + bb.15.BB_19: + successors: %bb.7(0x40000000), %bb.16(0x40000000) + + %46:gr8 = ADD8ri %44, -45, implicit-def dead $eflags + %47:gr8 = SUB8ri %46, 2, implicit-def $eflags + %57:gr32 = COPY %4 + JCC_1 %bb.7, 2, implicit $eflags + JMP_1 %bb.16 + + bb.16.BB_19: + successors: %bb.7(0x40000000), %bb.17(0x40000000) + + %48:gr8 = SUB8ri %44, 95, implicit-def $eflags + %57:gr32 = COPY %4 + JCC_1 %bb.7, 4, implicit $eflags + JMP_1 %bb.17 + + bb.17.BB_19: + successors: %bb.7(0x40000000), %bb.6(0x40000000) + + %49:gr8 = SUB8ri %44, 126, implicit-def $eflags + %57:gr32 = COPY %4 + JCC_1 %bb.7, 4, implicit $eflags + JMP_1 %bb.6 + + bb.6.BB_20: + successors: %bb.7(0x80000000) + + %50:gr32 = ADD32ri %4, 1, implicit-def $eflags + %57:gr32 = COPY %50 + + bb.7.BB_21: + successors: %bb.1(0x80000000) + + %11:gr32 = COPY %57 + %51:gr64 = ADD64ri32 %2, 1, implicit-def $eflags + %52:gr64_nosp = COPY %51 + %53:gr32 = COPY %9 + %54:gr32 = COPY %11 + JMP_1 %bb.1 + + bb.8.BB_22: + MOV32mr %16, 1, $noreg, 0, $noreg, %3 :: (store (s32) into %ir.3, !tbaa !9) + MOV64mr %15, 1, $noreg, 0, $noreg, %23 :: (store (s64) into %ir.27, !tbaa !5) + RET64 + +... +--- +name: CompareRefPairAlignments +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr32, preferred-register: '' } + - { id: 11, class: gr32, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: fr32, preferred-register: '' } + - { id: 16, class: fr32, preferred-register: '' } + - { id: 17, class: fr32, preferred-register: '' } + - { id: 18, class: gr64_nosp, preferred-register: '' } + - { id: 19, class: fr32, preferred-register: '' } + - { id: 20, class: fr32, preferred-register: '' } + - { id: 21, class: fr32, preferred-register: '' } + - { id: 22, class: fr32, preferred-register: '' } + - { id: 23, class: fr32, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64_nosp, preferred-register: '' } + - { id: 28, class: fr32, preferred-register: '' } + - { id: 29, class: fr32, preferred-register: '' } + - { id: 30, class: gr64, preferred-register: '' } + - { id: 31, class: fr32, preferred-register: '' } + - { id: 32, class: fr32, preferred-register: '' } + - { id: 33, class: gr64, preferred-register: '' } + - { id: 34, class: gr64, preferred-register: '' } + - { id: 35, class: gr64_nosp, preferred-register: '' } + - { id: 36, class: fr32, preferred-register: '' } + - { id: 37, class: fr32, preferred-register: '' } + - { id: 38, class: gr64, preferred-register: '' } + - { id: 39, class: fr32, preferred-register: '' } + - { id: 40, class: fr32, preferred-register: '' } + - { id: 41, class: gr64, preferred-register: '' } + - { id: 42, class: gr64, preferred-register: '' } + - { id: 43, class: fr32, preferred-register: '' } + - { id: 44, class: fr32, preferred-register: '' } + - { id: 45, class: gr64_nosp, preferred-register: '' } + - { id: 46, class: fr32, preferred-register: '' } + - { id: 47, class: fr32, preferred-register: '' } + - { id: 48, class: fr32, preferred-register: '' } + - { id: 49, class: fr32, preferred-register: '' } + - { id: 50, class: fr32, preferred-register: '' } + - { id: 51, class: fr32, preferred-register: '' } + - { id: 52, class: gr64, preferred-register: '' } + - { id: 53, class: gr64, preferred-register: '' } + - { id: 54, class: gr64, preferred-register: '' } + - { id: 55, class: gr64, preferred-register: '' } + - { id: 56, class: gr64, preferred-register: '' } + - { id: 57, class: gr64, preferred-register: '' } + - { id: 58, class: gr64, preferred-register: '' } + - { id: 59, class: gr64, preferred-register: '' } + - { id: 60, class: gr64, preferred-register: '' } + - { id: 61, class: gr64, preferred-register: '' } + - { id: 62, class: fr32, preferred-register: '' } + - { id: 63, class: gr32, preferred-register: '' } + - { id: 64, class: gr32, preferred-register: '' } + - { id: 65, class: gr64, preferred-register: '' } + - { id: 66, class: gr64, preferred-register: '' } + - { id: 67, class: gr64, preferred-register: '' } + - { id: 68, class: gr64, preferred-register: '' } + - { id: 69, class: gr64, preferred-register: '' } + - { id: 70, class: gr64, preferred-register: '' } + - { id: 71, class: gr64, preferred-register: '' } + - { id: 72, class: gr64, preferred-register: '' } + - { id: 73, class: gr64, preferred-register: '' } + - { id: 74, class: gr64, preferred-register: '' } + - { id: 75, class: gr64, preferred-register: '' } + - { id: 76, class: gr64, preferred-register: '' } + - { id: 77, class: gr64, preferred-register: '' } + - { id: 78, class: gr64, preferred-register: '' } + - { id: 79, class: gr64, preferred-register: '' } + - { id: 80, class: gr64, preferred-register: '' } + - { id: 81, class: gr64, preferred-register: '' } + - { id: 82, class: gr64, preferred-register: '' } + - { id: 83, class: fr32, preferred-register: '' } + - { id: 84, class: gr32, preferred-register: '' } + - { id: 85, class: gr64, preferred-register: '' } + - { id: 86, class: fr32, preferred-register: '' } + - { id: 87, class: fr32, preferred-register: '' } + - { id: 88, class: gr64, preferred-register: '' } + - { id: 89, class: gr32, preferred-register: '' } + - { id: 90, class: gr64, preferred-register: '' } + - { id: 91, class: gr32, preferred-register: '' } + - { id: 92, class: gr64, preferred-register: '' } + - { id: 93, class: fr32, preferred-register: '' } + - { id: 94, class: gr64, preferred-register: '' } + - { id: 95, class: gr64, preferred-register: '' } + - { id: 96, class: gr64, preferred-register: '' } + - { id: 97, class: gr64, preferred-register: '' } + - { id: 98, class: gr32, preferred-register: '' } + - { id: 99, class: gr32, preferred-register: '' } + - { id: 100, class: fr32, preferred-register: '' } + - { id: 101, class: fr32, preferred-register: '' } + - { id: 102, class: fr32, preferred-register: '' } + - { id: 103, class: fr32, preferred-register: '' } + - { id: 104, class: fr32, preferred-register: '' } + - { id: 105, class: gr64_nosp, preferred-register: '' } + - { id: 106, class: gr32, preferred-register: '' } + - { id: 107, class: gr32, preferred-register: '' } + - { id: 108, class: fr32, preferred-register: '' } + - { id: 109, class: fr32, preferred-register: '' } + - { id: 110, class: fr32, preferred-register: '' } + - { id: 111, class: gr64_nosp, preferred-register: '' } + - { id: 112, class: gr32, preferred-register: '' } + - { id: 113, class: gr32, preferred-register: '' } + - { id: 114, class: fr32, preferred-register: '' } + - { id: 115, class: fr32, preferred-register: '' } + - { id: 116, class: fr32, preferred-register: '' } + - { id: 117, class: fr32, preferred-register: '' } + - { id: 118, class: gr32, preferred-register: '' } + - { id: 119, class: gr32, preferred-register: '' } + - { id: 120, class: fr32, preferred-register: '' } + - { id: 121, class: fr32, preferred-register: '' } + - { id: 122, class: fr32, preferred-register: '' } + - { id: 123, class: fr32, preferred-register: '' } + - { id: 124, class: gr32, preferred-register: '' } + - { id: 125, class: gr32, preferred-register: '' } + - { id: 126, class: fr32, preferred-register: '' } + - { id: 127, class: fr32, preferred-register: '' } + - { id: 128, class: fr32, preferred-register: '' } + - { id: 129, class: fr32, preferred-register: '' } + - { id: 130, class: gr32, preferred-register: '' } + - { id: 131, class: gr32, preferred-register: '' } + - { id: 132, class: fr32, preferred-register: '' } + - { id: 133, class: gr32, preferred-register: '' } + - { id: 134, class: gr64, preferred-register: '' } + - { id: 135, class: gr64, preferred-register: '' } + - { id: 136, class: gr32, preferred-register: '' } + - { id: 137, class: gr64, preferred-register: '' } + - { id: 138, class: gr32, preferred-register: '' } + - { id: 139, class: gr64, preferred-register: '' } + - { id: 140, class: gr64, preferred-register: '' } + - { id: 141, class: gr64, preferred-register: '' } + - { id: 142, class: gr64, preferred-register: '' } + - { id: 143, class: gr64, preferred-register: '' } + - { id: 144, class: gr32, preferred-register: '' } + - { id: 145, class: gr32, preferred-register: '' } + - { id: 146, class: fr32, preferred-register: '' } + - { id: 147, class: fr32, preferred-register: '' } + - { id: 148, class: fr32, preferred-register: '' } + - { id: 149, class: fr32, preferred-register: '' } + - { id: 150, class: fr32, preferred-register: '' } + - { id: 151, class: gr64_nosp, preferred-register: '' } + - { id: 152, class: gr32, preferred-register: '' } + - { id: 153, class: gr32, preferred-register: '' } + - { id: 154, class: fr32, preferred-register: '' } + - { id: 155, class: fr32, preferred-register: '' } + - { id: 156, class: fr32, preferred-register: '' } + - { id: 157, class: gr64_nosp, preferred-register: '' } + - { id: 158, class: gr32, preferred-register: '' } + - { id: 159, class: gr32, preferred-register: '' } + - { id: 160, class: fr32, preferred-register: '' } + - { id: 161, class: fr32, preferred-register: '' } + - { id: 162, class: fr32, preferred-register: '' } + - { id: 163, class: fr32, preferred-register: '' } + - { id: 164, class: gr32, preferred-register: '' } + - { id: 165, class: gr32, preferred-register: '' } + - { id: 166, class: fr32, preferred-register: '' } + - { id: 167, class: fr32, preferred-register: '' } + - { id: 168, class: gr32, preferred-register: '' } + - { id: 169, class: gr32, preferred-register: '' } + - { id: 170, class: fr32, preferred-register: '' } + - { id: 171, class: fr32, preferred-register: '' } + - { id: 172, class: fr32, preferred-register: '' } + - { id: 173, class: fr32, preferred-register: '' } + - { id: 174, class: gr32, preferred-register: '' } + - { id: 175, class: gr32, preferred-register: '' } + - { id: 176, class: fr32, preferred-register: '' } + - { id: 177, class: fr32, preferred-register: '' } + - { id: 178, class: fr32, preferred-register: '' } + - { id: 179, class: gr64, preferred-register: '' } + - { id: 180, class: gr64, preferred-register: '' } + - { id: 181, class: gr64, preferred-register: '' } + - { id: 182, class: gr64, preferred-register: '' } + - { id: 183, class: fr32, preferred-register: '' } + - { id: 184, class: fr32, preferred-register: '' } + - { id: 185, class: fr32, preferred-register: '' } + - { id: 186, class: gr64_nosp, preferred-register: '' } + - { id: 187, class: fr32, preferred-register: '' } + - { id: 188, class: fr32, preferred-register: '' } + - { id: 189, class: fr32, preferred-register: '' } + - { id: 190, class: fr32, preferred-register: '' } + - { id: 191, class: fr32, preferred-register: '' } + - { id: 192, class: gr64_nosp, preferred-register: '' } + - { id: 193, class: fr32, preferred-register: '' } + - { id: 194, class: fr32, preferred-register: '' } + - { id: 195, class: gr64, preferred-register: '' } + - { id: 196, class: fr32, preferred-register: '' } + - { id: 197, class: fr32, preferred-register: '' } + - { id: 198, class: gr64_nosp, preferred-register: '' } + - { id: 199, class: fr32, preferred-register: '' } + - { id: 200, class: fr32, preferred-register: '' } + - { id: 201, class: gr64, preferred-register: '' } + - { id: 202, class: fr32, preferred-register: '' } + - { id: 203, class: fr32, preferred-register: '' } + - { id: 204, class: fr32, preferred-register: '' } + - { id: 205, class: fr32, preferred-register: '' } + - { id: 206, class: gr64_nosp, preferred-register: '' } + - { id: 207, class: fr32, preferred-register: '' } + - { id: 208, class: fr32, preferred-register: '' } + - { id: 209, class: fr32, preferred-register: '' } + - { id: 210, class: fr32, preferred-register: '' } + - { id: 211, class: fr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%52' } + - { reg: '$rsi', virtual-reg: '%54' } + - { reg: '$rdx', virtual-reg: '%56' } + - { reg: '$rcx', virtual-reg: '%58' } + - { reg: '$r8', virtual-reg: '%60' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 2, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 3, name: '', type: default, offset: 0, size: 8, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 4, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 5, name: '', type: default, offset: 0, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: + - id: 0 + value: 'float 1.000000e+00' + alignment: 4 + isTargetSpecific: false +machineFunctionInfo: {} +body: | + bb.0.BB_23: + successors: %bb.6(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $rsi, $rdx, $rcx, $r8 + + %60:gr64 = COPY $r8 + %58:gr64 = COPY $rcx + %56:gr64 = COPY $rdx + %54:gr64 = COPY $rsi + %52:gr64 = COPY $rdi + %53:gr64 = COPY killed %52 + %55:gr64 = COPY killed %54 + %57:gr64 = COPY killed %56 + %59:gr64 = COPY killed %58 + %61:gr64 = COPY killed %60 + %82:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %81:gr64 = LEA64r %stack.1, 1, $noreg, 0, $noreg + %80:gr64 = LEA64r %stack.2, 1, $noreg, 0, $noreg + %79:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + %78:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + %77:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + %75:gr64 = LEA64r %stack.2, 1, $noreg, 0, $noreg + %76:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %53 + $rsi = COPY %55 + $rdx = COPY %59 + $rcx = COPY %61 + $r8 = COPY %75 + $r9 = COPY %76 + CALL64pcrel32 @make_ref_alilist, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit $r8, implicit $r9 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %73:gr64 = LEA64r %stack.3, 1, $noreg, 0, $noreg + %74:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %53 + $rsi = COPY %57 + $rdx = COPY %61 + $rcx = COPY %59 + $r8 = COPY %73 + $r9 = COPY %74 + CALL64pcrel32 @make_ref_alilist, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit $r8, implicit $r9 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %71:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %72:gr64 = LEA64r %stack.4, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %53 + $rsi = COPY %55 + $rdx = COPY %55 + $rcx = COPY %57 + $r8 = COPY %71 + $r9 = COPY %72 + CALL64pcrel32 @make_ref_alilist, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit $r8, implicit $r9 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %69:gr64 = LEA64r %stack.1, 1, $noreg, 0, $noreg + %70:gr64 = LEA64r %stack.5, 1, $noreg, 0, $noreg + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %53 + $rsi = COPY %57 + $rdx = COPY %57 + $rcx = COPY %55 + $r8 = COPY %69 + $r9 = COPY %70 + CALL64pcrel32 @make_ref_alilist, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit $r8, implicit $r9 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %68:gr64 = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load (s64) from %ir.5, !tbaa !5) + %67:gr64 = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load (s64) from %ir.6, !tbaa !5) + %66:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load (s64) from %ir.7, !tbaa !5) + %65:gr64 = MOV64rm %stack.3, 1, $noreg, 0, $noreg :: (load (s64) from %ir.8, !tbaa !5) + %64:gr32 = MOV32rm %stack.4, 1, $noreg, 0, $noreg :: (load (s32) from %ir.9, !tbaa !9) + %63:gr32 = MOV32rm %stack.5, 1, $noreg, 0, $noreg :: (load (s32) from %ir.10, !tbaa !9) + %62:fr32 = FsFLD0SS + CMP32ri %64, 0, implicit-def $eflags + %190:fr32 = COPY %62 + %191:fr32 = COPY %62 + JCC_1 %bb.6, 14, implicit $eflags + + bb.1.BB_24: + successors: %bb.4(0x40000000), %bb.2(0x40000000) + + %89:gr32 = MOV32rr %64 + %90:gr64 = SUBREG_TO_REG 0, %89, %subreg.sub_32bit + %88:gr64 = AND64ri32 %90, 1, implicit-def $eflags + %84:gr32 = MOV32r0 implicit-def $eflags + %85:gr64 = SUBREG_TO_REG 0, %84, %subreg.sub_32bit + %86:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %87:fr32 = FsFLD0SS + CMP32ri %64, 1, implicit-def $eflags + %184:fr32 = IMPLICIT_DEF + %185:fr32 = IMPLICIT_DEF + %186:gr64_nosp = COPY %85 + %187:fr32 = COPY %86 + %188:fr32 = COPY %87 + JCC_1 %bb.4, 4, implicit $eflags + + bb.2.BB_25: + successors: %bb.9(0x80000000) + + %94:gr64 = MOV64ri 4294967294 + %95:gr64 = AND64rr %90, %94, implicit-def $eflags + %91:gr32 = MOV32r0 implicit-def $eflags + %92:gr64 = SUBREG_TO_REG 0, %91, %subreg.sub_32bit + %93:fr32 = FsFLD0SS + %192:gr64_nosp = COPY %92 + %193:fr32 = COPY %93 + %194:fr32 = COPY %93 + %195:gr64 = COPY %92 + JMP_1 %bb.9 + + bb.3.BB_26: + successors: %bb.4(0x80000000) + + %122:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %123:fr32 = ADDSSrr %110, %122, implicit $mxcsr + %184:fr32 = COPY %110 + %185:fr32 = COPY %102 + %186:gr64_nosp = COPY %97 + %187:fr32 = COPY %123 + %188:fr32 = COPY %102 + + bb.4.BB_27: + successors: %bb.6(0x40000000), %bb.5(0x40000000) + + %20:fr32 = COPY %188 + %19:fr32 = COPY %187 + %18:gr64_nosp = COPY %186 + %17:fr32 = COPY %185 + %16:fr32 = COPY %184 + CMP64ri32 %88, 0, implicit-def $eflags + %190:fr32 = COPY %17 + %191:fr32 = COPY %16 + JCC_1 %bb.6, 4, implicit $eflags + + bb.5.BB_28: + successors: %bb.14(0x40000000), %bb.15(0x40000000) + + %131:gr32 = MOV32rm %66, 4, %18, 0, $noreg :: (load (s32) from %ir.35, !tbaa !9) + %130:gr32 = MOV32rm %68, 4, %18, 0, $noreg :: (load (s32) from %ir.37, !tbaa !9) + %128:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %129:fr32 = ADDSSrr %20, %128, implicit $mxcsr + CMP32rr %131, %130, implicit-def $eflags + %189:fr32 = COPY %129 + JCC_1 %bb.15, 4, implicit $eflags + + bb.14.BB_28: + successors: %bb.15(0x80000000) + + %189:fr32 = COPY %20 + + bb.15.BB_28: + successors: %bb.6(0x80000000) + + %127:fr32 = COPY %189 + %190:fr32 = COPY %127 + %191:fr32 = COPY %19 + + bb.6.BB_29: + successors: %bb.13(0x40000000), %bb.7(0x40000000) + + %23:fr32 = COPY %191 + %22:fr32 = COPY %190 + CMP32ri %63, 0, implicit-def $eflags + %210:fr32 = COPY %22 + %211:fr32 = COPY %23 + JCC_1 %bb.13, 14, implicit $eflags + + bb.7.BB_30: + successors: %bb.11(0x40000000), %bb.8(0x40000000) + + %136:gr32 = MOV32rr %63 + %137:gr64 = SUBREG_TO_REG 0, %136, %subreg.sub_32bit + %135:gr64 = AND64ri32 %137, 1, implicit-def $eflags + %133:gr32 = MOV32r0 implicit-def $eflags + %134:gr64 = SUBREG_TO_REG 0, %133, %subreg.sub_32bit + CMP32ri %63, 1, implicit-def $eflags + %204:fr32 = IMPLICIT_DEF + %205:fr32 = IMPLICIT_DEF + %206:gr64_nosp = COPY %134 + %207:fr32 = COPY %23 + %208:fr32 = COPY %22 + JCC_1 %bb.11, 4, implicit $eflags + + bb.8.BB_31: + successors: %bb.10(0x80000000) + + %140:gr64 = MOV64ri 4294967294 + %141:gr64 = AND64rr %137, %140, implicit-def $eflags + %138:gr32 = MOV32r0 implicit-def $eflags + %139:gr64 = SUBREG_TO_REG 0, %138, %subreg.sub_32bit + %198:gr64_nosp = COPY %139 + %199:fr32 = COPY %23 + %200:fr32 = COPY %22 + %201:gr64 = COPY %139 + JMP_1 %bb.10 + + bb.9.BB_32: + successors: %bb.16(0x40000000), %bb.17(0x40000000) + + %30:gr64 = COPY %195 + %29:fr32 = COPY %194 + %28:fr32 = COPY %193 + %27:gr64_nosp = COPY %192 + %120:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %121:fr32 = ADDSSrr %28, %120, implicit $mxcsr + %119:gr32 = MOV32rm %66, 4, %27, 0, $noreg :: (load (s32) from %ir.54, !tbaa !9) + %118:gr32 = MOV32rm %68, 4, %27, 0, $noreg :: (load (s32) from %ir.56, !tbaa !9) + %116:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %117:fr32 = ADDSSrr %29, %116, implicit $mxcsr + CMP32rr %119, %118, implicit-def $eflags + %196:fr32 = COPY %117 + JCC_1 %bb.17, 4, implicit $eflags + + bb.16.BB_32: + successors: %bb.17(0x80000000) + + %196:fr32 = COPY %29 + + bb.17.BB_32: + successors: %bb.18(0x40000000), %bb.19(0x40000000) + + %115:fr32 = COPY %196 + %111:gr64_nosp = OR64ri32 %27, 1, implicit-def $eflags + %109:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %110:fr32 = ADDSSrr %121, %109, implicit $mxcsr + %107:gr32 = MOV32rm %66, 4, %111, 0, $noreg :: (load (s32) from %ir.63, !tbaa !9) + %106:gr32 = MOV32rm %68, 4, %111, 0, $noreg :: (load (s32) from %ir.65, !tbaa !9) + %103:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %104:fr32 = ADDSSrr %115, %103, implicit $mxcsr + CMP32rr %107, %106, implicit-def $eflags + %197:fr32 = COPY %104 + JCC_1 %bb.19, 4, implicit $eflags + + bb.18.BB_32: + successors: %bb.19(0x80000000) + + %197:fr32 = COPY %115 + + bb.19.BB_32: + successors: %bb.3(0x40000000), %bb.9(0x40000000) + + %102:fr32 = COPY %197 + %97:gr64 = ADD64ri32 %27, 2, implicit-def $eflags + %96:gr64 = ADD64ri32 %30, 2, implicit-def $eflags + CMP64rr %96, %95, implicit-def $eflags + %192:gr64_nosp = COPY %97 + %193:fr32 = COPY %110 + %194:fr32 = COPY %102 + %195:gr64 = COPY %96 + JCC_1 %bb.3, 4, implicit $eflags + JMP_1 %bb.9 + + bb.10.BB_33: + successors: %bb.20(0x40000000), %bb.21(0x40000000) + + %38:gr64 = COPY %201 + %37:fr32 = COPY %200 + %36:fr32 = COPY %199 + %35:gr64_nosp = COPY %198 + %166:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %167:fr32 = ADDSSrr %36, %166, implicit $mxcsr + %165:gr32 = MOV32rm %67, 4, %35, 0, $noreg :: (load (s32) from %ir.78, !tbaa !9) + %164:gr32 = MOV32rm %65, 4, %35, 0, $noreg :: (load (s32) from %ir.80, !tbaa !9) + %162:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %163:fr32 = ADDSSrr %37, %162, implicit $mxcsr + CMP32rr %165, %164, implicit-def $eflags + %202:fr32 = COPY %163 + JCC_1 %bb.21, 4, implicit $eflags + + bb.20.BB_33: + successors: %bb.21(0x80000000) + + %202:fr32 = COPY %37 + + bb.21.BB_33: + successors: %bb.22(0x40000000), %bb.23(0x40000000) + + %161:fr32 = COPY %202 + %157:gr64_nosp = OR64ri32 %35, 1, implicit-def $eflags + %155:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %156:fr32 = ADDSSrr %167, %155, implicit $mxcsr + %153:gr32 = MOV32rm %67, 4, %157, 0, $noreg :: (load (s32) from %ir.87, !tbaa !9) + %152:gr32 = MOV32rm %65, 4, %157, 0, $noreg :: (load (s32) from %ir.89, !tbaa !9) + %149:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %150:fr32 = ADDSSrr %161, %149, implicit $mxcsr + CMP32rr %153, %152, implicit-def $eflags + %203:fr32 = COPY %150 + JCC_1 %bb.23, 4, implicit $eflags + + bb.22.BB_33: + successors: %bb.23(0x80000000) + + %203:fr32 = COPY %161 + + bb.23.BB_33: + successors: %bb.10(0x40000000), %bb.11(0x40000000) + + %148:fr32 = COPY %203 + %143:gr64 = ADD64ri32 %35, 2, implicit-def $eflags + %142:gr64 = ADD64ri32 %38, 2, implicit-def $eflags + CMP64rr %142, %141, implicit-def $eflags + %198:gr64_nosp = COPY %143 + %199:fr32 = COPY %156 + %200:fr32 = COPY %148 + %201:gr64 = COPY %142 + %204:fr32 = COPY %156 + %205:fr32 = COPY %148 + %206:gr64_nosp = COPY %143 + %207:fr32 = COPY %156 + %208:fr32 = COPY %148 + JCC_1 %bb.10, 5, implicit $eflags + + bb.11.BB_34: + successors: %bb.13(0x40000000), %bb.12(0x40000000) + + %47:fr32 = COPY %208 + %46:fr32 = COPY %207 + %45:gr64_nosp = COPY %206 + %44:fr32 = COPY %205 + %43:fr32 = COPY %204 + CMP64ri32 %135, 0, implicit-def $eflags + %210:fr32 = COPY %44 + %211:fr32 = COPY %43 + JCC_1 %bb.13, 4, implicit $eflags + + bb.12.BB_35: + successors: %bb.24(0x40000000), %bb.25(0x40000000) + + %176:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %177:fr32 = ADDSSrr %46, %176, implicit $mxcsr + %175:gr32 = MOV32rm %67, 4, %45, 0, $noreg :: (load (s32) from %ir.104, !tbaa !9) + %174:gr32 = MOV32rm %65, 4, %45, 0, $noreg :: (load (s32) from %ir.106, !tbaa !9) + %172:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %173:fr32 = ADDSSrr %47, %172, implicit $mxcsr + CMP32rr %175, %174, implicit-def $eflags + %209:fr32 = COPY %173 + JCC_1 %bb.25, 4, implicit $eflags + + bb.24.BB_35: + successors: %bb.25(0x80000000) + + %209:fr32 = COPY %47 + + bb.25.BB_35: + successors: %bb.13(0x80000000) + + %171:fr32 = COPY %209 + %210:fr32 = COPY %171 + %211:fr32 = COPY %177 + + bb.13.BB_36: + %51:fr32 = COPY %211 + %50:fr32 = COPY %210 + %183:fr32 = DIVSSrr %50, %51, implicit $mxcsr + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %68 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %67 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %66 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %65 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $xmm0 = COPY %183 + RET64 implicit $xmm0 + +... +--- +name: make_ref_alilist +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr64, preferred-register: '' } + - { id: 3, class: gr64_nosp, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr32, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64_nosp, preferred-register: '' } + - { id: 10, class: gr32, preferred-register: '' } + - { id: 11, class: gr32, preferred-register: '' } + - { id: 12, class: gr32, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr8, preferred-register: '' } + - { id: 15, class: gr8, preferred-register: '' } + - { id: 16, class: gr32, preferred-register: '' } + - { id: 17, class: gr32, preferred-register: '' } + - { id: 18, class: gr32, preferred-register: '' } + - { id: 19, class: gr8, preferred-register: '' } + - { id: 20, class: gr8, preferred-register: '' } + - { id: 21, class: gr32, preferred-register: '' } + - { id: 22, class: gr32, preferred-register: '' } + - { id: 23, class: gr32, preferred-register: '' } + - { id: 24, class: gr32, preferred-register: '' } + - { id: 25, class: gr32, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr64, preferred-register: '' } + - { id: 29, class: gr64, preferred-register: '' } + - { id: 30, class: gr64, preferred-register: '' } + - { id: 31, class: gr64, preferred-register: '' } + - { id: 32, class: gr64, preferred-register: '' } + - { id: 33, class: gr32, preferred-register: '' } + - { id: 34, class: gr64, preferred-register: '' } + - { id: 35, class: gr32, preferred-register: '' } + - { id: 36, class: gr64, preferred-register: '' } + - { id: 37, class: gr32, preferred-register: '' } + - { id: 38, class: gr64, preferred-register: '' } + - { id: 39, class: gr64, preferred-register: '' } + - { id: 40, class: gr64, preferred-register: '' } + - { id: 41, class: gr64, preferred-register: '' } + - { id: 42, class: gr64, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: gr32, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: gr64, preferred-register: '' } + - { id: 47, class: gr64, preferred-register: '' } + - { id: 48, class: gr64, preferred-register: '' } + - { id: 49, class: gr64, preferred-register: '' } + - { id: 50, class: gr8, preferred-register: '' } + - { id: 51, class: gr8, preferred-register: '' } + - { id: 52, class: gr8, preferred-register: '' } + - { id: 53, class: gr8, preferred-register: '' } + - { id: 54, class: gr8, preferred-register: '' } + - { id: 55, class: gr8, preferred-register: '' } + - { id: 56, class: gr32, preferred-register: '' } + - { id: 57, class: gr64, preferred-register: '' } + - { id: 58, class: gr32, preferred-register: '' } + - { id: 59, class: gr8, preferred-register: '' } + - { id: 60, class: gr8, preferred-register: '' } + - { id: 61, class: gr8, preferred-register: '' } + - { id: 62, class: gr8, preferred-register: '' } + - { id: 63, class: gr8, preferred-register: '' } + - { id: 64, class: gr32, preferred-register: '' } + - { id: 65, class: gr64_nosp, preferred-register: '' } + - { id: 66, class: gr64_nosp, preferred-register: '' } + - { id: 67, class: gr32, preferred-register: '' } + - { id: 68, class: gr32, preferred-register: '' } + - { id: 69, class: gr8, preferred-register: '' } + - { id: 70, class: gr8, preferred-register: '' } + - { id: 71, class: gr8, preferred-register: '' } + - { id: 72, class: gr8, preferred-register: '' } + - { id: 73, class: gr32, preferred-register: '' } + - { id: 74, class: gr32, preferred-register: '' } + - { id: 75, class: gr8, preferred-register: '' } + - { id: 76, class: gr32, preferred-register: '' } + - { id: 77, class: gr64_nosp, preferred-register: '' } + - { id: 78, class: gr64_nosp, preferred-register: '' } + - { id: 79, class: gr8, preferred-register: '' } + - { id: 80, class: gr8, preferred-register: '' } + - { id: 81, class: gr8, preferred-register: '' } + - { id: 82, class: gr8, preferred-register: '' } + - { id: 83, class: gr8, preferred-register: '' } + - { id: 84, class: gr32, preferred-register: '' } + - { id: 85, class: gr8, preferred-register: '' } + - { id: 86, class: gr8, preferred-register: '' } + - { id: 87, class: gr8, preferred-register: '' } + - { id: 88, class: gr8, preferred-register: '' } + - { id: 89, class: gr8, preferred-register: '' } + - { id: 90, class: gr8, preferred-register: '' } + - { id: 91, class: gr32, preferred-register: '' } + - { id: 92, class: gr64, preferred-register: '' } + - { id: 93, class: gr32, preferred-register: '' } + - { id: 94, class: gr64_nosp, preferred-register: '' } + - { id: 95, class: gr32, preferred-register: '' } + - { id: 96, class: gr64_nosp, preferred-register: '' } + - { id: 97, class: gr8, preferred-register: '' } + - { id: 98, class: gr8, preferred-register: '' } + - { id: 99, class: gr32, preferred-register: '' } + - { id: 100, class: gr8, preferred-register: '' } + - { id: 101, class: gr32, preferred-register: '' } + - { id: 102, class: gr64, preferred-register: '' } + - { id: 103, class: gr64_nosp, preferred-register: '' } + - { id: 104, class: gr32, preferred-register: '' } + - { id: 105, class: gr32, preferred-register: '' } + - { id: 106, class: gr64_nosp, preferred-register: '' } + - { id: 107, class: gr32, preferred-register: '' } + - { id: 108, class: gr32, preferred-register: '' } + - { id: 109, class: gr32, preferred-register: '' } + - { id: 110, class: gr32, preferred-register: '' } + - { id: 111, class: gr8, preferred-register: '' } + - { id: 112, class: gr32, preferred-register: '' } + - { id: 113, class: gr32, preferred-register: '' } + - { id: 114, class: gr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%27' } + - { reg: '$rsi', virtual-reg: '%28' } + - { reg: '$rdx', virtual-reg: '%29' } + - { reg: '$rcx', virtual-reg: '%30' } + - { reg: '$r8', virtual-reg: '%31' } + - { reg: '$r9', virtual-reg: '%32' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_37: + successors: %bb.1(0x80000000) + liveins: $rdi, $rsi, $rdx, $rcx, $r8, $r9 + + %32:gr64 = COPY $r9 + %31:gr64 = COPY $r8 + %30:gr64 = COPY $rcx + %29:gr64 = COPY $rdx + %28:gr64 = COPY $rsi + %27:gr64 = COPY $rdi + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %29 + CALL64pcrel32 target-flags(x86-plt) @strlen, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %49:gr64 = COPY $rax + %47:gr64 = COPY %49 + %48:gr64 = SHL64ri %47, 2, implicit-def $eflags + %43:gr64 = MOV64ri @.str + %44:gr32 = MOV32ri 236 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %43 + $esi = COPY %44 + $rdx = COPY %48 + CALL64pcrel32 target-flags(x86-plt) @sre_malloc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit $rdx, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %46:gr64 = COPY $rax + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %29 + CALL64pcrel32 target-flags(x86-plt) @strlen, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp + %42:gr64 = COPY $rax + %40:gr64 = COPY %42 + %41:gr64 = SHL64ri %40, 2, implicit-def $eflags + %36:gr64 = MOV64ri @.str + %37:gr32 = MOV32ri 237 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %36 + $esi = COPY %37 + $rdx = COPY %41 + CALL64pcrel32 target-flags(x86-plt) @sre_malloc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit $rdx, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %39:gr64 = COPY $rax + %33:gr32 = MOV32r0 implicit-def $eflags + %34:gr64 = SUBREG_TO_REG 0, %33, %subreg.sub_32bit + %35:gr32 = MOV32r0 implicit-def $eflags + %103:gr64_nosp = COPY %34 + %104:gr32 = COPY %35 + + bb.1.BB_38: + successors: %bb.2(0x40000000), %bb.16(0x40000000) + + %4:gr32 = COPY %104 + %3:gr64_nosp = COPY %103 + %50:gr8 = MOV8rm %28, 1, %3, 0, $noreg :: (load (s8) from %ir.15, !tbaa !11) + TEST8rr %50, %50, implicit-def $eflags + JCC_1 %bb.2, 4, implicit $eflags + JMP_1 %bb.16 + + bb.16.BB_38: + successors: %bb.4(0x40000000), %bb.17(0x40000000) + + %51:gr8 = SUB8ri %50, 32, implicit-def $eflags + %105:gr32 = COPY %4 + JCC_1 %bb.4, 4, implicit $eflags + JMP_1 %bb.17 + + bb.17.BB_38: + successors: %bb.4(0x40000000), %bb.18(0x40000000) + + %52:gr8 = ADD8ri %50, -45, implicit-def dead $eflags + %53:gr8 = SUB8ri %52, 2, implicit-def $eflags + %105:gr32 = COPY %4 + JCC_1 %bb.4, 2, implicit $eflags + JMP_1 %bb.18 + + bb.18.BB_38: + successors: %bb.4(0x40000000), %bb.19(0x40000000) + + %54:gr8 = SUB8ri %50, 95, implicit-def $eflags + %105:gr32 = COPY %4 + JCC_1 %bb.4, 4, implicit $eflags + JMP_1 %bb.19 + + bb.19.BB_38: + successors: %bb.4(0x40000000), %bb.3(0x40000000) + + %55:gr8 = SUB8ri %50, 126, implicit-def $eflags + %105:gr32 = COPY %4 + JCC_1 %bb.4, 4, implicit $eflags + JMP_1 %bb.3 + + bb.2.BB_39: + successors: %bb.5(0x80000000) + + %56:gr32 = MOV32r0 implicit-def $eflags + %57:gr64 = SUBREG_TO_REG 0, %56, %subreg.sub_32bit + %58:gr32 = MOV32r0 implicit-def $eflags + %106:gr64_nosp = COPY %57 + %107:gr32 = COPY %58 + %108:gr32 = COPY %58 + %109:gr32 = COPY %58 + JMP_1 %bb.5 + + bb.3.BB_40: + successors: %bb.4(0x80000000) + + CMP32mi %27, 4, %3, 0, $noreg, 0, implicit-def $eflags :: (load (s32) from %ir.18, !tbaa !9) + %100:gr8 = SETCCr 5, implicit $eflags + %98:gr8 = AND8ri %100, 1, implicit-def $eflags + %99:gr32 = MOVZX32rr8 %98 + %96:gr64_nosp = MOVSX64rr32 %4 + MOV32mr %39, 4, %96, 0, $noreg, %99 :: (store (s32) into %ir.23, !tbaa !9) + %93:gr32 = ADD32ri %4, 1, implicit-def $eflags + %105:gr32 = COPY %93 + + bb.4.BB_41: + successors: %bb.1(0x80000000) + + %7:gr32 = COPY %105 + %102:gr64 = ADD64ri32 %3, 1, implicit-def $eflags + %103:gr64_nosp = COPY %102 + %104:gr32 = COPY %7 + JMP_1 %bb.1 + + bb.5.BB_42: + successors: %bb.15(0x40000000), %bb.20(0x40000000) + + %12:gr32 = COPY %109 + %11:gr32 = COPY %108 + %10:gr32 = COPY %107 + %9:gr64_nosp = COPY %106 + %13:gr64 = ADD64rr %29, %9, implicit-def dead $eflags + %14:gr8 = MOV8rm %29, 1, %9, 0, $noreg :: (load (s8) from %ir.31, !tbaa !11) + TEST8rr %14, %14, implicit-def $eflags + JCC_1 %bb.15, 4, implicit $eflags + JMP_1 %bb.20 + + bb.20.BB_42: + successors: %bb.10(0x40000000), %bb.21(0x40000000) + + %59:gr8 = SUB8ri %14, 32, implicit-def $eflags + %111:gr8 = COPY %14 + %112:gr32 = COPY %12 + JCC_1 %bb.10, 4, implicit $eflags + JMP_1 %bb.21 + + bb.21.BB_42: + successors: %bb.10(0x40000000), %bb.22(0x40000000) + + %60:gr8 = ADD8ri %14, -45, implicit-def dead $eflags + %61:gr8 = SUB8ri %60, 2, implicit-def $eflags + %111:gr8 = COPY %14 + %112:gr32 = COPY %12 + JCC_1 %bb.10, 2, implicit $eflags + JMP_1 %bb.22 + + bb.22.BB_42: + successors: %bb.10(0x40000000), %bb.23(0x40000000) + + %62:gr8 = SUB8ri %14, 95, implicit-def $eflags + %111:gr8 = COPY %14 + %112:gr32 = COPY %12 + JCC_1 %bb.10, 4, implicit $eflags + JMP_1 %bb.23 + + bb.23.BB_42: + successors: %bb.10(0x40000000), %bb.6(0x40000000) + + %63:gr8 = SUB8ri %14, 126, implicit-def $eflags + %111:gr8 = COPY %14 + %112:gr32 = COPY %12 + JCC_1 %bb.10, 4, implicit $eflags + JMP_1 %bb.6 + + bb.6.BB_43: + successors: %bb.10(0x40000000), %bb.7(0x40000000) + + %66:gr64_nosp = MOVSX64rr32 %10 + CMP32mi %39, 4, %66, 0, $noreg, 0, implicit-def $eflags :: (load (s32) from %ir.34, !tbaa !9) + %111:gr8 = COPY %14 + %112:gr32 = COPY %12 + JCC_1 %bb.10, 4, implicit $eflags + + bb.7.BB_44: + successors: %bb.9(0x40000000), %bb.24(0x40000000) + + %15:gr8 = MOV8rm %30, 1, %9, 0, $noreg :: (load (s8) from %ir.37, !tbaa !11) + %68:gr32 = MOV32ri -1 + %69:gr8 = SUB8ri %15, 32, implicit-def $eflags + %110:gr32 = COPY %68 + JCC_1 %bb.9, 4, implicit $eflags + JMP_1 %bb.24 + + bb.24.BB_44: + successors: %bb.9(0x40000000), %bb.25(0x40000000) + + %70:gr8 = ADD8ri %15, -45, implicit-def dead $eflags + %71:gr8 = SUB8ri %70, 2, implicit-def $eflags + %110:gr32 = COPY %68 + JCC_1 %bb.9, 2, implicit $eflags + JMP_1 %bb.25 + + bb.25.BB_44: + successors: %bb.9(0x40000000), %bb.8(0x40000000) + + %72:gr8 = SUB8ri %15, 95, implicit-def $eflags + %110:gr32 = COPY %68 + JCC_1 %bb.9, 4, implicit $eflags + JMP_1 %bb.8 + + bb.8.BB_45: + successors: %bb.9(0x80000000) + + %73:gr32 = MOV32ri 4294967295 + CMP8ri %15, 126, implicit-def $eflags + %74:gr32 = CMOV32rr %11, %73, 4, implicit $eflags + %110:gr32 = COPY %74 + + bb.9.BB_46: + successors: %bb.10(0x80000000) + + %17:gr32 = COPY %110 + %78:gr64_nosp = MOVSX64rr32 %12 + MOV32mr %46, 4, %78, 0, $noreg, %17 :: (store (s32) into %ir.43, !tbaa !9) + %76:gr32 = ADD32ri %12, 1, implicit-def $eflags + %75:gr8 = MOV8rm %13, 1, $noreg, 0, $noreg :: (load (s8) from %ir.31, !tbaa !11) + %111:gr8 = COPY %75 + %112:gr32 = COPY %76 + + bb.10.BB_47: + successors: %bb.12(0x40000000), %bb.26(0x40000000) + + %21:gr32 = COPY %112 + %20:gr8 = COPY %111 + %79:gr8 = SUB8ri %20, 32, implicit-def $eflags + %113:gr32 = COPY %10 + JCC_1 %bb.12, 4, implicit $eflags + JMP_1 %bb.26 + + bb.26.BB_47: + successors: %bb.12(0x40000000), %bb.27(0x40000000) + + %80:gr8 = ADD8ri %20, -45, implicit-def dead $eflags + %81:gr8 = SUB8ri %80, 2, implicit-def $eflags + %113:gr32 = COPY %10 + JCC_1 %bb.12, 2, implicit $eflags + JMP_1 %bb.27 + + bb.27.BB_47: + successors: %bb.12(0x40000000), %bb.28(0x40000000) + + %82:gr8 = SUB8ri %20, 95, implicit-def $eflags + %113:gr32 = COPY %10 + JCC_1 %bb.12, 4, implicit $eflags + JMP_1 %bb.28 + + bb.28.BB_47: + successors: %bb.12(0x40000000), %bb.11(0x40000000) + + %83:gr8 = SUB8ri %20, 126, implicit-def $eflags + %113:gr32 = COPY %10 + JCC_1 %bb.12, 4, implicit $eflags + JMP_1 %bb.11 + + bb.11.BB_48: + successors: %bb.12(0x80000000) + + %84:gr32 = ADD32ri %10, 1, implicit-def $eflags + %113:gr32 = COPY %84 + + bb.12.BB_49: + successors: %bb.14(0x40000000), %bb.29(0x40000000) + + %23:gr32 = COPY %113 + %85:gr8 = MOV8rm %30, 1, %9, 0, $noreg :: (load (s8) from %ir.50, !tbaa !11) + %86:gr8 = SUB8ri %85, 32, implicit-def $eflags + %114:gr32 = COPY %11 + JCC_1 %bb.14, 4, implicit $eflags + JMP_1 %bb.29 + + bb.29.BB_49: + successors: %bb.14(0x40000000), %bb.30(0x40000000) + + %87:gr8 = ADD8ri %85, -45, implicit-def dead $eflags + %88:gr8 = SUB8ri %87, 2, implicit-def $eflags + %114:gr32 = COPY %11 + JCC_1 %bb.14, 2, implicit $eflags + JMP_1 %bb.30 + + bb.30.BB_49: + successors: %bb.14(0x40000000), %bb.31(0x40000000) + + %89:gr8 = SUB8ri %85, 95, implicit-def $eflags + %114:gr32 = COPY %11 + JCC_1 %bb.14, 4, implicit $eflags + JMP_1 %bb.31 + + bb.31.BB_49: + successors: %bb.14(0x40000000), %bb.13(0x40000000) + + %90:gr8 = SUB8ri %85, 126, implicit-def $eflags + %114:gr32 = COPY %11 + JCC_1 %bb.14, 4, implicit $eflags + JMP_1 %bb.13 + + bb.13.BB_50: + successors: %bb.14(0x80000000) + + %91:gr32 = ADD32ri %11, 1, implicit-def $eflags + %114:gr32 = COPY %91 + + bb.14.BB_51: + successors: %bb.5(0x80000000) + + %25:gr32 = COPY %114 + %92:gr64 = ADD64ri32 %9, 1, implicit-def $eflags + %106:gr64_nosp = COPY %92 + %107:gr32 = COPY %23 + %108:gr32 = COPY %25 + %109:gr32 = COPY %21 + JMP_1 %bb.5 + + bb.15.BB_52: + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %39 + CALL64pcrel32 target-flags(x86-plt) @free, csr_64, implicit $rsp, implicit $ssp, implicit $rdi + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + MOV32mr %32, 1, $noreg, 0, $noreg, %12 :: (store (s32) into %ir.5, !tbaa !9) + MOV64mr %31, 1, $noreg, 0, $noreg, %46 :: (store (s64) into %ir.55, !tbaa !5) + RET64 + +... +--- +name: CompareMultAlignments +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: fr32, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: fr32, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64_nosp, preferred-register: '' } + - { id: 11, class: fr32, preferred-register: '' } + - { id: 12, class: fr32, preferred-register: '' } + - { id: 13, class: fr32, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: fr32, preferred-register: '' } + - { id: 16, class: fr32, preferred-register: '' } + - { id: 17, class: fr32, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr32, preferred-register: '' } + - { id: 23, class: gr32, preferred-register: '' } + - { id: 24, class: fr32, preferred-register: '' } + - { id: 25, class: gr32, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: fr32, preferred-register: '' } + - { id: 29, class: gr32, preferred-register: '' } + - { id: 30, class: gr64, preferred-register: '' } + - { id: 31, class: gr32, preferred-register: '' } + - { id: 32, class: gr64, preferred-register: '' } + - { id: 33, class: gr64, preferred-register: '' } + - { id: 34, class: gr64, preferred-register: '' } + - { id: 35, class: gr64, preferred-register: '' } + - { id: 36, class: gr64, preferred-register: '' } + - { id: 37, class: gr64, preferred-register: '' } + - { id: 38, class: fr32, preferred-register: '' } + - { id: 39, class: fr32, preferred-register: '' } + - { id: 40, class: gr64, preferred-register: '' } + - { id: 41, class: gr64, preferred-register: '' } + - { id: 42, class: gr64, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: fr32, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: gr64, preferred-register: '' } + - { id: 47, class: gr64, preferred-register: '' } + - { id: 48, class: gr64, preferred-register: '' } + - { id: 49, class: gr64, preferred-register: '' } + - { id: 50, class: fr32, preferred-register: '' } + - { id: 51, class: gr64, preferred-register: '' } + - { id: 52, class: fr64, preferred-register: '' } + - { id: 53, class: fr32, preferred-register: '' } + - { id: 54, class: fr64, preferred-register: '' } + - { id: 55, class: fr64, preferred-register: '' } + - { id: 56, class: fr64, preferred-register: '' } + - { id: 57, class: fr64, preferred-register: '' } + - { id: 58, class: fr64, preferred-register: '' } + - { id: 59, class: fr64, preferred-register: '' } + - { id: 60, class: fr64, preferred-register: '' } + - { id: 61, class: fr64, preferred-register: '' } + - { id: 62, class: fr32, preferred-register: '' } + - { id: 63, class: fr64, preferred-register: '' } + - { id: 64, class: fr32, preferred-register: '' } + - { id: 65, class: fr64, preferred-register: '' } + - { id: 66, class: fr64, preferred-register: '' } + - { id: 67, class: fr64, preferred-register: '' } + - { id: 68, class: fr64, preferred-register: '' } + - { id: 69, class: fr32, preferred-register: '' } + - { id: 70, class: gr64, preferred-register: '' } + - { id: 71, class: gr64, preferred-register: '' } + - { id: 72, class: fr32, preferred-register: '' } + - { id: 73, class: gr64_nosp, preferred-register: '' } + - { id: 74, class: fr32, preferred-register: '' } + - { id: 75, class: fr32, preferred-register: '' } + - { id: 76, class: fr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%18' } + - { reg: '$rsi', virtual-reg: '%20' } + - { reg: '$edx', virtual-reg: '%22' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: + - id: 0 + value: 'float -1.000000e+00' + alignment: 4 + isTargetSpecific: false + - id: 1 + value: 'double -1.000000e+00' + alignment: 8 + isTargetSpecific: false + - id: 2 + value: 'double 2.000000e+00' + alignment: 8 + isTargetSpecific: false +machineFunctionInfo: {} +body: | + bb.0.BB_53: + successors: %bb.7(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $rsi, $edx + + %22:gr32 = COPY $edx + %20:gr64 = COPY $rsi + %18:gr64 = COPY $rdi + %19:gr64 = COPY killed %18 + %21:gr64 = COPY killed %20 + %23:gr32 = COPY killed %22 + %24:fr32 = FsFLD0SS + CMP32ri %23, 0, implicit-def $eflags + %75:fr32 = COPY %24 + JCC_1 %bb.7, 14, implicit $eflags + + bb.1.BB_54: + successors: %bb.3(0x80000000) + + %31:gr32 = MOV32rr %23 + %32:gr64 = SUBREG_TO_REG 0, %31, %subreg.sub_32bit + %29:gr32 = MOV32rr %23 + %30:gr64 = SUBREG_TO_REG 0, %29, %subreg.sub_32bit + %25:gr32 = MOV32r0 implicit-def $eflags + %26:gr64 = SUBREG_TO_REG 0, %25, %subreg.sub_32bit + %27:gr64 = MOV32ri64 1 + %28:fr32 = FsFLD0SS + %70:gr64 = COPY %26 + %71:gr64 = COPY %27 + %72:fr32 = COPY %28 + JMP_1 %bb.3 + + bb.2.BB_55: + successors: %bb.7(0x40000000), %bb.3(0x40000000) + + %2:fr32 = COPY %69 + %51:gr64 = ADD64ri32 %5, 1, implicit-def $eflags + CMP64rr %33, %30, implicit-def $eflags + %70:gr64 = COPY %33 + %71:gr64 = COPY %51 + %72:fr32 = COPY %2 + %75:fr32 = COPY %2 + JCC_1 %bb.7, 4, implicit $eflags + + bb.3.BB_56: + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + %6:fr32 = COPY %72 + %5:gr64 = COPY %71 + %4:gr64 = COPY %70 + %33:gr64 = ADD64ri32 %4, 1, implicit-def $eflags + CMP64rr %33, %32, implicit-def $eflags + %69:fr32 = COPY %6 + JCC_1 %bb.2, 3, implicit $eflags + + bb.4.BB_57: + successors: %bb.5(0x80000000) + + %36:gr64 = SHL64ri %4, 3, implicit-def $eflags + %37:gr64 = ADD64rr %19, %36, implicit-def $eflags + %34:gr64 = SHL64ri %4, 3, implicit-def $eflags + %35:gr64 = ADD64rr %21, %34, implicit-def $eflags + %73:gr64_nosp = COPY %5 + %74:fr32 = COPY %6 + + bb.5.BB_58: + successors: %bb.8(0x40000000), %bb.6(0x40000000) + + %11:fr32 = COPY %74 + %10:gr64_nosp = COPY %73 + %48:gr64 = MOV64rm %37, 1, $noreg, 0, $noreg :: (load (s64) from %ir.14, !tbaa !5) + %47:gr64 = MOV64rm %19, 8, %10, 0, $noreg :: (load (s64) from %ir.19, !tbaa !5) + %46:gr64 = MOV64rm %35, 1, $noreg, 0, $noreg :: (load (s64) from %ir.15, !tbaa !5) + %45:gr64 = MOV64rm %21, 8, %10, 0, $noreg :: (load (s64) from %ir.22, !tbaa !5) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %48 + $rsi = COPY %47 + $rdx = COPY %46 + $rcx = COPY %45 + CALL64pcrel32 @ComparePairAlignments, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit-def $xmm0 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %44:fr32 = COPY $xmm0 + %38:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %39:fr32 = FsFLD0SS + UCOMISSrr %39, %44, implicit-def $eflags, implicit $mxcsr + %76:fr32 = COPY %38 + JCC_1 %bb.8, 7, implicit $eflags + + bb.6.BB_59: + successors: %bb.2(0x40000000), %bb.5(0x40000000) + + %50:fr32 = ADDSSrr %11, %44, implicit $mxcsr + %49:gr64 = ADD64ri32 %10, 1, implicit-def $eflags + CMP64rr %49, %30, implicit-def $eflags + %69:fr32 = COPY %50 + %73:gr64_nosp = COPY %49 + %74:fr32 = COPY %50 + JCC_1 %bb.2, 4, implicit $eflags + JMP_1 %bb.5 + + bb.7.BB_60: + successors: %bb.8(0x80000000) + + %15:fr32 = COPY %75 + %68:fr64 = CVTSS2SDrr %15, implicit $mxcsr + %66:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.2, $noreg + %67:fr64 = MULSDrr %68, %66, implicit $mxcsr + %64:fr32 = CVTSI2SSrr %23, implicit $mxcsr + %63:fr64 = CVTSS2SDrr %64, implicit $mxcsr + %60:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.1, $noreg + %61:fr64 = ADDSDrr %63, %60, implicit $mxcsr + %59:fr64 = MULSDrr %61, %63, implicit $mxcsr + %56:fr64 = DIVSDrr %67, %59, implicit $mxcsr + %53:fr32 = CVTSD2SSrr %56, implicit $mxcsr + %76:fr32 = COPY %53 + + bb.8.BB_61: + %17:fr32 = COPY %76 + $xmm0 = COPY %17 + RET64 implicit $xmm0 + +... +--- +name: CompareRefMultAlignments +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: fr32, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: gr64, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: fr32, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64_nosp, preferred-register: '' } + - { id: 11, class: fr32, preferred-register: '' } + - { id: 12, class: fr32, preferred-register: '' } + - { id: 13, class: fr32, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: fr32, preferred-register: '' } + - { id: 16, class: fr32, preferred-register: '' } + - { id: 17, class: fr32, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr32, preferred-register: '' } + - { id: 25, class: gr32, preferred-register: '' } + - { id: 26, class: fr32, preferred-register: '' } + - { id: 27, class: gr32, preferred-register: '' } + - { id: 28, class: gr64, preferred-register: '' } + - { id: 29, class: gr64, preferred-register: '' } + - { id: 30, class: fr32, preferred-register: '' } + - { id: 31, class: gr32, preferred-register: '' } + - { id: 32, class: gr64, preferred-register: '' } + - { id: 33, class: gr32, preferred-register: '' } + - { id: 34, class: gr64, preferred-register: '' } + - { id: 35, class: gr64, preferred-register: '' } + - { id: 36, class: gr64, preferred-register: '' } + - { id: 37, class: gr64, preferred-register: '' } + - { id: 38, class: gr64, preferred-register: '' } + - { id: 39, class: gr64, preferred-register: '' } + - { id: 40, class: fr32, preferred-register: '' } + - { id: 41, class: fr32, preferred-register: '' } + - { id: 42, class: gr64, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: gr64, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: fr32, preferred-register: '' } + - { id: 47, class: gr64, preferred-register: '' } + - { id: 48, class: gr64, preferred-register: '' } + - { id: 49, class: gr64, preferred-register: '' } + - { id: 50, class: gr64, preferred-register: '' } + - { id: 51, class: gr64, preferred-register: '' } + - { id: 52, class: fr32, preferred-register: '' } + - { id: 53, class: gr64, preferred-register: '' } + - { id: 54, class: fr64, preferred-register: '' } + - { id: 55, class: fr32, preferred-register: '' } + - { id: 56, class: fr64, preferred-register: '' } + - { id: 57, class: fr64, preferred-register: '' } + - { id: 58, class: fr64, preferred-register: '' } + - { id: 59, class: fr64, preferred-register: '' } + - { id: 60, class: fr64, preferred-register: '' } + - { id: 61, class: fr64, preferred-register: '' } + - { id: 62, class: fr64, preferred-register: '' } + - { id: 63, class: fr64, preferred-register: '' } + - { id: 64, class: fr32, preferred-register: '' } + - { id: 65, class: fr64, preferred-register: '' } + - { id: 66, class: fr32, preferred-register: '' } + - { id: 67, class: fr64, preferred-register: '' } + - { id: 68, class: fr64, preferred-register: '' } + - { id: 69, class: fr64, preferred-register: '' } + - { id: 70, class: fr64, preferred-register: '' } + - { id: 71, class: fr32, preferred-register: '' } + - { id: 72, class: gr64, preferred-register: '' } + - { id: 73, class: gr64, preferred-register: '' } + - { id: 74, class: fr32, preferred-register: '' } + - { id: 75, class: gr64_nosp, preferred-register: '' } + - { id: 76, class: fr32, preferred-register: '' } + - { id: 77, class: fr32, preferred-register: '' } + - { id: 78, class: fr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%18' } + - { reg: '$rsi', virtual-reg: '%20' } + - { reg: '$rdx', virtual-reg: '%22' } + - { reg: '$ecx', virtual-reg: '%24' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: + - id: 0 + value: 'float -1.000000e+00' + alignment: 4 + isTargetSpecific: false + - id: 1 + value: 'double -1.000000e+00' + alignment: 8 + isTargetSpecific: false + - id: 2 + value: 'double 2.000000e+00' + alignment: 8 + isTargetSpecific: false +machineFunctionInfo: {} +body: | + bb.0.BB_62: + successors: %bb.7(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $rsi, $rdx, $ecx + + %24:gr32 = COPY $ecx + %22:gr64 = COPY $rdx + %20:gr64 = COPY $rsi + %18:gr64 = COPY $rdi + %19:gr64 = COPY killed %18 + %21:gr64 = COPY killed %20 + %23:gr64 = COPY killed %22 + %25:gr32 = COPY killed %24 + %26:fr32 = FsFLD0SS + CMP32ri %25, 0, implicit-def $eflags + %77:fr32 = COPY %26 + JCC_1 %bb.7, 14, implicit $eflags + + bb.1.BB_63: + successors: %bb.3(0x80000000) + + %33:gr32 = MOV32rr %25 + %34:gr64 = SUBREG_TO_REG 0, %33, %subreg.sub_32bit + %31:gr32 = MOV32rr %25 + %32:gr64 = SUBREG_TO_REG 0, %31, %subreg.sub_32bit + %27:gr32 = MOV32r0 implicit-def $eflags + %28:gr64 = SUBREG_TO_REG 0, %27, %subreg.sub_32bit + %29:gr64 = MOV32ri64 1 + %30:fr32 = FsFLD0SS + %72:gr64 = COPY %28 + %73:gr64 = COPY %29 + %74:fr32 = COPY %30 + JMP_1 %bb.3 + + bb.2.BB_64: + successors: %bb.7(0x40000000), %bb.3(0x40000000) + + %2:fr32 = COPY %71 + %53:gr64 = ADD64ri32 %5, 1, implicit-def $eflags + CMP64rr %35, %32, implicit-def $eflags + %72:gr64 = COPY %35 + %73:gr64 = COPY %53 + %74:fr32 = COPY %2 + %77:fr32 = COPY %2 + JCC_1 %bb.7, 4, implicit $eflags + + bb.3.BB_65: + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + %6:fr32 = COPY %74 + %5:gr64 = COPY %73 + %4:gr64 = COPY %72 + %35:gr64 = ADD64ri32 %4, 1, implicit-def $eflags + CMP64rr %35, %34, implicit-def $eflags + %71:fr32 = COPY %6 + JCC_1 %bb.2, 3, implicit $eflags + + bb.4.BB_66: + successors: %bb.5(0x80000000) + + %38:gr64 = SHL64ri %4, 3, implicit-def $eflags + %39:gr64 = ADD64rr %21, %38, implicit-def $eflags + %36:gr64 = SHL64ri %4, 3, implicit-def $eflags + %37:gr64 = ADD64rr %23, %36, implicit-def $eflags + %75:gr64_nosp = COPY %5 + %76:fr32 = COPY %6 + + bb.5.BB_67: + successors: %bb.8(0x40000000), %bb.6(0x40000000) + + %11:fr32 = COPY %76 + %10:gr64_nosp = COPY %75 + %50:gr64 = MOV64rm %39, 1, $noreg, 0, $noreg :: (load (s64) from %ir.15, !tbaa !5) + %49:gr64 = MOV64rm %21, 8, %10, 0, $noreg :: (load (s64) from %ir.20, !tbaa !5) + %48:gr64 = MOV64rm %37, 1, $noreg, 0, $noreg :: (load (s64) from %ir.16, !tbaa !5) + %47:gr64 = MOV64rm %23, 8, %10, 0, $noreg :: (load (s64) from %ir.23, !tbaa !5) + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %19 + $rsi = COPY %50 + $rdx = COPY %49 + $rcx = COPY %48 + $r8 = COPY %47 + CALL64pcrel32 @CompareRefPairAlignments, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit $rdx, implicit $rcx, implicit $r8, implicit-def $xmm0 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %46:fr32 = COPY $xmm0 + %40:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + %41:fr32 = FsFLD0SS + UCOMISSrr %41, %46, implicit-def $eflags, implicit $mxcsr + %78:fr32 = COPY %40 + JCC_1 %bb.8, 7, implicit $eflags + + bb.6.BB_68: + successors: %bb.2(0x40000000), %bb.5(0x40000000) + + %52:fr32 = ADDSSrr %11, %46, implicit $mxcsr + %51:gr64 = ADD64ri32 %10, 1, implicit-def $eflags + CMP64rr %51, %32, implicit-def $eflags + %71:fr32 = COPY %52 + %75:gr64_nosp = COPY %51 + %76:fr32 = COPY %52 + JCC_1 %bb.2, 4, implicit $eflags + JMP_1 %bb.5 + + bb.7.BB_69: + successors: %bb.8(0x80000000) + + %15:fr32 = COPY %77 + %70:fr64 = CVTSS2SDrr %15, implicit $mxcsr + %68:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.2, $noreg + %69:fr64 = MULSDrr %70, %68, implicit $mxcsr + %66:fr32 = CVTSI2SSrr %25, implicit $mxcsr + %65:fr64 = CVTSS2SDrr %66, implicit $mxcsr + %62:fr64 = MOVSDrm_alt $rip, 1, $noreg, %const.1, $noreg + %63:fr64 = ADDSDrr %65, %62, implicit $mxcsr + %61:fr64 = MULSDrr %63, %65, implicit $mxcsr + %58:fr64 = DIVSDrr %69, %61, implicit $mxcsr + %55:fr32 = CVTSD2SSrr %58, implicit $mxcsr + %78:fr32 = COPY %55 + + bb.8.BB_70: + %17:fr32 = COPY %78 + $xmm0 = COPY %17 + RET64 implicit $xmm0 + +... +--- +name: PairwiseIdentity +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr8, preferred-register: '' } + - { id: 1, class: gr64_nosp, preferred-register: '' } + - { id: 2, class: gr8, preferred-register: '' } + - { id: 3, class: gr32, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr32, preferred-register: '' } + - { id: 6, class: gr8, preferred-register: '' } + - { id: 7, class: gr32, preferred-register: '' } + - { id: 8, class: gr32, preferred-register: '' } + - { id: 9, class: gr32, preferred-register: '' } + - { id: 10, class: gr32, preferred-register: '' } + - { id: 11, class: gr32, preferred-register: '' } + - { id: 12, class: gr32, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr8, preferred-register: '' } + - { id: 15, class: gr32, preferred-register: '' } + - { id: 16, class: gr32, preferred-register: '' } + - { id: 17, class: gr32, preferred-register: '' } + - { id: 18, class: gr32, preferred-register: '' } + - { id: 19, class: fr32, preferred-register: '' } + - { id: 20, class: fr32, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr32, preferred-register: '' } + - { id: 26, class: gr32, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr8, preferred-register: '' } + - { id: 29, class: gr8, preferred-register: '' } + - { id: 30, class: gr8, preferred-register: '' } + - { id: 31, class: gr8, preferred-register: '' } + - { id: 32, class: gr8, preferred-register: '' } + - { id: 33, class: gr8, preferred-register: '' } + - { id: 34, class: gr8, preferred-register: '' } + - { id: 35, class: gr32, preferred-register: '' } + - { id: 36, class: gr32, preferred-register: '' } + - { id: 37, class: gr8, preferred-register: '' } + - { id: 38, class: gr8, preferred-register: '' } + - { id: 39, class: gr32, preferred-register: '' } + - { id: 40, class: gr8, preferred-register: '' } + - { id: 41, class: gr32, preferred-register: '' } + - { id: 42, class: gr8, preferred-register: '' } + - { id: 43, class: gr8, preferred-register: '' } + - { id: 44, class: gr8, preferred-register: '' } + - { id: 45, class: gr8, preferred-register: '' } + - { id: 46, class: gr8, preferred-register: '' } + - { id: 47, class: gr32, preferred-register: '' } + - { id: 48, class: gr8, preferred-register: '' } + - { id: 49, class: gr64, preferred-register: '' } + - { id: 50, class: fr32, preferred-register: '' } + - { id: 51, class: gr32, preferred-register: '' } + - { id: 52, class: fr32, preferred-register: '' } + - { id: 53, class: fr32, preferred-register: '' } + - { id: 54, class: fr32, preferred-register: '' } + - { id: 55, class: fr32, preferred-register: '' } + - { id: 56, class: fr32, preferred-register: '' } + - { id: 57, class: gr64_nosp, preferred-register: '' } + - { id: 58, class: gr8, preferred-register: '' } + - { id: 59, class: gr32, preferred-register: '' } + - { id: 60, class: gr32, preferred-register: '' } + - { id: 61, class: gr32, preferred-register: '' } + - { id: 62, class: gr32, preferred-register: '' } + - { id: 63, class: gr32, preferred-register: '' } + - { id: 64, class: gr32, preferred-register: '' } + - { id: 65, class: gr32, preferred-register: '' } + - { id: 66, class: gr32, preferred-register: '' } + - { id: 67, class: gr32, preferred-register: '' } + - { id: 68, class: fr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%21' } + - { reg: '$rsi', virtual-reg: '%23' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} +body: | + bb.0.BB_71: + successors: %bb.7(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $rsi + + %23:gr64 = COPY $rsi + %21:gr64 = COPY $rdi + %22:gr64 = COPY killed %21 + %24:gr64 = COPY killed %23 + %28:gr8 = MOV8rm %22, 1, $noreg, 0, $noreg :: (load (s8) from %ir.0, !tbaa !11) + %25:gr32 = MOV32r0 implicit-def $eflags + %26:gr32 = MOV32r0 implicit-def $eflags + %27:gr64 = SUBREG_TO_REG 0, %26, %subreg.sub_32bit + CMP8ri %28, 0, implicit-def $eflags + %57:gr64_nosp = COPY %27 + %58:gr8 = COPY %28 + %59:gr32 = COPY %25 + %60:gr32 = COPY %25 + %61:gr32 = COPY %25 + %65:gr32 = COPY %25 + %66:gr32 = COPY %25 + %67:gr32 = COPY %25 + JCC_1 %bb.7, 4, implicit $eflags + + bb.1.BB_72: + successors: %bb.7(0x40000000), %bb.2(0x40000000) + + %5:gr32 = COPY %61 + %4:gr32 = COPY %60 + %3:gr32 = COPY %59 + %2:gr8 = COPY %58 + %1:gr64_nosp = COPY %57 + %29:gr8 = MOV8rm %24, 1, %1, 0, $noreg :: (load (s8) from %ir.9, !tbaa !11) + CMP8ri %29, 0, implicit-def $eflags + %65:gr32 = COPY %5 + %66:gr32 = COPY %4 + %67:gr32 = COPY %3 + JCC_1 %bb.7, 4, implicit $eflags + + bb.2.BB_73: + successors: %bb.4(0x40000000), %bb.10(0x40000000) + + %30:gr8 = SUB8ri %2, 32, implicit-def $eflags + %62:gr32 = COPY %5 + %63:gr32 = COPY %4 + JCC_1 %bb.4, 4, implicit $eflags + JMP_1 %bb.10 + + bb.10.BB_73: + successors: %bb.4(0x40000000), %bb.11(0x40000000) + + %31:gr8 = ADD8ri %2, -45, implicit-def dead $eflags + %32:gr8 = SUB8ri %31, 2, implicit-def $eflags + %62:gr32 = COPY %5 + %63:gr32 = COPY %4 + JCC_1 %bb.4, 2, implicit $eflags + JMP_1 %bb.11 + + bb.11.BB_73: + successors: %bb.4(0x40000000), %bb.12(0x40000000) + + %33:gr8 = SUB8ri %2, 95, implicit-def $eflags + %62:gr32 = COPY %5 + %63:gr32 = COPY %4 + JCC_1 %bb.4, 4, implicit $eflags + JMP_1 %bb.12 + + bb.12.BB_73: + successors: %bb.4(0x40000000), %bb.3(0x40000000) + + %34:gr8 = SUB8ri %2, 126, implicit-def $eflags + %62:gr32 = COPY %5 + %63:gr32 = COPY %4 + JCC_1 %bb.4, 4, implicit $eflags + JMP_1 %bb.3 + + bb.3.BB_74: + successors: %bb.4(0x80000000) + + %41:gr32 = ADD32ri %4, 1, implicit-def $eflags + CMP8rr %2, %29, implicit-def $eflags + %40:gr8 = SETCCr 4, implicit $eflags + %38:gr8 = AND8ri %40, 1, implicit-def $eflags + %39:gr32 = MOVZX32rr8 %38 + %36:gr32 = ADD32rr %5, %39, implicit-def $eflags + %62:gr32 = COPY %36 + %63:gr32 = COPY %41 + + bb.4.BB_75: + successors: %bb.6(0x40000000), %bb.13(0x40000000) + + %10:gr32 = COPY %63 + %9:gr32 = COPY %62 + %42:gr8 = SUB8ri %29, 32, implicit-def $eflags + %64:gr32 = COPY %3 + JCC_1 %bb.6, 4, implicit $eflags + JMP_1 %bb.13 + + bb.13.BB_75: + successors: %bb.6(0x40000000), %bb.14(0x40000000) + + %43:gr8 = ADD8ri %29, -45, implicit-def dead $eflags + %44:gr8 = SUB8ri %43, 2, implicit-def $eflags + %64:gr32 = COPY %3 + JCC_1 %bb.6, 2, implicit $eflags + JMP_1 %bb.14 + + bb.14.BB_75: + successors: %bb.6(0x40000000), %bb.15(0x40000000) + + %45:gr8 = SUB8ri %29, 95, implicit-def $eflags + %64:gr32 = COPY %3 + JCC_1 %bb.6, 4, implicit $eflags + JMP_1 %bb.15 + + bb.15.BB_75: + successors: %bb.6(0x40000000), %bb.5(0x40000000) + + %46:gr8 = SUB8ri %29, 126, implicit-def $eflags + %64:gr32 = COPY %3 + JCC_1 %bb.6, 4, implicit $eflags + JMP_1 %bb.5 + + bb.5.BB_76: + successors: %bb.6(0x80000000) + + %47:gr32 = ADD32ri %3, 1, implicit-def $eflags + %64:gr32 = COPY %47 + + bb.6.BB_77: + successors: %bb.1(0x40000000), %bb.7(0x40000000) + + %12:gr32 = COPY %64 + %49:gr64 = ADD64ri32 %1, 1, implicit-def $eflags + %48:gr8 = MOV8rm %22, 1, %1, 1, $noreg :: (load (s8) from %ir.21, !tbaa !11) + CMP8ri %48, 0, implicit-def $eflags + %57:gr64_nosp = COPY %49 + %58:gr8 = COPY %48 + %59:gr32 = COPY %12 + %60:gr32 = COPY %10 + %61:gr32 = COPY %9 + %65:gr32 = COPY %9 + %66:gr32 = COPY %10 + %67:gr32 = COPY %12 + JCC_1 %bb.1, 5, implicit $eflags + + bb.7.BB_78: + successors: %bb.9(0x40000000), %bb.8(0x40000000) + + %17:gr32 = COPY %67 + %16:gr32 = COPY %66 + %15:gr32 = COPY %65 + CMP32rr %17, %16, implicit-def $eflags + %51:gr32 = CMOV32rr %16, %17, 12, implicit $eflags + %50:fr32 = FsFLD0SS + CMP32ri %51, 0, implicit-def $eflags + %68:fr32 = COPY %50 + JCC_1 %bb.9, 4, implicit $eflags + + bb.8.BB_79: + successors: %bb.9(0x80000000) + + %56:fr32 = CVTSI2SSrr %15, implicit $mxcsr + %55:fr32 = CVTSI2SSrr %51, implicit $mxcsr + %54:fr32 = DIVSSrr %56, %55, implicit $mxcsr + %68:fr32 = COPY %54 + + bb.9.BB_80: + %20:fr32 = COPY %68 + $xmm0 = COPY %20 + RET64 implicit $xmm0 + +... +--- +name: AlignmentIdentityBySampling +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: fr64, preferred-register: '' } + - { id: 1, class: fr32, preferred-register: '' } + - { id: 2, class: gr32, preferred-register: '' } + - { id: 3, class: gr32, preferred-register: '' } + - { id: 4, class: gr32, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr8, preferred-register: '' } + - { id: 8, class: gr64_nosp, preferred-register: '' } + - { id: 9, class: gr8, preferred-register: '' } + - { id: 10, class: gr32, preferred-register: '' } + - { id: 11, class: gr32, preferred-register: '' } + - { id: 12, class: gr32, preferred-register: '' } + - { id: 13, class: gr8, preferred-register: '' } + - { id: 14, class: gr32, preferred-register: '' } + - { id: 15, class: gr32, preferred-register: '' } + - { id: 16, class: gr32, preferred-register: '' } + - { id: 17, class: gr32, preferred-register: '' } + - { id: 18, class: gr32, preferred-register: '' } + - { id: 19, class: gr32, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr8, preferred-register: '' } + - { id: 22, class: gr32, preferred-register: '' } + - { id: 23, class: gr32, preferred-register: '' } + - { id: 24, class: gr32, preferred-register: '' } + - { id: 25, class: gr32, preferred-register: '' } + - { id: 26, class: fr32, preferred-register: '' } + - { id: 27, class: fr32, preferred-register: '' } + - { id: 28, class: fr32, preferred-register: '' } + - { id: 29, class: gr32, preferred-register: '' } + - { id: 30, class: fr32, preferred-register: '' } + - { id: 31, class: fr32, preferred-register: '' } + - { id: 32, class: fr32, preferred-register: '' } + - { id: 33, class: gr64, preferred-register: '' } + - { id: 34, class: gr64, preferred-register: '' } + - { id: 35, class: gr32, preferred-register: '' } + - { id: 36, class: gr32, preferred-register: '' } + - { id: 37, class: gr32, preferred-register: '' } + - { id: 38, class: gr32, preferred-register: '' } + - { id: 39, class: gr32, preferred-register: '' } + - { id: 40, class: gr32, preferred-register: '' } + - { id: 41, class: fr32, preferred-register: '' } + - { id: 42, class: fr32, preferred-register: '' } + - { id: 43, class: fr32, preferred-register: '' } + - { id: 44, class: gr32, preferred-register: '' } + - { id: 45, class: fr64, preferred-register: '' } + - { id: 46, class: fr64, preferred-register: '' } + - { id: 47, class: gr32, preferred-register: '' } + - { id: 48, class: fr64, preferred-register: '' } + - { id: 49, class: fr64, preferred-register: '' } + - { id: 50, class: fr64, preferred-register: '' } + - { id: 51, class: fr64, preferred-register: '' } + - { id: 52, class: gr32, preferred-register: '' } + - { id: 53, class: fr64, preferred-register: '' } + - { id: 54, class: fr64, preferred-register: '' } + - { id: 55, class: fr64, preferred-register: '' } + - { id: 56, class: gr32, preferred-register: '' } + - { id: 57, class: gr32, preferred-register: '' } + - { id: 58, class: gr64, preferred-register: '' } + - { id: 59, class: gr8, preferred-register: '' } + - { id: 60, class: gr64_nosp, preferred-register: '' } + - { id: 61, class: gr64, preferred-register: '' } + - { id: 62, class: gr64_nosp, preferred-register: '' } + - { id: 63, class: gr64_nosp, preferred-register: '' } + - { id: 64, class: gr64, preferred-register: '' } + - { id: 65, class: gr64_nosp, preferred-register: '' } + - { id: 66, class: gr8, preferred-register: '' } + - { id: 67, class: gr8, preferred-register: '' } + - { id: 68, class: gr8, preferred-register: '' } + - { id: 69, class: gr8, preferred-register: '' } + - { id: 70, class: gr8, preferred-register: '' } + - { id: 71, class: gr8, preferred-register: '' } + - { id: 72, class: gr32, preferred-register: '' } + - { id: 73, class: gr32, preferred-register: '' } + - { id: 74, class: gr8, preferred-register: '' } + - { id: 75, class: gr8, preferred-register: '' } + - { id: 76, class: gr32, preferred-register: '' } + - { id: 77, class: gr8, preferred-register: '' } + - { id: 78, class: gr32, preferred-register: '' } + - { id: 79, class: gr8, preferred-register: '' } + - { id: 80, class: gr8, preferred-register: '' } + - { id: 81, class: gr8, preferred-register: '' } + - { id: 82, class: gr8, preferred-register: '' } + - { id: 83, class: gr8, preferred-register: '' } + - { id: 84, class: gr32, preferred-register: '' } + - { id: 85, class: gr8, preferred-register: '' } + - { id: 86, class: gr64, preferred-register: '' } + - { id: 87, class: fr32, preferred-register: '' } + - { id: 88, class: gr32, preferred-register: '' } + - { id: 89, class: fr32, preferred-register: '' } + - { id: 90, class: fr32, preferred-register: '' } + - { id: 91, class: fr32, preferred-register: '' } + - { id: 92, class: fr32, preferred-register: '' } + - { id: 93, class: fr32, preferred-register: '' } + - { id: 94, class: gr32, preferred-register: '' } + - { id: 95, class: fr32, preferred-register: '' } + - { id: 96, class: fr32, preferred-register: '' } + - { id: 97, class: fr32, preferred-register: '' } + - { id: 98, class: fr32, preferred-register: '' } + - { id: 99, class: fr32, preferred-register: '' } + - { id: 100, class: gr32, preferred-register: '' } + - { id: 101, class: gr64_nosp, preferred-register: '' } + - { id: 102, class: gr8, preferred-register: '' } + - { id: 103, class: gr32, preferred-register: '' } + - { id: 104, class: gr32, preferred-register: '' } + - { id: 105, class: gr32, preferred-register: '' } + - { id: 106, class: gr32, preferred-register: '' } + - { id: 107, class: gr32, preferred-register: '' } + - { id: 108, class: gr32, preferred-register: '' } + - { id: 109, class: gr32, preferred-register: '' } + - { id: 110, class: gr32, preferred-register: '' } + - { id: 111, class: gr32, preferred-register: '' } + - { id: 112, class: fr32, preferred-register: '' } + - { id: 113, class: fr32, preferred-register: '' } + - { id: 114, class: fr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%33' } + - { reg: '$esi', virtual-reg: '%35' } + - { reg: '$edx', virtual-reg: '%37' } + - { reg: '$ecx', virtual-reg: '%39' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: + - id: 0 + value: 'float 1.000000e+00' + alignment: 4 + isTargetSpecific: false +machineFunctionInfo: {} +body: | + bb.0.BB_81: + successors: %bb.16(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $esi, $edx, $ecx + + %39:gr32 = COPY $ecx + %37:gr32 = COPY $edx + %35:gr32 = COPY $esi + %33:gr64 = COPY $rdi + %34:gr64 = COPY killed %33 + %36:gr32 = COPY killed %35 + %38:gr32 = COPY killed %37 + %40:gr32 = COPY killed %39 + %41:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + CMP32ri %38, 2, implicit-def $eflags + %114:fr32 = COPY %41 + JCC_1 %bb.16, 12, implicit $eflags + + bb.1.BB_82: + successors: %bb.15(0x40000000), %bb.2(0x40000000) + + %42:fr32 = FsFLD0SS + CMP32ri %40, 0, implicit-def $eflags + %113:fr32 = COPY %42 + JCC_1 %bb.15, 14, implicit $eflags + + bb.2.BB_83: + successors: %bb.3(0x80000000) + + %45:fr64 = CVTSI2SDrr %38 + %43:fr32 = FsFLD0SS + %44:gr32 = MOV32r0 implicit-def $eflags + %99:fr32 = COPY %43 + %100:gr32 = COPY %44 + + bb.3.BB_84: + successors: %bb.4(0x80000000) + + %2:gr32 = COPY %100 + %1:fr32 = COPY %99 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 target-flags(x86-plt) @sre_random, csr_64, implicit $rsp, implicit $ssp, implicit-def $xmm0 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %50:fr64 = COPY $xmm0 + %49:fr64 = MULSDrr %50, %45, implicit $mxcsr + %47:gr32 = CVTTSD2SIrr %49, implicit $mxcsr + + bb.4.BB_85: + successors: %bb.4(0x40000000), %bb.5(0x40000000) + + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 target-flags(x86-plt) @sre_random, csr_64, implicit $rsp, implicit $ssp, implicit-def $xmm0 + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %55:fr64 = COPY $xmm0 + %54:fr64 = MULSDrr %55, %45, implicit $mxcsr + %52:gr32 = CVTTSD2SIrr %54, implicit $mxcsr + CMP32rr %52, %47, implicit-def $eflags + JCC_1 %bb.4, 4, implicit $eflags + + bb.5.BB_86: + successors: %bb.12(0x40000000), %bb.6(0x40000000) + + %65:gr64_nosp = MOVSX64rr32 %47 + %64:gr64 = MOV64rm %34, 8, %65, 0, $noreg :: (load (s64) from %ir.17, !tbaa !5) + %62:gr64_nosp = MOVSX64rr32 %52 + %61:gr64 = MOV64rm %34, 8, %62, 0, $noreg :: (load (s64) from %ir.20, !tbaa !5) + %59:gr8 = MOV8rm %64, 1, $noreg, 0, $noreg :: (load (s8) from %ir.18, !tbaa !11) + %56:gr32 = MOV32r0 implicit-def $eflags + %57:gr32 = MOV32r0 implicit-def $eflags + %58:gr64 = SUBREG_TO_REG 0, %57, %subreg.sub_32bit + CMP8ri %59, 0, implicit-def $eflags + %101:gr64_nosp = COPY %58 + %102:gr8 = COPY %59 + %103:gr32 = COPY %56 + %104:gr32 = COPY %56 + %105:gr32 = COPY %56 + %109:gr32 = COPY %56 + %110:gr32 = COPY %56 + %111:gr32 = COPY %56 + JCC_1 %bb.12, 4, implicit $eflags + + bb.6.BB_87: + successors: %bb.12(0x40000000), %bb.7(0x40000000) + + %12:gr32 = COPY %105 + %11:gr32 = COPY %104 + %10:gr32 = COPY %103 + %9:gr8 = COPY %102 + %8:gr64_nosp = COPY %101 + %66:gr8 = MOV8rm %61, 1, %8, 0, $noreg :: (load (s8) from %ir.29, !tbaa !11) + CMP8ri %66, 0, implicit-def $eflags + %109:gr32 = COPY %12 + %110:gr32 = COPY %11 + %111:gr32 = COPY %10 + JCC_1 %bb.12, 4, implicit $eflags + + bb.7.BB_88: + successors: %bb.9(0x40000000), %bb.17(0x40000000) + + %67:gr8 = SUB8ri %9, 32, implicit-def $eflags + %106:gr32 = COPY %12 + %107:gr32 = COPY %11 + JCC_1 %bb.9, 4, implicit $eflags + JMP_1 %bb.17 + + bb.17.BB_88: + successors: %bb.9(0x40000000), %bb.18(0x40000000) + + %68:gr8 = ADD8ri %9, -45, implicit-def dead $eflags + %69:gr8 = SUB8ri %68, 2, implicit-def $eflags + %106:gr32 = COPY %12 + %107:gr32 = COPY %11 + JCC_1 %bb.9, 2, implicit $eflags + JMP_1 %bb.18 + + bb.18.BB_88: + successors: %bb.9(0x40000000), %bb.19(0x40000000) + + %70:gr8 = SUB8ri %9, 95, implicit-def $eflags + %106:gr32 = COPY %12 + %107:gr32 = COPY %11 + JCC_1 %bb.9, 4, implicit $eflags + JMP_1 %bb.19 + + bb.19.BB_88: + successors: %bb.9(0x40000000), %bb.8(0x40000000) + + %71:gr8 = SUB8ri %9, 126, implicit-def $eflags + %106:gr32 = COPY %12 + %107:gr32 = COPY %11 + JCC_1 %bb.9, 4, implicit $eflags + JMP_1 %bb.8 + + bb.8.BB_89: + successors: %bb.9(0x80000000) + + %78:gr32 = ADD32ri %11, 1, implicit-def $eflags + CMP8rr %9, %66, implicit-def $eflags + %77:gr8 = SETCCr 4, implicit $eflags + %75:gr8 = AND8ri %77, 1, implicit-def $eflags + %76:gr32 = MOVZX32rr8 %75 + %73:gr32 = ADD32rr %12, %76, implicit-def $eflags + %106:gr32 = COPY %73 + %107:gr32 = COPY %78 + + bb.9.BB_90: + successors: %bb.11(0x40000000), %bb.20(0x40000000) + + %17:gr32 = COPY %107 + %16:gr32 = COPY %106 + %79:gr8 = SUB8ri %66, 32, implicit-def $eflags + %108:gr32 = COPY %10 + JCC_1 %bb.11, 4, implicit $eflags + JMP_1 %bb.20 + + bb.20.BB_90: + successors: %bb.11(0x40000000), %bb.21(0x40000000) + + %80:gr8 = ADD8ri %66, -45, implicit-def dead $eflags + %81:gr8 = SUB8ri %80, 2, implicit-def $eflags + %108:gr32 = COPY %10 + JCC_1 %bb.11, 2, implicit $eflags + JMP_1 %bb.21 + + bb.21.BB_90: + successors: %bb.11(0x40000000), %bb.22(0x40000000) + + %82:gr8 = SUB8ri %66, 95, implicit-def $eflags + %108:gr32 = COPY %10 + JCC_1 %bb.11, 4, implicit $eflags + JMP_1 %bb.22 + + bb.22.BB_90: + successors: %bb.11(0x40000000), %bb.10(0x40000000) + + %83:gr8 = SUB8ri %66, 126, implicit-def $eflags + %108:gr32 = COPY %10 + JCC_1 %bb.11, 4, implicit $eflags + JMP_1 %bb.10 + + bb.10.BB_91: + successors: %bb.11(0x80000000) + + %84:gr32 = ADD32ri %10, 1, implicit-def $eflags + %108:gr32 = COPY %84 + + bb.11.BB_92: + successors: %bb.6(0x40000000), %bb.12(0x40000000) + + %19:gr32 = COPY %108 + %86:gr64 = ADD64ri32 %8, 1, implicit-def $eflags + %85:gr8 = MOV8rm %64, 1, %8, 1, $noreg :: (load (s8) from %ir.41, !tbaa !11) + CMP8ri %85, 0, implicit-def $eflags + %101:gr64_nosp = COPY %86 + %102:gr8 = COPY %85 + %103:gr32 = COPY %19 + %104:gr32 = COPY %17 + %105:gr32 = COPY %16 + %109:gr32 = COPY %16 + %110:gr32 = COPY %17 + %111:gr32 = COPY %19 + JCC_1 %bb.6, 5, implicit $eflags + + bb.12.BB_93: + successors: %bb.14(0x40000000), %bb.13(0x40000000) + + %24:gr32 = COPY %111 + %23:gr32 = COPY %110 + %22:gr32 = COPY %109 + CMP32rr %24, %23, implicit-def $eflags + %88:gr32 = CMOV32rr %23, %24, 12, implicit $eflags + %87:fr32 = FsFLD0SS + CMP32ri %88, 0, implicit-def $eflags + %112:fr32 = COPY %87 + JCC_1 %bb.14, 4, implicit $eflags + + bb.13.BB_94: + successors: %bb.14(0x80000000) + + %93:fr32 = CVTSI2SSrr %22, implicit $mxcsr + %92:fr32 = CVTSI2SSrr %88, implicit $mxcsr + %91:fr32 = DIVSSrr %93, %92, implicit $mxcsr + %112:fr32 = COPY %91 + + bb.14.BB_95: + successors: %bb.3(0x40000000), %bb.15(0x40000000) + + %27:fr32 = COPY %112 + %95:fr32 = ADDSSrr %1, %27, implicit $mxcsr + %94:gr32 = ADD32ri %2, 1, implicit-def $eflags + CMP32rr %94, %40, implicit-def $eflags + %99:fr32 = COPY %95 + %100:gr32 = COPY %94 + %113:fr32 = COPY %95 + JCC_1 %bb.3, 5, implicit $eflags + + bb.15.BB_96: + successors: %bb.16(0x80000000) + + %30:fr32 = COPY %113 + %98:fr32 = CVTSI2SSrr %40, implicit $mxcsr + %97:fr32 = DIVSSrr %30, %98, implicit $mxcsr + %114:fr32 = COPY %97 + + bb.16.BB_97: + %32:fr32 = COPY %114 + $xmm0 = COPY %32 + RET64 implicit $xmm0 + +... +--- +name: MajorityRuleConsensus +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: gr64, preferred-register: '' } + - { id: 1, class: gr64, preferred-register: '' } + - { id: 2, class: gr8, preferred-register: '' } + - { id: 3, class: gr64, preferred-register: '' } + - { id: 4, class: fr32, preferred-register: '' } + - { id: 5, class: gr64, preferred-register: '' } + - { id: 6, class: gr64, preferred-register: '' } + - { id: 7, class: gr64, preferred-register: '' } + - { id: 8, class: gr64, preferred-register: '' } + - { id: 9, class: gr64, preferred-register: '' } + - { id: 10, class: gr64, preferred-register: '' } + - { id: 11, class: gr64, preferred-register: '' } + - { id: 12, class: gr64, preferred-register: '' } + - { id: 13, class: gr64, preferred-register: '' } + - { id: 14, class: gr64, preferred-register: '' } + - { id: 15, class: gr64, preferred-register: '' } + - { id: 16, class: gr64, preferred-register: '' } + - { id: 17, class: gr64, preferred-register: '' } + - { id: 18, class: gr64, preferred-register: '' } + - { id: 19, class: gr64, preferred-register: '' } + - { id: 20, class: gr64, preferred-register: '' } + - { id: 21, class: gr64, preferred-register: '' } + - { id: 22, class: gr64, preferred-register: '' } + - { id: 23, class: gr64, preferred-register: '' } + - { id: 24, class: gr64, preferred-register: '' } + - { id: 25, class: gr64, preferred-register: '' } + - { id: 26, class: gr64, preferred-register: '' } + - { id: 27, class: gr64, preferred-register: '' } + - { id: 28, class: gr64, preferred-register: '' } + - { id: 29, class: gr64, preferred-register: '' } + - { id: 30, class: gr64, preferred-register: '' } + - { id: 31, class: gr64, preferred-register: '' } + - { id: 32, class: gr64, preferred-register: '' } + - { id: 33, class: gr64_nosp, preferred-register: '' } + - { id: 34, class: gr32, preferred-register: '' } + - { id: 35, class: gr64, preferred-register: '' } + - { id: 36, class: gr64_nosp, preferred-register: '' } + - { id: 37, class: gr64_nosp, preferred-register: '' } + - { id: 38, class: gr64, preferred-register: '' } + - { id: 39, class: gr32, preferred-register: '' } + - { id: 40, class: gr32, preferred-register: '' } + - { id: 41, class: gr32, preferred-register: '' } + - { id: 42, class: gr32, preferred-register: '' } + - { id: 43, class: gr64, preferred-register: '' } + - { id: 44, class: gr32, preferred-register: '' } + - { id: 45, class: gr64, preferred-register: '' } + - { id: 46, class: gr64, preferred-register: '' } + - { id: 47, class: gr32, preferred-register: '' } + - { id: 48, class: gr32, preferred-register: '' } + - { id: 49, class: gr32, preferred-register: '' } + - { id: 50, class: gr32, preferred-register: '' } + - { id: 51, class: gr32, preferred-register: '' } + - { id: 52, class: gr64, preferred-register: '' } + - { id: 53, class: gr32, preferred-register: '' } + - { id: 54, class: gr64, preferred-register: '' } + - { id: 55, class: gr64, preferred-register: '' } + - { id: 56, class: gr32, preferred-register: '' } + - { id: 57, class: gr64, preferred-register: '' } + - { id: 58, class: gr32, preferred-register: '' } + - { id: 59, class: gr64, preferred-register: '' } + - { id: 60, class: gr32, preferred-register: '' } + - { id: 61, class: gr64, preferred-register: '' } + - { id: 62, class: gr32, preferred-register: '' } + - { id: 63, class: gr64, preferred-register: '' } + - { id: 64, class: gr64, preferred-register: '' } + - { id: 65, class: gr64, preferred-register: '' } + - { id: 66, class: gr64, preferred-register: '' } + - { id: 67, class: gr64, preferred-register: '' } + - { id: 68, class: gr64, preferred-register: '' } + - { id: 69, class: gr64, preferred-register: '' } + - { id: 70, class: gr64, preferred-register: '' } + - { id: 71, class: gr64, preferred-register: '' } + - { id: 72, class: gr64, preferred-register: '' } + - { id: 73, class: gr64, preferred-register: '' } + - { id: 74, class: gr64, preferred-register: '' } + - { id: 75, class: gr64, preferred-register: '' } + - { id: 76, class: gr64, preferred-register: '' } + - { id: 77, class: gr64, preferred-register: '' } + - { id: 78, class: gr64, preferred-register: '' } + - { id: 79, class: gr64, preferred-register: '' } + - { id: 80, class: gr64, preferred-register: '' } + - { id: 81, class: gr64, preferred-register: '' } + - { id: 82, class: gr64, preferred-register: '' } + - { id: 83, class: gr64, preferred-register: '' } + - { id: 84, class: gr64, preferred-register: '' } + - { id: 85, class: gr64, preferred-register: '' } + - { id: 86, class: gr64, preferred-register: '' } + - { id: 87, class: gr64, preferred-register: '' } + - { id: 88, class: gr64, preferred-register: '' } + - { id: 89, class: gr64, preferred-register: '' } + - { id: 90, class: gr64, preferred-register: '' } + - { id: 91, class: gr64, preferred-register: '' } + - { id: 92, class: gr64, preferred-register: '' } + - { id: 93, class: gr64, preferred-register: '' } + - { id: 94, class: gr64, preferred-register: '' } + - { id: 95, class: gr64, preferred-register: '' } + - { id: 96, class: gr64, preferred-register: '' } + - { id: 97, class: gr64, preferred-register: '' } + - { id: 98, class: gr64, preferred-register: '' } + - { id: 99, class: gr64, preferred-register: '' } + - { id: 100, class: gr64, preferred-register: '' } + - { id: 101, class: gr64, preferred-register: '' } + - { id: 102, class: gr64, preferred-register: '' } + - { id: 103, class: gr64, preferred-register: '' } + - { id: 104, class: gr64, preferred-register: '' } + - { id: 105, class: gr64, preferred-register: '' } + - { id: 106, class: gr64, preferred-register: '' } + - { id: 107, class: gr64, preferred-register: '' } + - { id: 108, class: gr64, preferred-register: '' } + - { id: 109, class: gr64, preferred-register: '' } + - { id: 110, class: gr64, preferred-register: '' } + - { id: 111, class: gr64, preferred-register: '' } + - { id: 112, class: gr64, preferred-register: '' } + - { id: 113, class: gr64, preferred-register: '' } + - { id: 114, class: gr32, preferred-register: '' } + - { id: 115, class: gr64, preferred-register: '' } + - { id: 116, class: gr32, preferred-register: '' } + - { id: 117, class: gr64, preferred-register: '' } + - { id: 118, class: fr32, preferred-register: '' } + - { id: 119, class: gr64, preferred-register: '' } + - { id: 120, class: gr64, preferred-register: '' } + - { id: 121, class: gr8, preferred-register: '' } + - { id: 122, class: gr32, preferred-register: '' } + - { id: 123, class: gr32, preferred-register: '' } + - { id: 124, class: gr64, preferred-register: '' } + - { id: 125, class: gr32, preferred-register: '' } + - { id: 126, class: gr64, preferred-register: '' } + - { id: 127, class: gr64, preferred-register: '' } + - { id: 128, class: gr64, preferred-register: '' } + - { id: 129, class: gr64, preferred-register: '' } + - { id: 130, class: gr16, preferred-register: '' } + - { id: 131, class: gr16, preferred-register: '' } + - { id: 132, class: gr16, preferred-register: '' } + - { id: 133, class: gr16, preferred-register: '' } + - { id: 134, class: gr8, preferred-register: '' } + - { id: 135, class: gr64_nosp, preferred-register: '' } + - { id: 136, class: gr64, preferred-register: '' } + - { id: 137, class: gr64, preferred-register: '' } + - { id: 138, class: gr64_nosp, preferred-register: '' } + - { id: 139, class: gr32, preferred-register: '' } + - { id: 140, class: gr32, preferred-register: '' } + - { id: 141, class: gr32, preferred-register: '' } + - { id: 142, class: gr32, preferred-register: '' } + - { id: 143, class: gr32, preferred-register: '' } + - { id: 144, class: gr64_nosp, preferred-register: '' } + - { id: 145, class: gr32, preferred-register: '' } + - { id: 146, class: gr32, preferred-register: '' } + - { id: 147, class: gr64, preferred-register: '' } + - { id: 148, class: gr32, preferred-register: '' } + - { id: 149, class: gr64, preferred-register: '' } + - { id: 150, class: gr64, preferred-register: '' } + - { id: 151, class: gr64, preferred-register: '' } + - { id: 152, class: gr32, preferred-register: '' } + - { id: 153, class: gr32, preferred-register: '' } + - { id: 154, class: gr32, preferred-register: '' } + - { id: 155, class: gr32, preferred-register: '' } + - { id: 156, class: gr64, preferred-register: '' } + - { id: 157, class: gr32, preferred-register: '' } + - { id: 158, class: fr32, preferred-register: '' } + - { id: 159, class: fr32, preferred-register: '' } + - { id: 160, class: fr32, preferred-register: '' } + - { id: 161, class: fr32, preferred-register: '' } + - { id: 162, class: fr32, preferred-register: '' } + - { id: 163, class: gr64_nosp, preferred-register: '' } + - { id: 164, class: gr8, preferred-register: '' } + - { id: 165, class: gr64_nosp, preferred-register: '' } + - { id: 166, class: gr32, preferred-register: '' } + - { id: 167, class: gr32, preferred-register: '' } + - { id: 168, class: gr32, preferred-register: '' } + - { id: 169, class: gr8, preferred-register: '' } + - { id: 170, class: gr8, preferred-register: '' } + - { id: 171, class: gr8, preferred-register: '' } + - { id: 172, class: gr32, preferred-register: '' } + - { id: 173, class: gr32, preferred-register: '' } + - { id: 174, class: gr8, preferred-register: '' } + - { id: 175, class: gr8, preferred-register: '' } + - { id: 176, class: gr8, preferred-register: '' } + - { id: 177, class: gr32, preferred-register: '' } + - { id: 178, class: gr32, preferred-register: '' } + - { id: 179, class: gr8, preferred-register: '' } + - { id: 180, class: gr8, preferred-register: '' } + - { id: 181, class: gr8, preferred-register: '' } + - { id: 182, class: gr32, preferred-register: '' } + - { id: 183, class: gr32, preferred-register: '' } + - { id: 184, class: gr8, preferred-register: '' } + - { id: 185, class: gr8, preferred-register: '' } + - { id: 186, class: gr8, preferred-register: '' } + - { id: 187, class: gr32, preferred-register: '' } + - { id: 188, class: gr32, preferred-register: '' } + - { id: 189, class: gr8, preferred-register: '' } + - { id: 190, class: gr8, preferred-register: '' } + - { id: 191, class: gr8, preferred-register: '' } + - { id: 192, class: gr32, preferred-register: '' } + - { id: 193, class: gr32, preferred-register: '' } + - { id: 194, class: gr8, preferred-register: '' } + - { id: 195, class: gr8, preferred-register: '' } + - { id: 196, class: gr8, preferred-register: '' } + - { id: 197, class: gr32, preferred-register: '' } + - { id: 198, class: gr32, preferred-register: '' } + - { id: 199, class: gr8, preferred-register: '' } + - { id: 200, class: gr8, preferred-register: '' } + - { id: 201, class: gr8, preferred-register: '' } + - { id: 202, class: gr32, preferred-register: '' } + - { id: 203, class: gr32, preferred-register: '' } + - { id: 204, class: gr8, preferred-register: '' } + - { id: 205, class: gr8, preferred-register: '' } + - { id: 206, class: gr8, preferred-register: '' } + - { id: 207, class: gr32, preferred-register: '' } + - { id: 208, class: gr32, preferred-register: '' } + - { id: 209, class: gr8, preferred-register: '' } + - { id: 210, class: gr8, preferred-register: '' } + - { id: 211, class: gr8, preferred-register: '' } + - { id: 212, class: gr32, preferred-register: '' } + - { id: 213, class: gr32, preferred-register: '' } + - { id: 214, class: gr8, preferred-register: '' } + - { id: 215, class: gr8, preferred-register: '' } + - { id: 216, class: gr8, preferred-register: '' } + - { id: 217, class: gr32, preferred-register: '' } + - { id: 218, class: gr32, preferred-register: '' } + - { id: 219, class: gr8, preferred-register: '' } + - { id: 220, class: gr8, preferred-register: '' } + - { id: 221, class: gr8, preferred-register: '' } + - { id: 222, class: gr32, preferred-register: '' } + - { id: 223, class: gr32, preferred-register: '' } + - { id: 224, class: gr8, preferred-register: '' } + - { id: 225, class: gr8, preferred-register: '' } + - { id: 226, class: gr8, preferred-register: '' } + - { id: 227, class: gr32, preferred-register: '' } + - { id: 228, class: gr32, preferred-register: '' } + - { id: 229, class: gr8, preferred-register: '' } + - { id: 230, class: gr8, preferred-register: '' } + - { id: 231, class: gr8, preferred-register: '' } + - { id: 232, class: gr32, preferred-register: '' } + - { id: 233, class: gr32, preferred-register: '' } + - { id: 234, class: gr8, preferred-register: '' } + - { id: 235, class: gr8, preferred-register: '' } + - { id: 236, class: gr8, preferred-register: '' } + - { id: 237, class: gr32, preferred-register: '' } + - { id: 238, class: gr32, preferred-register: '' } + - { id: 239, class: gr8, preferred-register: '' } + - { id: 240, class: gr8, preferred-register: '' } + - { id: 241, class: gr8, preferred-register: '' } + - { id: 242, class: gr32, preferred-register: '' } + - { id: 243, class: gr32, preferred-register: '' } + - { id: 244, class: gr8, preferred-register: '' } + - { id: 245, class: gr8, preferred-register: '' } + - { id: 246, class: gr8, preferred-register: '' } + - { id: 247, class: gr32, preferred-register: '' } + - { id: 248, class: gr32, preferred-register: '' } + - { id: 249, class: gr8, preferred-register: '' } + - { id: 250, class: gr8, preferred-register: '' } + - { id: 251, class: gr8, preferred-register: '' } + - { id: 252, class: gr32, preferred-register: '' } + - { id: 253, class: gr32, preferred-register: '' } + - { id: 254, class: gr8, preferred-register: '' } + - { id: 255, class: gr8, preferred-register: '' } + - { id: 256, class: gr8, preferred-register: '' } + - { id: 257, class: gr32, preferred-register: '' } + - { id: 258, class: gr32, preferred-register: '' } + - { id: 259, class: gr8, preferred-register: '' } + - { id: 260, class: gr8, preferred-register: '' } + - { id: 261, class: gr8, preferred-register: '' } + - { id: 262, class: gr32, preferred-register: '' } + - { id: 263, class: gr32, preferred-register: '' } + - { id: 264, class: gr8, preferred-register: '' } + - { id: 265, class: gr8, preferred-register: '' } + - { id: 266, class: gr8, preferred-register: '' } + - { id: 267, class: gr32, preferred-register: '' } + - { id: 268, class: gr32, preferred-register: '' } + - { id: 269, class: gr8, preferred-register: '' } + - { id: 270, class: gr8, preferred-register: '' } + - { id: 271, class: gr8, preferred-register: '' } + - { id: 272, class: gr32, preferred-register: '' } + - { id: 273, class: gr32, preferred-register: '' } + - { id: 274, class: gr8, preferred-register: '' } + - { id: 275, class: gr8, preferred-register: '' } + - { id: 276, class: gr8, preferred-register: '' } + - { id: 277, class: gr32, preferred-register: '' } + - { id: 278, class: gr32, preferred-register: '' } + - { id: 279, class: gr8, preferred-register: '' } + - { id: 280, class: gr8, preferred-register: '' } + - { id: 281, class: gr8, preferred-register: '' } + - { id: 282, class: gr32, preferred-register: '' } + - { id: 283, class: gr32, preferred-register: '' } + - { id: 284, class: gr8, preferred-register: '' } + - { id: 285, class: gr8, preferred-register: '' } + - { id: 286, class: gr8, preferred-register: '' } + - { id: 287, class: gr32, preferred-register: '' } + - { id: 288, class: gr32, preferred-register: '' } + - { id: 289, class: gr8, preferred-register: '' } + - { id: 290, class: gr8, preferred-register: '' } + - { id: 291, class: gr8, preferred-register: '' } + - { id: 292, class: gr32, preferred-register: '' } + - { id: 293, class: gr8, preferred-register: '' } + - { id: 294, class: gr8, preferred-register: '' } + - { id: 295, class: gr8, preferred-register: '' } + - { id: 296, class: gr32, preferred-register: '' } + - { id: 297, class: gr32, preferred-register: '' } + - { id: 298, class: gr32, preferred-register: '' } + - { id: 299, class: gr32, preferred-register: '' } + - { id: 300, class: gr32, preferred-register: '' } + - { id: 301, class: gr32, preferred-register: '' } + - { id: 302, class: gr32, preferred-register: '' } + - { id: 303, class: gr32, preferred-register: '' } + - { id: 304, class: gr32, preferred-register: '' } + - { id: 305, class: gr32, preferred-register: '' } + - { id: 306, class: gr32, preferred-register: '' } + - { id: 307, class: gr32, preferred-register: '' } + - { id: 308, class: gr32, preferred-register: '' } + - { id: 309, class: gr32, preferred-register: '' } + - { id: 310, class: gr32, preferred-register: '' } + - { id: 311, class: gr32, preferred-register: '' } + - { id: 312, class: gr32, preferred-register: '' } + - { id: 313, class: gr32, preferred-register: '' } + - { id: 314, class: gr32, preferred-register: '' } + - { id: 315, class: gr32, preferred-register: '' } + - { id: 316, class: gr32, preferred-register: '' } + - { id: 317, class: gr32, preferred-register: '' } + - { id: 318, class: gr32, preferred-register: '' } + - { id: 319, class: gr32, preferred-register: '' } + - { id: 320, class: gr32, preferred-register: '' } + - { id: 321, class: gr32, preferred-register: '' } + - { id: 322, class: gr32, preferred-register: '' } + - { id: 323, class: gr32, preferred-register: '' } + - { id: 324, class: gr32, preferred-register: '' } + - { id: 325, class: gr32, preferred-register: '' } + - { id: 326, class: gr32, preferred-register: '' } + - { id: 327, class: gr32, preferred-register: '' } + - { id: 328, class: gr32, preferred-register: '' } + - { id: 329, class: gr32, preferred-register: '' } + - { id: 330, class: gr32, preferred-register: '' } + - { id: 331, class: gr32, preferred-register: '' } + - { id: 332, class: gr32, preferred-register: '' } + - { id: 333, class: gr32, preferred-register: '' } + - { id: 334, class: gr32, preferred-register: '' } + - { id: 335, class: gr32, preferred-register: '' } + - { id: 336, class: gr32, preferred-register: '' } + - { id: 337, class: gr32, preferred-register: '' } + - { id: 338, class: gr32, preferred-register: '' } + - { id: 339, class: gr32, preferred-register: '' } + - { id: 340, class: gr32, preferred-register: '' } + - { id: 341, class: gr32, preferred-register: '' } + - { id: 342, class: gr32, preferred-register: '' } + - { id: 343, class: gr32, preferred-register: '' } + - { id: 344, class: gr32, preferred-register: '' } + - { id: 345, class: gr32, preferred-register: '' } + - { id: 346, class: gr32, preferred-register: '' } + - { id: 347, class: gr32, preferred-register: '' } + - { id: 348, class: gr64, preferred-register: '' } + - { id: 349, class: gr64_nosp, preferred-register: '' } + - { id: 350, class: gr64_nosp, preferred-register: '' } + - { id: 351, class: gr64_nosp, preferred-register: '' } + - { id: 352, class: gr32, preferred-register: '' } + - { id: 353, class: gr64_nosp, preferred-register: '' } + - { id: 354, class: gr32, preferred-register: '' } + - { id: 355, class: gr8, preferred-register: '' } + - { id: 356, class: gr8, preferred-register: '' } + - { id: 357, class: gr8, preferred-register: '' } + - { id: 358, class: gr8, preferred-register: '' } + - { id: 359, class: gr8, preferred-register: '' } + - { id: 360, class: gr8, preferred-register: '' } + - { id: 361, class: gr8, preferred-register: '' } + - { id: 362, class: gr8, preferred-register: '' } + - { id: 363, class: gr8, preferred-register: '' } + - { id: 364, class: gr8, preferred-register: '' } + - { id: 365, class: gr8, preferred-register: '' } + - { id: 366, class: gr8, preferred-register: '' } + - { id: 367, class: gr8, preferred-register: '' } + - { id: 368, class: gr8, preferred-register: '' } + - { id: 369, class: gr8, preferred-register: '' } + - { id: 370, class: gr8, preferred-register: '' } + - { id: 371, class: gr8, preferred-register: '' } + - { id: 372, class: gr8, preferred-register: '' } + - { id: 373, class: gr8, preferred-register: '' } + - { id: 374, class: gr8, preferred-register: '' } + - { id: 375, class: gr8, preferred-register: '' } + - { id: 376, class: gr8, preferred-register: '' } + - { id: 377, class: gr8, preferred-register: '' } + - { id: 378, class: gr8, preferred-register: '' } + - { id: 379, class: gr8, preferred-register: '' } + - { id: 380, class: gr8, preferred-register: '' } + - { id: 381, class: gr32, preferred-register: '' } + - { id: 382, class: gr32, preferred-register: '' } +liveins: + - { reg: '$rdi', virtual-reg: '%45' } + - { reg: '$esi', virtual-reg: '%47' } + - { reg: '$edx', virtual-reg: '%49' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 16 + adjustsStack: false + hasCalls: true + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: '', type: default, offset: 0, size: 108, alignment: 16, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: + - id: 0 + value: float 5.000000e-01 + alignment: 4 + isTargetSpecific: false +machineFunctionInfo: {} +body: | + bb.0.BB_98: + successors: %bb.12(0x40000000), %bb.1(0x40000000) + liveins: $rdi, $esi, $edx + + %49:gr32 = COPY $edx + %47:gr32 = COPY $esi + %45:gr64 = COPY $rdi + %46:gr64 = COPY killed %45 + %48:gr32 = COPY killed %47 + %50:gr32 = COPY killed %49 + %59:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %58:gr32 = ADD32ri %50, 1, implicit-def $eflags + %57:gr64 = MOVSX64rr32 %58 + %52:gr64 = MOV64ri @.str + %53:gr32 = MOV32ri 485 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %52 + $esi = COPY %53 + $rdx = COPY %57 + CALL64pcrel32 target-flags(x86-plt) @sre_malloc, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit $rdx, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %55:gr64 = COPY $rax + %51:gr32 = MOV32r0 implicit-def $eflags + CMP32ri %50, 0, implicit-def $eflags + %382:gr32 = COPY %51 + JCC_1 %bb.12, 14, implicit $eflags + + bb.1.BB_99: + successors: %bb.2(0x80000000) + + CMP32ri %48, 0, implicit-def $eflags + %121:gr8 = SETCCr 15, implicit $eflags + %119:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %120:gr64 = ADD64ri32 %119, 104, implicit-def $eflags + %118:fr32 = CVTSI2SSrr %48, implicit $mxcsr + %116:gr32 = MOV32rr %50 + %117:gr64 = SUBREG_TO_REG 0, %116, %subreg.sub_32bit + %114:gr32 = MOV32rr %48 + %115:gr64 = SUBREG_TO_REG 0, %114, %subreg.sub_32bit + %113:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %111:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %112:gr64 = ADD64ri32 %111, 4, implicit-def $eflags + %109:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %110:gr64 = ADD64ri32 %109, 8, implicit-def $eflags + %107:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %108:gr64 = ADD64ri32 %107, 12, implicit-def $eflags + %105:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %106:gr64 = ADD64ri32 %105, 16, implicit-def $eflags + %103:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %104:gr64 = ADD64ri32 %103, 20, implicit-def $eflags + %101:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %102:gr64 = ADD64ri32 %101, 24, implicit-def $eflags + %99:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %100:gr64 = ADD64ri32 %99, 28, implicit-def $eflags + %97:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %98:gr64 = ADD64ri32 %97, 32, implicit-def $eflags + %95:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %96:gr64 = ADD64ri32 %95, 36, implicit-def $eflags + %93:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %94:gr64 = ADD64ri32 %93, 40, implicit-def $eflags + %91:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %92:gr64 = ADD64ri32 %91, 44, implicit-def $eflags + %89:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %90:gr64 = ADD64ri32 %89, 48, implicit-def $eflags + %87:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %88:gr64 = ADD64ri32 %87, 52, implicit-def $eflags + %85:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %86:gr64 = ADD64ri32 %85, 56, implicit-def $eflags + %83:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %84:gr64 = ADD64ri32 %83, 60, implicit-def $eflags + %81:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %82:gr64 = ADD64ri32 %81, 64, implicit-def $eflags + %79:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %80:gr64 = ADD64ri32 %79, 68, implicit-def $eflags + %77:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %78:gr64 = ADD64ri32 %77, 72, implicit-def $eflags + %75:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %76:gr64 = ADD64ri32 %75, 76, implicit-def $eflags + %73:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %74:gr64 = ADD64ri32 %73, 80, implicit-def $eflags + %71:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %72:gr64 = ADD64ri32 %71, 84, implicit-def $eflags + %69:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %70:gr64 = ADD64ri32 %69, 88, implicit-def $eflags + %67:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %68:gr64 = ADD64ri32 %67, 92, implicit-def $eflags + %65:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %66:gr64 = ADD64ri32 %65, 96, implicit-def $eflags + %63:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg + %64:gr64 = ADD64ri32 %63, 100, implicit-def $eflags + %60:gr32 = MOV32r0 implicit-def $eflags + %61:gr64 = SUBREG_TO_REG 0, %60, %subreg.sub_32bit + %62:gr32 = MOV32r0 implicit-def $eflags + %351:gr64_nosp = COPY %61 + %352:gr32 = COPY %62 + + bb.2.BB_100: + successors: %bb.3(0x40000000), %bb.9(0x40000000) + + %34:gr32 = COPY %352 + %33:gr64_nosp = COPY %351 + %123:gr32 = MOV32r0 implicit-def $eflags + %124:gr64 = MOV32ri64 108 + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + $rdi = COPY %59 + $esi = COPY %123 + $rdx = COPY %124 + CALL64pcrel32 target-flags(x86-plt) , csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $esi, implicit $rdx + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %122:gr32 = MOV32r0 implicit-def $eflags + TEST8ri %121, 1, implicit-def $eflags + %354:gr32 = COPY %122 + JCC_1 %bb.3, 5, implicit $eflags + JMP_1 %bb.9 + + bb.3.BB_101: + successors: %bb.4(0x80000000) + + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 target-flags(x86-plt) @__ctype_b_loc, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %129:gr64 = COPY $rax + %128:gr64 = MOV64rm %129, 1, $noreg, 0, $noreg :: (load (s64) from %ir.42, !tbaa !5) + %125:gr32 = MOV32r0 implicit-def $eflags + %126:gr64 = SUBREG_TO_REG 0, %125, %subreg.sub_32bit + %353:gr64_nosp = COPY %126 + + bb.4.BB_102: + successors: %bb.6(0x40000000), %bb.5(0x40000000) + + %36:gr64_nosp = COPY %353 + %137:gr64 = MOV64rm %46, 8, %36, 0, $noreg :: (load (s64) from %ir.45, !tbaa !5) + %135:gr64_nosp = MOVSX64rm8 %137, 1, %33, 0, $noreg :: (load (s8) from %ir.47, !tbaa !11) + %133:gr16 = MOV16rm %128, 2, %135, 0, $noreg :: (load (s16) from %ir.50, !tbaa !12) + %132:gr16 = AND16ri %133, 1024, implicit-def $eflags + CMP16ri %132, 0, implicit-def $eflags + JCC_1 %bb.6, 4, implicit $eflags + + bb.5.BB_103: + successors: %bb.7(0x80000000) + + ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + CALL64pcrel32 target-flags(x86-plt) @__ctype_toupper_loc, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax + ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp + %151:gr64 = COPY $rax + %150:gr64 = MOV64rm %151, 1, $noreg, 0, $noreg :: (load (s64) from %ir.54, !tbaa !5) + %148:gr32 = MOV32rm %150, 4, %135, 0, $noreg :: (load (s32) from %ir.56, !tbaa !9) + %146:gr32 = ADD32ri %148, -65, implicit-def $eflags + %144:gr64_nosp = MOVSX64rr32 %146 + %142:gr32 = MOV32rm %stack.0, 4, %144, 0, $noreg :: (load (s32) from %ir.60, !tbaa !9) + %141:gr32 = ADD32ri %142, 1, implicit-def $eflags + MOV32mr %stack.0, 4, %144, 0, $noreg, %141 :: (store (s32) into %ir.60, !tbaa !9) + JMP_1 %bb.7 + + bb.6.BB_104: + successors: %bb.7(0x80000000) + + %155:gr32 = MOV32rm %120, 1, $noreg, 0, $noreg :: (load (s32) from %ir.10, align 8, !tbaa !9) + %154:gr32 = ADD32ri %155, 1, implicit-def $eflags + MOV32mr %120, 1, $noreg, 0, $noreg, %154 :: (store (s32) into %ir.10, align 8, !tbaa !9) + + bb.7.BB_105: + successors: %bb.4(0x40000000), %bb.8(0x40000000) + + %156:gr64 = ADD64ri32 %36, 1, implicit-def $eflags + CMP64rr %156, %115, implicit-def $eflags + %353:gr64_nosp = COPY %156 + JCC_1 %bb.4, 5, implicit $eflags + + bb.8.BB_106: + successors: %bb.9(0x80000000) + + %157:gr32 = MOV32rm %120, 1, $noreg, 0, $noreg :: (load (s32) from %ir.10, align 8, !tbaa !9) + %354:gr32 = COPY %157 + + bb.9.BB_107: + successors: %bb.11(0x40000000), %bb.10(0x40000000) + + %40:gr32 = COPY %354 + %162:fr32 = CVTSI2SSrr %40, implicit $mxcsr + %161:fr32 = DIVSSrr %162, %118, implicit $mxcsr + %158:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.0, $noreg + UCOMISSrr %158, %161, implicit-def $eflags, implicit $mxcsr + %381:gr32 = COPY %34 + JCC_1 %bb.11, 2, implicit $eflags + + bb.10.BB_108: + successors: %bb.13(0x40000000), %bb.14(0x40000000) + + %347:gr32 = MOV32rm %113, 1, $noreg, 0, $noreg :: (load (s32) from %ir.14, align 16, !tbaa !9) + %345:gr32 = MOV32ri 4294967295 + CMP32ri %347, -1, implicit-def $eflags + %346:gr32 = CMOV32rr %345, %347, 15, implicit $eflags + %344:gr32 = MOV32rm %112, 1, $noreg, 0, $noreg :: (load (s32) from %ir.15, !tbaa !9) + CMP32rr %344, %346, implicit-def $eflags + %343:gr32 = CMOV32rr %346, %344, 15, implicit $eflags + %342:gr32 = MOV32rm %110, 1, $noreg, 0, $noreg :: (load (s32) from %ir.16, align 8, !tbaa !9) + CMP32rr %342, %343, implicit-def $eflags + %341:gr32 = CMOV32rr %343, %342, 15, implicit $eflags + %340:gr32 = MOV32rm %108, 1, $noreg, 0, $noreg :: (load (s32) from %ir.17, !tbaa !9) + CMP32rr %340, %341, implicit-def $eflags + %339:gr32 = CMOV32rr %341, %340, 15, implicit $eflags + %338:gr32 = MOV32rm %106, 1, $noreg, 0, $noreg :: (load (s32) from %ir.18, align 16, !tbaa !9) + CMP32rr %338, %339, implicit-def $eflags + %337:gr32 = CMOV32rr %339, %338, 15, implicit $eflags + %336:gr32 = MOV32rm %104, 1, $noreg, 0, $noreg :: (load (s32) from %ir.19, !tbaa !9) + CMP32rr %336, %337, implicit-def $eflags + %335:gr32 = CMOV32rr %337, %336, 15, implicit $eflags + %334:gr32 = MOV32rm %102, 1, $noreg, 0, $noreg :: (load (s32) from %ir.20, align 8, !tbaa !9) + CMP32rr %334, %335, implicit-def $eflags + %333:gr32 = CMOV32rr %335, %334, 15, implicit $eflags + %332:gr32 = MOV32rm %100, 1, $noreg, 0, $noreg :: (load (s32) from %ir.21, !tbaa !9) + CMP32rr %332, %333, implicit-def $eflags + %331:gr32 = CMOV32rr %333, %332, 15, implicit $eflags + %330:gr32 = MOV32rm %98, 1, $noreg, 0, $noreg :: (load (s32) from %ir.22, align 16, !tbaa !9) + CMP32rr %330, %331, implicit-def $eflags + %329:gr32 = CMOV32rr %331, %330, 15, implicit $eflags + %328:gr32 = MOV32rm %96, 1, $noreg, 0, $noreg :: (load (s32) from %ir.23, !tbaa !9) + CMP32rr %328, %329, implicit-def $eflags + %327:gr32 = CMOV32rr %329, %328, 15, implicit $eflags + %326:gr32 = MOV32rm %94, 1, $noreg, 0, $noreg :: (load (s32) from %ir.24, align 8, !tbaa !9) + CMP32rr %326, %327, implicit-def $eflags + %325:gr32 = CMOV32rr %327, %326, 15, implicit $eflags + %324:gr32 = MOV32rm %92, 1, $noreg, 0, $noreg :: (load (s32) from %ir.25, !tbaa !9) + CMP32rr %324, %325, implicit-def $eflags + %323:gr32 = CMOV32rr %325, %324, 15, implicit $eflags + %322:gr32 = MOV32rm %90, 1, $noreg, 0, $noreg :: (load (s32) from %ir.26, align 16, !tbaa !9) + CMP32rr %322, %323, implicit-def $eflags + %321:gr32 = CMOV32rr %323, %322, 15, implicit $eflags + %320:gr32 = MOV32rm %88, 1, $noreg, 0, $noreg :: (load (s32) from %ir.27, !tbaa !9) + CMP32rr %320, %321, implicit-def $eflags + %319:gr32 = CMOV32rr %321, %320, 15, implicit $eflags + %318:gr32 = MOV32rm %86, 1, $noreg, 0, $noreg :: (load (s32) from %ir.28, align 8, !tbaa !9) + CMP32rr %318, %319, implicit-def $eflags + %317:gr32 = CMOV32rr %319, %318, 15, implicit $eflags + %316:gr32 = MOV32rm %84, 1, $noreg, 0, $noreg :: (load (s32) from %ir.29, !tbaa !9) + CMP32rr %316, %317, implicit-def $eflags + %315:gr32 = CMOV32rr %317, %316, 15, implicit $eflags + %314:gr32 = MOV32rm %82, 1, $noreg, 0, $noreg :: (load (s32) from %ir.30, align 16, !tbaa !9) + CMP32rr %314, %315, implicit-def $eflags + %313:gr32 = CMOV32rr %315, %314, 15, implicit $eflags + %312:gr32 = MOV32rm %80, 1, $noreg, 0, $noreg :: (load (s32) from %ir.31, !tbaa !9) + CMP32rr %312, %313, implicit-def $eflags + %311:gr32 = CMOV32rr %313, %312, 15, implicit $eflags + %310:gr32 = MOV32rm %78, 1, $noreg, 0, $noreg :: (load (s32) from %ir.32, align 8, !tbaa !9) + CMP32rr %310, %311, implicit-def $eflags + %309:gr32 = CMOV32rr %311, %310, 15, implicit $eflags + %308:gr32 = MOV32rm %76, 1, $noreg, 0, $noreg :: (load (s32) from %ir.33, !tbaa !9) + CMP32rr %308, %309, implicit-def $eflags + %307:gr32 = CMOV32rr %309, %308, 15, implicit $eflags + %306:gr32 = MOV32rm %74, 1, $noreg, 0, $noreg :: (load (s32) from %ir.34, align 16, !tbaa !9) + CMP32rr %306, %307, implicit-def $eflags + %305:gr32 = CMOV32rr %307, %306, 15, implicit $eflags + %304:gr32 = MOV32rm %72, 1, $noreg, 0, $noreg :: (load (s32) from %ir.35, !tbaa !9) + CMP32rr %304, %305, implicit-def $eflags + %303:gr32 = CMOV32rr %305, %304, 15, implicit $eflags + %302:gr32 = MOV32rm %70, 1, $noreg, 0, $noreg :: (load (s32) from %ir.36, align 8, !tbaa !9) + CMP32rr %302, %303, implicit-def $eflags + %301:gr32 = CMOV32rr %303, %302, 15, implicit $eflags + %300:gr32 = MOV32rm %68, 1, $noreg, 0, $noreg :: (load (s32) from %ir.37, !tbaa !9) + CMP32rr %300, %301, implicit-def $eflags + %299:gr32 = CMOV32rr %301, %300, 15, implicit $eflags + %298:gr32 = MOV32rm %66, 1, $noreg, 0, $noreg :: (load (s32) from %ir.38, align 16, !tbaa !9) + CMP32rr %298, %299, implicit-def $eflags + %297:gr32 = CMOV32rr %299, %298, 15, implicit $eflags + %296:gr32 = MOV32rm %64, 1, $noreg, 0, $noreg :: (load (s32) from %ir.39, !tbaa !9) + %293:gr8 = MOV8ri 65 + %294:gr8 = MOV8ri 64 + CMP32ri %347, -1, implicit-def $eflags + %355:gr8 = COPY %293 + JCC_1 %bb.14, 15, implicit $eflags + + bb.13.BB_108: + successors: %bb.14(0x80000000) + + %355:gr8 = COPY %294 + + bb.14.BB_108: + successors: %bb.15(0x40000000), %bb.16(0x40000000) + + %295:gr8 = COPY %355 + %289:gr8 = MOV8ri 66 + CMP32rr %344, %346, implicit-def $eflags + %356:gr8 = COPY %289 + JCC_1 %bb.16, 15, implicit $eflags + + bb.15.BB_108: + successors: %bb.16(0x80000000) + + %356:gr8 = COPY %295 + + bb.16.BB_108: + successors: %bb.17(0x40000000), %bb.18(0x40000000) + + %291:gr8 = COPY %356 + %284:gr8 = MOV8ri 67 + CMP32rr %342, %343, implicit-def $eflags + %357:gr8 = COPY %284 + JCC_1 %bb.18, 15, implicit $eflags + + bb.17.BB_108: + successors: %bb.18(0x80000000) + + %357:gr8 = COPY %291 + + bb.18.BB_108: + successors: %bb.19(0x40000000), %bb.20(0x40000000) + + %286:gr8 = COPY %357 + %279:gr8 = MOV8ri 68 + CMP32rr %340, %341, implicit-def $eflags + %358:gr8 = COPY %279 + JCC_1 %bb.20, 15, implicit $eflags + + bb.19.BB_108: + successors: %bb.20(0x80000000) + + %358:gr8 = COPY %286 + + bb.20.BB_108: + successors: %bb.21(0x40000000), %bb.22(0x40000000) + + %281:gr8 = COPY %358 + %274:gr8 = MOV8ri 69 + CMP32rr %338, %339, implicit-def $eflags + %359:gr8 = COPY %274 + JCC_1 %bb.22, 15, implicit $eflags + + bb.21.BB_108: + successors: %bb.22(0x80000000) + + %359:gr8 = COPY %281 + + bb.22.BB_108: + successors: %bb.23(0x40000000), %bb.24(0x40000000) + + %276:gr8 = COPY %359 + %269:gr8 = MOV8ri 70 + CMP32rr %336, %337, implicit-def $eflags + %360:gr8 = COPY %269 + JCC_1 %bb.24, 15, implicit $eflags + + bb.23.BB_108: + successors: %bb.24(0x80000000) + + %360:gr8 = COPY %276 + + bb.24.BB_108: + successors: %bb.25(0x40000000), %bb.26(0x40000000) + + %271:gr8 = COPY %360 + %264:gr8 = MOV8ri 71 + CMP32rr %334, %335, implicit-def $eflags + %361:gr8 = COPY %264 + JCC_1 %bb.26, 15, implicit $eflags + + bb.25.BB_108: + successors: %bb.26(0x80000000) + + %361:gr8 = COPY %271 + + bb.26.BB_108: + successors: %bb.27(0x40000000), %bb.28(0x40000000) + + %266:gr8 = COPY %361 + %259:gr8 = MOV8ri 72 + CMP32rr %332, %333, implicit-def $eflags + %362:gr8 = COPY %259 + JCC_1 %bb.28, 15, implicit $eflags + + bb.27.BB_108: + successors: %bb.28(0x80000000) + + %362:gr8 = COPY %266 + + bb.28.BB_108: + successors: %bb.29(0x40000000), %bb.30(0x40000000) + + %261:gr8 = COPY %362 + %254:gr8 = MOV8ri 73 + CMP32rr %330, %331, implicit-def $eflags + %363:gr8 = COPY %254 + JCC_1 %bb.30, 15, implicit $eflags + + bb.29.BB_108: + successors: %bb.30(0x80000000) + + %363:gr8 = COPY %261 + + bb.30.BB_108: + successors: %bb.31(0x40000000), %bb.32(0x40000000) + + %256:gr8 = COPY %363 + %249:gr8 = MOV8ri 74 + CMP32rr %328, %329, implicit-def $eflags + %364:gr8 = COPY %249 + JCC_1 %bb.32, 15, implicit $eflags + + bb.31.BB_108: + successors: %bb.32(0x80000000) + + %364:gr8 = COPY %256 + + bb.32.BB_108: + successors: %bb.33(0x40000000), %bb.34(0x40000000) + + %251:gr8 = COPY %364 + %244:gr8 = MOV8ri 75 + CMP32rr %326, %327, implicit-def $eflags + %365:gr8 = COPY %244 + JCC_1 %bb.34, 15, implicit $eflags + + bb.33.BB_108: + successors: %bb.34(0x80000000) + + %365:gr8 = COPY %251 + + bb.34.BB_108: + successors: %bb.35(0x40000000), %bb.36(0x40000000) + + %246:gr8 = COPY %365 + %239:gr8 = MOV8ri 76 + CMP32rr %324, %325, implicit-def $eflags + %366:gr8 = COPY %239 + JCC_1 %bb.36, 15, implicit $eflags + + bb.35.BB_108: + successors: %bb.36(0x80000000) + + %366:gr8 = COPY %246 + + bb.36.BB_108: + successors: %bb.37(0x40000000), %bb.38(0x40000000) + + %241:gr8 = COPY %366 + %234:gr8 = MOV8ri 77 + CMP32rr %322, %323, implicit-def $eflags + %367:gr8 = COPY %234 + JCC_1 %bb.38, 15, implicit $eflags + + bb.37.BB_108: + successors: %bb.38(0x80000000) + + %367:gr8 = COPY %241 + + bb.38.BB_108: + successors: %bb.39(0x40000000), %bb.40(0x40000000) + + %236:gr8 = COPY %367 + %229:gr8 = MOV8ri 78 + CMP32rr %320, %321, implicit-def $eflags + %368:gr8 = COPY %229 + JCC_1 %bb.40, 15, implicit $eflags + + bb.39.BB_108: + successors: %bb.40(0x80000000) + + %368:gr8 = COPY %236 + + bb.40.BB_108: + successors: %bb.41(0x40000000), %bb.42(0x40000000) + + %231:gr8 = COPY %368 + %224:gr8 = MOV8ri 79 + CMP32rr %318, %319, implicit-def $eflags + %369:gr8 = COPY %224 + JCC_1 %bb.42, 15, implicit $eflags + + bb.41.BB_108: + successors: %bb.42(0x80000000) + + %369:gr8 = COPY %231 + + bb.42.BB_108: + successors: %bb.43(0x40000000), %bb.44(0x40000000) + + %226:gr8 = COPY %369 + %219:gr8 = MOV8ri 80 + CMP32rr %316, %317, implicit-def $eflags + %370:gr8 = COPY %219 + JCC_1 %bb.44, 15, implicit $eflags + + bb.43.BB_108: + successors: %bb.44(0x80000000) + + %370:gr8 = COPY %226 + + bb.44.BB_108: + successors: %bb.45(0x40000000), %bb.46(0x40000000) + + %221:gr8 = COPY %370 + %214:gr8 = MOV8ri 81 + CMP32rr %314, %315, implicit-def $eflags + %371:gr8 = COPY %214 + JCC_1 %bb.46, 15, implicit $eflags + + bb.45.BB_108: + successors: %bb.46(0x80000000) + + %371:gr8 = COPY %221 + + bb.46.BB_108: + successors: %bb.47(0x40000000), %bb.48(0x40000000) + + %216:gr8 = COPY %371 + %209:gr8 = MOV8ri 82 + CMP32rr %312, %313, implicit-def $eflags + %372:gr8 = COPY %209 + JCC_1 %bb.48, 15, implicit $eflags + + bb.47.BB_108: + successors: %bb.48(0x80000000) + + %372:gr8 = COPY %216 + + bb.48.BB_108: + successors: %bb.49(0x40000000), %bb.50(0x40000000) + + %211:gr8 = COPY %372 + %204:gr8 = MOV8ri 83 + CMP32rr %310, %311, implicit-def $eflags + %373:gr8 = COPY %204 + JCC_1 %bb.50, 15, implicit $eflags + + bb.49.BB_108: + successors: %bb.50(0x80000000) + + %373:gr8 = COPY %211 + + bb.50.BB_108: + successors: %bb.51(0x40000000), %bb.52(0x40000000) + + %206:gr8 = COPY %373 + %199:gr8 = MOV8ri 84 + CMP32rr %308, %309, implicit-def $eflags + %374:gr8 = COPY %199 + JCC_1 %bb.52, 15, implicit $eflags + + bb.51.BB_108: + successors: %bb.52(0x80000000) + + %374:gr8 = COPY %206 + + bb.52.BB_108: + successors: %bb.53(0x40000000), %bb.54(0x40000000) + + %201:gr8 = COPY %374 + %194:gr8 = MOV8ri 85 + CMP32rr %306, %307, implicit-def $eflags + %375:gr8 = COPY %194 + JCC_1 %bb.54, 15, implicit $eflags + + bb.53.BB_108: + successors: %bb.54(0x80000000) + + %375:gr8 = COPY %201 + + bb.54.BB_108: + successors: %bb.55(0x40000000), %bb.56(0x40000000) + + %196:gr8 = COPY %375 + %189:gr8 = MOV8ri 86 + CMP32rr %304, %305, implicit-def $eflags + %376:gr8 = COPY %189 + JCC_1 %bb.56, 15, implicit $eflags + + bb.55.BB_108: + successors: %bb.56(0x80000000) + + %376:gr8 = COPY %196 + + bb.56.BB_108: + successors: %bb.57(0x40000000), %bb.58(0x40000000) + + %191:gr8 = COPY %376 + %184:gr8 = MOV8ri 87 + CMP32rr %302, %303, implicit-def $eflags + %377:gr8 = COPY %184 + JCC_1 %bb.58, 15, implicit $eflags + + bb.57.BB_108: + successors: %bb.58(0x80000000) + + %377:gr8 = COPY %191 + + bb.58.BB_108: + successors: %bb.59(0x40000000), %bb.60(0x40000000) + + %186:gr8 = COPY %377 + %179:gr8 = MOV8ri 88 + CMP32rr %300, %301, implicit-def $eflags + %378:gr8 = COPY %179 + JCC_1 %bb.60, 15, implicit $eflags + + bb.59.BB_108: + successors: %bb.60(0x80000000) + + %378:gr8 = COPY %186 + + bb.60.BB_108: + successors: %bb.61(0x40000000), %bb.62(0x40000000) + + %181:gr8 = COPY %378 + %174:gr8 = MOV8ri 89 + CMP32rr %298, %299, implicit-def $eflags + %379:gr8 = COPY %174 + JCC_1 %bb.62, 15, implicit $eflags + + bb.61.BB_108: + successors: %bb.62(0x80000000) + + %379:gr8 = COPY %181 + + bb.62.BB_108: + successors: %bb.63(0x40000000), %bb.64(0x40000000) + + %176:gr8 = COPY %379 + %169:gr8 = MOV8ri 90 + CMP32rr %296, %297, implicit-def $eflags + %380:gr8 = COPY %169 + JCC_1 %bb.64, 15, implicit $eflags + + bb.63.BB_108: + successors: %bb.64(0x80000000) + + %380:gr8 = COPY %176 + + bb.64.BB_108: + successors: %bb.11(0x80000000) + + %171:gr8 = COPY %380 + %166:gr32 = ADD32ri %34, 1, implicit-def $eflags + %165:gr64_nosp = MOVSX64rr32 %34 + MOV8mr %55, 1, %165, 0, $noreg, %171 :: (store (s8) into %ir.177, !tbaa !11) + %381:gr32 = COPY %166 + + bb.11.BB_109: + successors: %bb.2(0x40000000), %bb.12(0x40000000) + + %42:gr32 = COPY %381 + %348:gr64 = ADD64ri32 %33, 1, implicit-def $eflags + CMP64rr %348, %117, implicit-def $eflags + %351:gr64_nosp = COPY %348 + %352:gr32 = COPY %42 + %382:gr32 = COPY %42 + JCC_1 %bb.2, 5, implicit $eflags + + bb.12.BB_110: + %44:gr32 = COPY %382 + %350:gr64_nosp = MOVSX64rr32 %44 + MOV8mi %55, 1, %350, 0, $noreg, 0 :: (store (s8) into %ir.183, !tbaa !11) + $rax = COPY %55 + RET64 implicit $rax + +... diff --git a/mir_input/test_mir_input/aligneval_O2.bc.mir.liveinfo b/mir_input/test_mir_input/aligneval_O2.bc.mir.liveinfo new file mode 100644 index 00000000..9f71695d --- /dev/null +++ b/mir_input/test_mir_input/aligneval_O2.bc.mir.liveinfo @@ -0,0 +1,1293 @@ +ComparePairAlignments +CH [0B,16r:0)[336r,352r:4)[480r,496r:3)[624r,640r:2)[768r,784r:1) 0@0B-phi 1@768r 2@624r 3@480r 4@336r +CL [0B,16r:0)[336r,352r:4)[480r,496r:3)[624r,640r:2)[768r,784r:1) 0@0B-phi 1@768r 2@624r 3@480r 4@336r +DH [0B,32r:0)[320r,352r:4)[464r,496r:3)[608r,640r:2)[752r,784r:1) 0@0B-phi 1@752r 2@608r 3@464r 4@320r +DIL [0B,64r:0)[288r,352r:8)[432r,496r:7)[576r,640r:6)[720r,784r:5)[4272r,4288r:4)[4336r,4352r:3)[4400r,4416r:2)[4464r,4480r:1) 0@0B-phi 1@4464r 2@4400r 3@4336r 4@4272r 5@720r 6@576r 7@432r 8@288r +DIH [0B,64r:0)[288r,352r:8)[432r,496r:7)[576r,640r:6)[720r,784r:5)[4272r,4288r:4)[4336r,4352r:3)[4400r,4416r:2)[4464r,4480r:1) 0@0B-phi 1@4464r 2@4400r 3@4336r 4@4272r 5@720r 6@576r 7@432r 8@288r +DL [0B,32r:0)[320r,352r:4)[464r,496r:3)[608r,640r:2)[752r,784r:1) 0@0B-phi 1@752r 2@608r 3@464r 4@320r +HCX [0B,16r:0)[336r,352r:4)[480r,496r:3)[624r,640r:2)[768r,784r:1) 0@0B-phi 1@768r 2@624r 3@480r 4@336r +HDI [0B,64r:0)[288r,352r:8)[432r,496r:7)[576r,640r:6)[720r,784r:5)[4272r,4288r:4)[4336r,4352r:3)[4400r,4416r:2)[4464r,4480r:1) 0@0B-phi 1@4464r 2@4400r 3@4336r 4@4272r 5@720r 6@576r 7@432r 8@288r +HDX [0B,32r:0)[320r,352r:4)[464r,496r:3)[608r,640r:2)[752r,784r:1) 0@0B-phi 1@752r 2@608r 3@464r 4@320r +SIL [0B,48r:0)[304r,352r:4)[448r,496r:3)[592r,640r:2)[736r,784r:1) 0@0B-phi 1@736r 2@592r 3@448r 4@304r +SIH [0B,48r:0)[304r,352r:4)[448r,496r:3)[592r,640r:2)[736r,784r:1) 0@0B-phi 1@736r 2@592r 3@448r 4@304r +HSI [0B,48r:0)[304r,352r:4)[448r,496r:3)[592r,640r:2)[736r,784r:1) 0@0B-phi 1@736r 2@592r 3@448r 4@304r +%16 [1616r,1664r:0) 0@1616r weight:0.000000e+00 +%17 [1600r,1648r:0) 0@1600r weight:0.000000e+00 +%18 [1584r,1728r:0) 0@1584r weight:0.000000e+00 +%19 [1568r,1904r:0) 0@1568r weight:0.000000e+00 +%20 [1552r,1840r:0) 0@1552r weight:0.000000e+00 +%22 [1952r,2352r:0) 0@1952r weight:0.000000e+00 +%23 [1936r,2336r:0) 0@1936r weight:0.000000e+00 +%27 [2464r,2912r:0) 0@2464r weight:0.000000e+00 +%28 [2448r,2496r:0) 0@2448r weight:0.000000e+00 +%29 [2432r,2640r:0) 0@2432r weight:0.000000e+00 +%30 [2416r,2928r:0) 0@2416r weight:0.000000e+00 +%35 [3120r,3568r:0) 0@3120r weight:0.000000e+00 +%36 [3104r,3152r:0) 0@3104r weight:0.000000e+00 +%37 [3088r,3296r:0) 0@3088r weight:0.000000e+00 +%38 [3072r,3584r:0) 0@3072r weight:0.000000e+00 +%43 [3856r,3904r:0) 0@3856r weight:0.000000e+00 +%44 [3840r,3888r:0) 0@3840r weight:0.000000e+00 +%45 [3824r,4000r:0) 0@3824r weight:0.000000e+00 +%46 [3808r,3968r:0) 0@3808r weight:0.000000e+00 +%47 [3792r,4112r:0) 0@3792r weight:0.000000e+00 +%50 [4224r,4240r:0) 0@4224r weight:0.000000e+00 +%51 [4208r,4240r:0) 0@4208r weight:0.000000e+00 +%52 [64r,80r:0) 0@64r weight:0.000000e+00 +%53 [80r,736r:0) 0@80r weight:0.000000e+00 +%54 [48r,96r:0) 0@48r weight:0.000000e+00 +%55 [96r,720r:0) 0@96r weight:0.000000e+00 +%56 [32r,112r:0) 0@32r weight:0.000000e+00 +%57 [112r,448r:0) 0@112r weight:0.000000e+00 +%58 [16r,128r:0) 0@16r weight:0.000000e+00 +%59 [128r,432r:0) 0@128r weight:0.000000e+00 +%60 [912r,960r:0) 0@912r weight:0.000000e+00 +%61 [896r,2128r:0)[2400B,3056B:0) 0@896r weight:0.000000e+00 +%62 [880r,1120r:0) 0@880r weight:0.000000e+00 +%63 [864r,4464r:0) 0@864r weight:0.000000e+00 +%64 [848r,4400r:0) 0@848r weight:0.000000e+00 +%65 [832r,4336r:0) 0@832r weight:0.000000e+00 +%66 [816r,4272r:0) 0@816r weight:0.000000e+00 +%67 [672r,752r:0) 0@672r weight:0.000000e+00 +%68 [688r,768r:0) 0@688r weight:0.000000e+00 +%69 [528r,608r:0) 0@528r weight:0.000000e+00 +%70 [544r,624r:0) 0@544r weight:0.000000e+00 +%71 [384r,464r:0) 0@384r weight:0.000000e+00 +%72 [400r,480r:0) 0@400r weight:0.000000e+00 +%73 [240r,320r:0) 0@240r weight:0.000000e+00 +%74 [256r,336r:0) 0@256r weight:0.000000e+00 +%75 [224r,224d:0) 0@224r weight:0.000000e+00 +%76 [208r,208d:0) 0@208r weight:0.000000e+00 +%77 [192r,192d:0) 0@192r weight:0.000000e+00 +%78 [176r,176d:0) 0@176r weight:0.000000e+00 +%79 [160r,160d:0) 0@160r weight:0.000000e+00 +%80 [144r,144d:0) 0@144r weight:0.000000e+00 +%82 [1056r,1072r:0) 0@1056r weight:0.000000e+00 +%83 [1072r,1168r:0) 0@1072r weight:0.000000e+00 +%84 [1088r,1184r:0) 0@1088r weight:0.000000e+00 +%85 [1104r,1200r:0) 0@1104r weight:0.000000e+00 +%86 [1040r,1632r:0)[2400B,3056B:0) 0@1040r weight:0.000000e+00 +%87 [1008r,1024r:0) 0@1008r weight:0.000000e+00 +%88 [1024r,1264r:0) 0@1024r weight:0.000000e+00 +%89 [1280r,1296r:0) 0@1280r weight:0.000000e+00 +%90 [1296r,1376r:0) 0@1296r weight:0.000000e+00 +%91 [1312r,1360r:0) 0@1312r weight:0.000000e+00 +%92 [1248r,1264r:0) 0@1248r weight:0.000000e+00 +%93 [1264r,1408B:0)[2400B,3056B:0) 0@1264r weight:0.000000e+00 +%94 [2928r,3008r:0) 0@2928r weight:0.000000e+00 +%95 [1408B,1488r:0)[2912r,3056B:0) 0@2912r weight:0.000000e+00 +%100 [1408B,1520r:0)[2896r,3056B:0) 0@2896r weight:0.000000e+00 +%101 [2768r,2784r:0) 0@2768r weight:0.000000e+00 +%102 [2784r,2816r:0) 0@2784r weight:0.000000e+00 +%104 [2752r,2800r:0) 0@2752r weight:0.000000e+00 +%105 [2736r,2800r:0) 0@2736r weight:0.000000e+00 +%107 [2704r,2720r:0) 0@2704r weight:0.000000e+00 +%108 [1408B,1456r:0)[2720r,3056B:0) 0@2720r weight:0.000000e+00 +%109 [2688r,2752r:0) 0@2688r weight:0.000000e+00 +%113 [2672r,2864r:0) 0@2672r weight:0.000000e+00 +%114 [2544r,2560r:0) 0@2544r weight:0.000000e+00 +%115 [2560r,2592r:0) 0@2560r weight:0.000000e+00 +%116 [2528r,2576r:0) 0@2528r weight:0.000000e+00 +%117 [2512r,2576r:0) 0@2512r weight:0.000000e+00 +%118 [2480r,2496r:0) 0@2480r weight:0.000000e+00 +%119 [2496r,2720r:0) 0@2496r weight:0.000000e+00 +%120 [1424r,1440r:0) 0@1424r weight:0.000000e+00 +%121 [1440r,1504r:0) 0@1440r weight:0.000000e+00 +%125 [1872r,1888r:0) 0@1872r weight:0.000000e+00 +%126 [1744r,1760r:0) 0@1744r weight:0.000000e+00 +%127 [1760r,1792r:0) 0@1760r weight:0.000000e+00 +%128 [1728r,1776r:0) 0@1728r weight:0.000000e+00 +%129 [1712r,1776r:0) 0@1712r weight:0.000000e+00 +%131 [2096r,2112r:0) 0@2096r weight:0.000000e+00 +%132 [2112r,2176r:0) 0@2112r weight:0.000000e+00 +%133 [2080r,2400B:0)[3056B,3872r:0) 0@2080r weight:0.000000e+00 +%134 [2048r,2064r:0) 0@2048r weight:0.000000e+00 +%135 [2064r,2272r:0) 0@2064r weight:0.000000e+00 +%136 [2288r,2304r:0) 0@2288r weight:0.000000e+00 +%137 [2304r,2368r:0) 0@2304r weight:0.000000e+00 +%138 [2256r,2272r:0) 0@2256r weight:0.000000e+00 +%139 [2272r,2400B:0)[3056B,3776B:0) 0@2272r weight:0.000000e+00 +%140 [3584r,3664r:0) 0@3584r weight:0.000000e+00 +%141 [3568r,3712r:0) 0@3568r weight:0.000000e+00 +%146 [3552r,3744r:0) 0@3552r weight:0.000000e+00 +%147 [3424r,3440r:0) 0@3424r weight:0.000000e+00 +%148 [3440r,3472r:0) 0@3440r weight:0.000000e+00 +%150 [3408r,3456r:0) 0@3408r weight:0.000000e+00 +%151 [3392r,3456r:0) 0@3392r weight:0.000000e+00 +%153 [3360r,3376r:0) 0@3360r weight:0.000000e+00 +%154 [3376r,3728r:0) 0@3376r weight:0.000000e+00 +%155 [3344r,3408r:0) 0@3344r weight:0.000000e+00 +%159 [3328r,3520r:0) 0@3328r weight:0.000000e+00 +%160 [3200r,3216r:0) 0@3200r weight:0.000000e+00 +%161 [3216r,3248r:0) 0@3216r weight:0.000000e+00 +%162 [3184r,3232r:0) 0@3184r weight:0.000000e+00 +%163 [3168r,3232r:0) 0@3168r weight:0.000000e+00 +%164 [3136r,3152r:0) 0@3136r weight:0.000000e+00 +%165 [3152r,3376r:0) 0@3152r weight:0.000000e+00 +%169 [4144r,4160r:0) 0@4144r weight:0.000000e+00 +%170 [4016r,4032r:0) 0@4016r weight:0.000000e+00 +%171 [4032r,4064r:0) 0@4032r weight:0.000000e+00 +%172 [4000r,4048r:0) 0@4000r weight:0.000000e+00 +%173 [3984r,4048r:0) 0@3984r weight:0.000000e+00 +%174 [3952r,3968r:0) 0@3952r weight:0.000000e+00 +%175 [3968r,4176r:0) 0@3968r weight:0.000000e+00 +%181 [4240r,4512r:0) 0@4240r weight:0.000000e+00 +%182 [1136r,1232B:1)[1456r,1536B:0)[1536B,1616r:2) 0@1456r 1@1136r 2@1536B-phi weight:0.000000e+00 +%183 [1152r,1232B:1)[1472r,1536B:0)[1536B,1600r:2) 0@1472r 1@1152r 2@1536B-phi weight:0.000000e+00 +%184 [1168r,1232B:1)[1488r,1536B:0)[1536B,1584r:2) 0@1488r 1@1168r 2@1536B-phi weight:0.000000e+00 +%185 [1184r,1232B:1)[1504r,1536B:0)[1536B,1568r:2) 0@1504r 1@1184r 2@1536B-phi weight:0.000000e+00 +%186 [1200r,1232B:1)[1520r,1536B:0)[1536B,1552r:2) 0@1520r 1@1200r 2@1536B-phi weight:0.000000e+00 +%187 [1792r,1824B:1)[1840r,1856B:0)[1856B,1872r:2) 0@1840r 1@1792r 2@1856B-phi weight:0.000000e+00 +%188 [944r,992B:2)[1648r,1696B:1)[1888r,1920B:0)[1920B,1952r:3) 0@1888r 1@1648r 2@944r 3@1920B-phi weight:0.000000e+00 +%189 [960r,992B:2)[1664r,1696B:1)[1904r,1920B:0)[1920B,1936r:3) 0@1904r 1@1664r 2@960r 3@1920B-phi weight:0.000000e+00 +%190 [1328r,1408B:1)[2400B,2464r:2)[2960r,3056B:0) 0@2960r 1@1328r 2@2400B-phi weight:0.000000e+00 +%191 [1344r,1408B:1)[2400B,2448r:2)[2976r,3056B:0) 0@2976r 1@1344r 2@2400B-phi weight:0.000000e+00 +%192 [1360r,1408B:1)[2400B,2432r:2)[2992r,3056B:0) 0@2992r 1@1360r 2@2400B-phi weight:0.000000e+00 +%193 [1376r,1408B:1)[2400B,2416r:2)[3008r,3056B:0) 0@3008r 1@1376r 2@2400B-phi weight:0.000000e+00 +%194 [2592r,2624B:1)[2640r,2656B:0)[2656B,2672r:2) 0@2640r 1@2592r 2@2656B-phi weight:0.000000e+00 +%195 [2816r,2848B:1)[2864r,2880B:0)[2880B,2896r:2) 0@2864r 1@2816r 2@2880B-phi weight:0.000000e+00 +%196 [2320r,2400B:1)[3056B,3120r:2)[3616r,3776B:0) 0@3616r 1@2320r 2@3056B-phi weight:0.000000e+00 +%197 [2336r,2400B:1)[3056B,3104r:2)[3632r,3776B:0) 0@3632r 1@2336r 2@3056B-phi weight:0.000000e+00 +%198 [2352r,2400B:1)[3056B,3088r:2)[3648r,3776B:0) 0@3648r 1@2352r 2@3056B-phi weight:0.000000e+00 +%199 [2368r,2400B:1)[3056B,3072r:2)[3664r,3776B:0) 0@3664r 1@2368r 2@3056B-phi weight:0.000000e+00 +%200 [3248r,3280B:1)[3296r,3312B:0)[3312B,3328r:2) 0@3296r 1@3248r 2@3312B-phi weight:0.000000e+00 +%201 [3472r,3504B:1)[3520r,3536B:0)[3536B,3552r:2) 0@3520r 1@3472r 2@3536B-phi weight:0.000000e+00 +%202 [2144r,2240B:1)[3680r,3776B:0)[3776B,3856r:2) 0@3680r 1@2144r 2@3776B-phi weight:0.000000e+00 +%203 [2160r,2240B:1)[3696r,3776B:0)[3776B,3840r:2) 0@3696r 1@2160r 2@3776B-phi weight:0.000000e+00 +%204 [2176r,2240B:1)[3712r,3776B:0)[3776B,3824r:2) 0@3712r 1@2176r 2@3776B-phi weight:0.000000e+00 +%205 [2192r,2240B:1)[3728r,3776B:0)[3776B,3808r:2) 0@3728r 1@2192r 2@3776B-phi weight:0.000000e+00 +%206 [2208r,2240B:1)[3744r,3776B:0)[3776B,3792r:2) 0@3744r 1@2208r 2@3776B-phi weight:0.000000e+00 +%207 [4064r,4096B:1)[4112r,4128B:0)[4128B,4144r:2) 0@4112r 1@4064r 2@4128B-phi weight:0.000000e+00 +%208 [1984r,2032B:2)[3888r,3936B:1)[4160r,4192B:0)[4192B,4224r:3) 0@4160r 1@3888r 2@1984r 3@4192B-phi weight:0.000000e+00 +%209 [2000r,2032B:2)[3904r,3936B:1)[4176r,4192B:0)[4192B,4208r:3) 0@4176r 1@3904r 2@2000r 3@4192B-phi weight:0.000000e+00 +RegMasks: 352r 496r 640r 784r 4288r 4352r 4416r 4480r +BB_0: 0B 976B +BB_1: 992B 1216B +BB_2: 1232B 1392B +BB_3: 1408B 1520B +BB_4: 1536B 1680B +BB_5: 1696B 1808B +BB_5: 1824B 1840B +BB_5: 1856B 1904B +BB_6: 1920B 2016B +BB_7: 2032B 2224B +BB_8: 2240B 2384B +BB_9: 2400B 2608B +BB_9: 2624B 2640B +BB_9: 2656B 2832B +BB_9: 2848B 2864B +BB_9: 2880B 3040B +BB_10: 3056B 3264B +BB_10: 3280B 3296B +BB_10: 3312B 3488B +BB_10: 3504B 3520B +BB_10: 3536B 3760B +BB_11: 3776B 3920B +BB_12: 3936B 4080B +BB_12: 4096B 4112B +BB_12: 4128B 4176B +BB_13: 4192B 4528B +make_alilist +CH [0B,16r:0) 0@0B-phi +CL [0B,16r:0) 0@0B-phi +DH [0B,32r:0)[272r,288r:1) 0@0B-phi 1@272r +DIL [0B,64r:0)[96r,112r:2)[240r,288r:1) 0@0B-phi 1@240r 2@96r +DIH [0B,64r:0)[96r,112r:2)[240r,288r:1) 0@0B-phi 1@240r 2@96r +DL [0B,32r:0)[272r,288r:1) 0@0B-phi 1@272r +HCX [0B,16r:0) 0@0B-phi +HDI [0B,64r:0)[96r,112r:2)[240r,288r:1) 0@0B-phi 1@240r 2@96r +HDX [0B,32r:0)[272r,288r:1) 0@0B-phi 1@272r +SIL [0B,48r:0)[256r,288r:1) 0@0B-phi 1@256r +SIH [0B,48r:0)[256r,288r:1) 0@0B-phi 1@256r +HSI [0B,48r:0)[256r,288r:1) 0@0B-phi 1@256r +%2 [480r,1808r:0) 0@480r weight:0.000000e+00 +%3 [464r,1328r:0)[1888B,1904r:0) 0@464r weight:0.000000e+00 +%4 [448r,1744r:0) 0@448r weight:0.000000e+00 +%5 [912r,1216r:0) 0@912r weight:0.000000e+00 +%7 [1280r,1312r:0) 0@1280r weight:0.000000e+00 +%9 [1376r,1840r:0) 0@1376r weight:0.000000e+00 +%11 [1792r,1856r:0) 0@1792r weight:0.000000e+00 +%13 [64r,1888B:0) 0@64r weight:0.000000e+00 +%14 [48r,1888B:0) 0@48r weight:0.000000e+00 +%15 [32r,1920r:0) 0@32r weight:0.000000e+00 +%16 [16r,1904r:0) 0@16r weight:0.000000e+00 +%17 [336r,352r:0) 0@336r weight:0.000000e+00 +%18 [352r,384r:0) 0@352r weight:0.000000e+00 +%19 [368r,416r:0) 0@368r weight:0.000000e+00 +%20 [192r,240r:0) 0@192r weight:0.000000e+00 +%21 [208r,256r:0) 0@208r weight:0.000000e+00 +%23 [320r,1920r:0) 0@320r weight:0.000000e+00 +%24 [160r,176r:0) 0@160r weight:0.000000e+00 +%25 [176r,272r:0) 0@176r weight:0.000000e+00 +%26 [144r,160r:0) 0@144r weight:0.000000e+00 +%27 [496r,832r:0) 0@496r weight:0.000000e+00 +%28 [576r,576d:0) 0@576r weight:0.000000e+00 +%29 [656r,672r:0) 0@656r weight:0.000000e+00 +%30 [672r,672d:0) 0@672r weight:0.000000e+00 +%31 [752r,752d:0) 0@752r weight:0.000000e+00 +%32 [832r,832d:0) 0@832r weight:0.000000e+00 +%34 [928r,1136r:0) 0@928r weight:0.000000e+00 +%35 [944r,944d:0) 0@944r weight:0.000000e+00 +%36 [1024r,1040r:0) 0@1024r weight:0.000000e+00 +%37 [1040r,1040d:0) 0@1040r weight:0.000000e+00 +%38 [1120r,1120d:0) 0@1120r weight:0.000000e+00 +%39 [1200r,1232r:0) 0@1200r weight:0.000000e+00 +%40 [1232r,1248r:0) 0@1232r weight:0.000000e+00 +%41 [1328r,1344r:0) 0@1328r weight:0.000000e+00 +%43 [1296r,1312r:0) 0@1296r weight:0.000000e+00 +%44 [1392r,1664r:0) 0@1392r weight:0.000000e+00 +%45 [1408r,1408d:0) 0@1408r weight:0.000000e+00 +%46 [1488r,1504r:0) 0@1488r weight:0.000000e+00 +%47 [1504r,1504d:0) 0@1504r weight:0.000000e+00 +%48 [1584r,1584d:0) 0@1584r weight:0.000000e+00 +%49 [1664r,1664d:0) 0@1664r weight:0.000000e+00 +%50 [1744r,1760r:0) 0@1744r weight:0.000000e+00 +%51 [1808r,1824r:0) 0@1808r weight:0.000000e+00 +%52 [384r,432B:1)[432B,480r:2)[1824r,1888B:0) 0@1824r 1@384r 2@432B-phi weight:0.000000e+00 +%53 [400r,432B:1)[432B,464r:2)[1840r,1888B:0) 0@1840r 1@400r 2@432B-phi weight:0.000000e+00 +%54 [416r,432B:1)[432B,448r:2)[1856r,1888B:0) 0@1856r 1@416r 2@432B-phi weight:0.000000e+00 +%55 [960r,1008B:3)[1056r,1104B:2)[1136r,1184B:1)[1248r,1264B:0)[1264B,1280r:4) 0@1248r 1@1136r 2@1056r 3@960r 4@1264B-phi weight:0.000000e+00 +%56 [592r,640B:4)[688r,736B:3)[768r,816B:2)[848r,896B:1)[1344r,1360B:0)[1360B,1376r:5) 0@1344r 1@848r 2@768r 3@688r 4@592r 5@1360B-phi weight:0.000000e+00 +%57 [1424r,1472B:4)[1520r,1568B:3)[1600r,1648B:2)[1680r,1728B:1)[1760r,1776B:0)[1776B,1792r:5) 0@1760r 1@1680r 2@1600r 3@1520r 4@1424r 5@1776B-phi weight:0.000000e+00 +RegMasks: 112r 288r +BB_14: 0B 416B +BB_15: 432B 544B +BB_15: 560B 624B +BB_15: 640B 720B +BB_15: 736B 800B +BB_15: 816B 880B +BB_16: 896B 992B +BB_16: 1008B 1088B +BB_16: 1104B 1168B +BB_17: 1184B 1248B +BB_18: 1264B 1344B +BB_19: 1360B 1456B +BB_19: 1472B 1552B +BB_19: 1568B 1632B +BB_19: 1648B 1712B +BB_20: 1728B 1760B +BB_21: 1776B 1872B +BB_22: 1888B 1936B +CompareRefPairAlignments +CH [0B,32r:0)[368r,416r:4)[544r,592r:3)[720r,768r:2)[896r,944r:1) 0@0B-phi 1@896r 2@720r 3@544r 4@368r +CL [0B,32r:0)[368r,416r:4)[544r,592r:3)[720r,768r:2)[896r,944r:1) 0@0B-phi 1@896r 2@720r 3@544r 4@368r +DH [0B,48r:0)[352r,416r:4)[528r,592r:3)[704r,768r:2)[880r,944r:1) 0@0B-phi 1@880r 2@704r 3@528r 4@352r +DIL [0B,80r:0)[320r,416r:8)[496r,592r:7)[672r,768r:6)[848r,944r:5)[4432r,4448r:4)[4496r,4512r:3)[4560r,4576r:2)[4624r,4640r:1) 0@0B-phi 1@4624r 2@4560r 3@4496r 4@4432r 5@848r 6@672r 7@496r 8@320r +DIH [0B,80r:0)[320r,416r:8)[496r,592r:7)[672r,768r:6)[848r,944r:5)[4432r,4448r:4)[4496r,4512r:3)[4560r,4576r:2)[4624r,4640r:1) 0@0B-phi 1@4624r 2@4560r 3@4496r 4@4432r 5@848r 6@672r 7@496r 8@320r +DL [0B,48r:0)[352r,416r:4)[528r,592r:3)[704r,768r:2)[880r,944r:1) 0@0B-phi 1@880r 2@704r 3@528r 4@352r +HCX [0B,32r:0)[368r,416r:4)[544r,592r:3)[720r,768r:2)[896r,944r:1) 0@0B-phi 1@896r 2@720r 3@544r 4@368r +HDI [0B,80r:0)[320r,416r:8)[496r,592r:7)[672r,768r:6)[848r,944r:5)[4432r,4448r:4)[4496r,4512r:3)[4560r,4576r:2)[4624r,4640r:1) 0@0B-phi 1@4624r 2@4560r 3@4496r 4@4432r 5@848r 6@672r 7@496r 8@320r +HDX [0B,48r:0)[352r,416r:4)[528r,592r:3)[704r,768r:2)[880r,944r:1) 0@0B-phi 1@880r 2@704r 3@528r 4@352r +SIL [0B,64r:0)[336r,416r:4)[512r,592r:3)[688r,768r:2)[864r,944r:1) 0@0B-phi 1@864r 2@688r 3@512r 4@336r +SIH [0B,64r:0)[336r,416r:4)[512r,592r:3)[688r,768r:2)[864r,944r:1) 0@0B-phi 1@864r 2@688r 3@512r 4@336r +HSI [0B,64r:0)[336r,416r:4)[512r,592r:3)[688r,768r:2)[864r,944r:1) 0@0B-phi 1@864r 2@688r 3@512r 4@336r +R8B [0B,16r:0)[384r,416r:4)[560r,592r:3)[736r,768r:2)[912r,944r:1) 0@0B-phi 1@912r 2@736r 3@560r 4@384r +R8BH [0B,16r:0)[384r,416r:4)[560r,592r:3)[736r,768r:2)[912r,944r:1) 0@0B-phi 1@912r 2@736r 3@560r 4@384r +R8WH [0B,16r:0)[384r,416r:4)[560r,592r:3)[736r,768r:2)[912r,944r:1) 0@0B-phi 1@912r 2@736r 3@560r 4@384r +%16 [1776r,1824r:0) 0@1776r weight:0.000000e+00 +%17 [1760r,1808r:0) 0@1760r weight:0.000000e+00 +%18 [1744r,1888r:0) 0@1744r weight:0.000000e+00 +%19 [1728r,2064r:0) 0@1728r weight:0.000000e+00 +%20 [1712r,2000r:0) 0@1712r weight:0.000000e+00 +%22 [2112r,2512r:0) 0@2112r weight:0.000000e+00 +%23 [2096r,2496r:0) 0@2096r weight:0.000000e+00 +%27 [2624r,3072r:0) 0@2624r weight:0.000000e+00 +%28 [2608r,2656r:0) 0@2608r weight:0.000000e+00 +%29 [2592r,2800r:0) 0@2592r weight:0.000000e+00 +%30 [2576r,3088r:0) 0@2576r weight:0.000000e+00 +%35 [3280r,3728r:0) 0@3280r weight:0.000000e+00 +%36 [3264r,3312r:0) 0@3264r weight:0.000000e+00 +%37 [3248r,3456r:0) 0@3248r weight:0.000000e+00 +%38 [3232r,3744r:0) 0@3232r weight:0.000000e+00 +%43 [4016r,4064r:0) 0@4016r weight:0.000000e+00 +%44 [4000r,4048r:0) 0@4000r weight:0.000000e+00 +%45 [3984r,4160r:0) 0@3984r weight:0.000000e+00 +%46 [3968r,4128r:0) 0@3968r weight:0.000000e+00 +%47 [3952r,4272r:0) 0@3952r weight:0.000000e+00 +%50 [4384r,4400r:0) 0@4384r weight:0.000000e+00 +%51 [4368r,4400r:0) 0@4368r weight:0.000000e+00 +%52 [80r,96r:0) 0@80r weight:0.000000e+00 +%53 [96r,848r:0) 0@96r weight:0.000000e+00 +%54 [64r,112r:0) 0@64r weight:0.000000e+00 +%55 [112r,896r:0) 0@112r weight:0.000000e+00 +%56 [48r,128r:0) 0@48r weight:0.000000e+00 +%57 [128r,880r:0) 0@128r weight:0.000000e+00 +%58 [32r,144r:0) 0@32r weight:0.000000e+00 +%59 [144r,544r:0) 0@144r weight:0.000000e+00 +%60 [16r,160r:0) 0@16r weight:0.000000e+00 +%61 [160r,528r:0) 0@160r weight:0.000000e+00 +%62 [1072r,1120r:0) 0@1072r weight:0.000000e+00 +%63 [1056r,2288r:0)[2560B,3216B:0) 0@1056r weight:0.000000e+00 +%64 [1040r,1280r:0) 0@1040r weight:0.000000e+00 +%65 [1024r,4624r:0) 0@1024r weight:0.000000e+00 +%66 [1008r,4560r:0) 0@1008r weight:0.000000e+00 +%67 [992r,4496r:0) 0@992r weight:0.000000e+00 +%68 [976r,4432r:0) 0@976r weight:0.000000e+00 +%69 [800r,912r:0) 0@800r weight:0.000000e+00 +%70 [816r,928r:0) 0@816r weight:0.000000e+00 +%71 [624r,736r:0) 0@624r weight:0.000000e+00 +%72 [640r,752r:0) 0@640r weight:0.000000e+00 +%73 [448r,560r:0) 0@448r weight:0.000000e+00 +%74 [464r,576r:0) 0@464r weight:0.000000e+00 +%75 [272r,384r:0) 0@272r weight:0.000000e+00 +%76 [288r,400r:0) 0@288r weight:0.000000e+00 +%77 [256r,256d:0) 0@256r weight:0.000000e+00 +%78 [240r,240d:0) 0@240r weight:0.000000e+00 +%79 [224r,224d:0) 0@224r weight:0.000000e+00 +%80 [208r,208d:0) 0@208r weight:0.000000e+00 +%81 [192r,192d:0) 0@192r weight:0.000000e+00 +%82 [176r,176d:0) 0@176r weight:0.000000e+00 +%84 [1216r,1232r:0) 0@1216r weight:0.000000e+00 +%85 [1232r,1328r:0) 0@1232r weight:0.000000e+00 +%86 [1248r,1344r:0) 0@1248r weight:0.000000e+00 +%87 [1264r,1360r:0) 0@1264r weight:0.000000e+00 +%88 [1200r,1792r:0)[2560B,3216B:0) 0@1200r weight:0.000000e+00 +%89 [1168r,1184r:0) 0@1168r weight:0.000000e+00 +%90 [1184r,1424r:0) 0@1184r weight:0.000000e+00 +%91 [1440r,1456r:0) 0@1440r weight:0.000000e+00 +%92 [1456r,1536r:0) 0@1456r weight:0.000000e+00 +%93 [1472r,1520r:0) 0@1472r weight:0.000000e+00 +%94 [1408r,1424r:0) 0@1408r weight:0.000000e+00 +%95 [1424r,1568B:0)[2560B,3216B:0) 0@1424r weight:0.000000e+00 +%96 [3088r,3168r:0) 0@3088r weight:0.000000e+00 +%97 [1568B,1648r:0)[3072r,3216B:0) 0@3072r weight:0.000000e+00 +%102 [1568B,1680r:0)[3056r,3216B:0) 0@3056r weight:0.000000e+00 +%103 [2928r,2944r:0) 0@2928r weight:0.000000e+00 +%104 [2944r,2976r:0) 0@2944r weight:0.000000e+00 +%106 [2912r,2960r:0) 0@2912r weight:0.000000e+00 +%107 [2896r,2960r:0) 0@2896r weight:0.000000e+00 +%109 [2864r,2880r:0) 0@2864r weight:0.000000e+00 +%110 [1568B,1616r:0)[2880r,3216B:0) 0@2880r weight:0.000000e+00 +%111 [2848r,2912r:0) 0@2848r weight:0.000000e+00 +%115 [2832r,3024r:0) 0@2832r weight:0.000000e+00 +%116 [2704r,2720r:0) 0@2704r weight:0.000000e+00 +%117 [2720r,2752r:0) 0@2720r weight:0.000000e+00 +%118 [2688r,2736r:0) 0@2688r weight:0.000000e+00 +%119 [2672r,2736r:0) 0@2672r weight:0.000000e+00 +%120 [2640r,2656r:0) 0@2640r weight:0.000000e+00 +%121 [2656r,2880r:0) 0@2656r weight:0.000000e+00 +%122 [1584r,1600r:0) 0@1584r weight:0.000000e+00 +%123 [1600r,1664r:0) 0@1600r weight:0.000000e+00 +%127 [2032r,2048r:0) 0@2032r weight:0.000000e+00 +%128 [1904r,1920r:0) 0@1904r weight:0.000000e+00 +%129 [1920r,1952r:0) 0@1920r weight:0.000000e+00 +%130 [1888r,1936r:0) 0@1888r weight:0.000000e+00 +%131 [1872r,1936r:0) 0@1872r weight:0.000000e+00 +%133 [2256r,2272r:0) 0@2256r weight:0.000000e+00 +%134 [2272r,2336r:0) 0@2272r weight:0.000000e+00 +%135 [2240r,2560B:0)[3216B,4032r:0) 0@2240r weight:0.000000e+00 +%136 [2208r,2224r:0) 0@2208r weight:0.000000e+00 +%137 [2224r,2432r:0) 0@2224r weight:0.000000e+00 +%138 [2448r,2464r:0) 0@2448r weight:0.000000e+00 +%139 [2464r,2528r:0) 0@2464r weight:0.000000e+00 +%140 [2416r,2432r:0) 0@2416r weight:0.000000e+00 +%141 [2432r,2560B:0)[3216B,3936B:0) 0@2432r weight:0.000000e+00 +%142 [3744r,3824r:0) 0@3744r weight:0.000000e+00 +%143 [3728r,3872r:0) 0@3728r weight:0.000000e+00 +%148 [3712r,3904r:0) 0@3712r weight:0.000000e+00 +%149 [3584r,3600r:0) 0@3584r weight:0.000000e+00 +%150 [3600r,3632r:0) 0@3600r weight:0.000000e+00 +%152 [3568r,3616r:0) 0@3568r weight:0.000000e+00 +%153 [3552r,3616r:0) 0@3552r weight:0.000000e+00 +%155 [3520r,3536r:0) 0@3520r weight:0.000000e+00 +%156 [3536r,3888r:0) 0@3536r weight:0.000000e+00 +%157 [3504r,3568r:0) 0@3504r weight:0.000000e+00 +%161 [3488r,3680r:0) 0@3488r weight:0.000000e+00 +%162 [3360r,3376r:0) 0@3360r weight:0.000000e+00 +%163 [3376r,3408r:0) 0@3376r weight:0.000000e+00 +%164 [3344r,3392r:0) 0@3344r weight:0.000000e+00 +%165 [3328r,3392r:0) 0@3328r weight:0.000000e+00 +%166 [3296r,3312r:0) 0@3296r weight:0.000000e+00 +%167 [3312r,3536r:0) 0@3312r weight:0.000000e+00 +%171 [4304r,4320r:0) 0@4304r weight:0.000000e+00 +%172 [4176r,4192r:0) 0@4176r weight:0.000000e+00 +%173 [4192r,4224r:0) 0@4192r weight:0.000000e+00 +%174 [4160r,4208r:0) 0@4160r weight:0.000000e+00 +%175 [4144r,4208r:0) 0@4144r weight:0.000000e+00 +%176 [4112r,4128r:0) 0@4112r weight:0.000000e+00 +%177 [4128r,4336r:0) 0@4128r weight:0.000000e+00 +%183 [4400r,4672r:0) 0@4400r weight:0.000000e+00 +%184 [1296r,1392B:1)[1616r,1696B:0)[1696B,1776r:2) 0@1616r 1@1296r 2@1696B-phi weight:0.000000e+00 +%185 [1312r,1392B:1)[1632r,1696B:0)[1696B,1760r:2) 0@1632r 1@1312r 2@1696B-phi weight:0.000000e+00 +%186 [1328r,1392B:1)[1648r,1696B:0)[1696B,1744r:2) 0@1648r 1@1328r 2@1696B-phi weight:0.000000e+00 +%187 [1344r,1392B:1)[1664r,1696B:0)[1696B,1728r:2) 0@1664r 1@1344r 2@1696B-phi weight:0.000000e+00 +%188 [1360r,1392B:1)[1680r,1696B:0)[1696B,1712r:2) 0@1680r 1@1360r 2@1696B-phi weight:0.000000e+00 +%189 [1952r,1984B:1)[2000r,2016B:0)[2016B,2032r:2) 0@2000r 1@1952r 2@2016B-phi weight:0.000000e+00 +%190 [1104r,1152B:2)[1808r,1856B:1)[2048r,2080B:0)[2080B,2112r:3) 0@2048r 1@1808r 2@1104r 3@2080B-phi weight:0.000000e+00 +%191 [1120r,1152B:2)[1824r,1856B:1)[2064r,2080B:0)[2080B,2096r:3) 0@2064r 1@1824r 2@1120r 3@2080B-phi weight:0.000000e+00 +%192 [1488r,1568B:1)[2560B,2624r:2)[3120r,3216B:0) 0@3120r 1@1488r 2@2560B-phi weight:0.000000e+00 +%193 [1504r,1568B:1)[2560B,2608r:2)[3136r,3216B:0) 0@3136r 1@1504r 2@2560B-phi weight:0.000000e+00 +%194 [1520r,1568B:1)[2560B,2592r:2)[3152r,3216B:0) 0@3152r 1@1520r 2@2560B-phi weight:0.000000e+00 +%195 [1536r,1568B:1)[2560B,2576r:2)[3168r,3216B:0) 0@3168r 1@1536r 2@2560B-phi weight:0.000000e+00 +%196 [2752r,2784B:1)[2800r,2816B:0)[2816B,2832r:2) 0@2800r 1@2752r 2@2816B-phi weight:0.000000e+00 +%197 [2976r,3008B:1)[3024r,3040B:0)[3040B,3056r:2) 0@3024r 1@2976r 2@3040B-phi weight:0.000000e+00 +%198 [2480r,2560B:1)[3216B,3280r:2)[3776r,3936B:0) 0@3776r 1@2480r 2@3216B-phi weight:0.000000e+00 +%199 [2496r,2560B:1)[3216B,3264r:2)[3792r,3936B:0) 0@3792r 1@2496r 2@3216B-phi weight:0.000000e+00 +%200 [2512r,2560B:1)[3216B,3248r:2)[3808r,3936B:0) 0@3808r 1@2512r 2@3216B-phi weight:0.000000e+00 +%201 [2528r,2560B:1)[3216B,3232r:2)[3824r,3936B:0) 0@3824r 1@2528r 2@3216B-phi weight:0.000000e+00 +%202 [3408r,3440B:1)[3456r,3472B:0)[3472B,3488r:2) 0@3456r 1@3408r 2@3472B-phi weight:0.000000e+00 +%203 [3632r,3664B:1)[3680r,3696B:0)[3696B,3712r:2) 0@3680r 1@3632r 2@3696B-phi weight:0.000000e+00 +%204 [2304r,2400B:1)[3840r,3936B:0)[3936B,4016r:2) 0@3840r 1@2304r 2@3936B-phi weight:0.000000e+00 +%205 [2320r,2400B:1)[3856r,3936B:0)[3936B,4000r:2) 0@3856r 1@2320r 2@3936B-phi weight:0.000000e+00 +%206 [2336r,2400B:1)[3872r,3936B:0)[3936B,3984r:2) 0@3872r 1@2336r 2@3936B-phi weight:0.000000e+00 +%207 [2352r,2400B:1)[3888r,3936B:0)[3936B,3968r:2) 0@3888r 1@2352r 2@3936B-phi weight:0.000000e+00 +%208 [2368r,2400B:1)[3904r,3936B:0)[3936B,3952r:2) 0@3904r 1@2368r 2@3936B-phi weight:0.000000e+00 +%209 [4224r,4256B:1)[4272r,4288B:0)[4288B,4304r:2) 0@4272r 1@4224r 2@4288B-phi weight:0.000000e+00 +%210 [2144r,2192B:2)[4048r,4096B:1)[4320r,4352B:0)[4352B,4384r:3) 0@4320r 1@4048r 2@2144r 3@4352B-phi weight:0.000000e+00 +%211 [2160r,2192B:2)[4064r,4096B:1)[4336r,4352B:0)[4352B,4368r:3) 0@4336r 1@4064r 2@2160r 3@4352B-phi weight:0.000000e+00 +RegMasks: 416r 592r 768r 944r 4448r 4512r 4576r 4640r +BB_23: 0B 1136B +BB_24: 1152B 1376B +BB_25: 1392B 1552B +BB_26: 1568B 1680B +BB_27: 1696B 1840B +BB_28: 1856B 1968B +BB_28: 1984B 2000B +BB_28: 2016B 2064B +BB_29: 2080B 2176B +BB_30: 2192B 2384B +BB_31: 2400B 2544B +BB_32: 2560B 2768B +BB_32: 2784B 2800B +BB_32: 2816B 2992B +BB_32: 3008B 3024B +BB_32: 3040B 3200B +BB_33: 3216B 3424B +BB_33: 3440B 3456B +BB_33: 3472B 3648B +BB_33: 3664B 3680B +BB_33: 3696B 3920B +BB_34: 3936B 4080B +BB_35: 4096B 4240B +BB_35: 4256B 4272B +BB_35: 4288B 4336B +BB_36: 4352B 4688B +make_ref_alilist +CH [0B,48r:0) 0@0B-phi +CL [0B,48r:0) 0@0B-phi +DH [0B,64r:0)[304r,320r:2)[560r,576r:1) 0@0B-phi 1@560r 2@304r +DIL [0B,96r:0)[128r,144r:5)[272r,320r:4)[384r,400r:3)[528r,576r:2)[3680r,3696r:1) 0@0B-phi 1@3680r 2@528r 3@384r 4@272r 5@128r +DIH [0B,96r:0)[128r,144r:5)[272r,320r:4)[384r,400r:3)[528r,576r:2)[3680r,3696r:1) 0@0B-phi 1@3680r 2@528r 3@384r 4@272r 5@128r +DL [0B,64r:0)[304r,320r:2)[560r,576r:1) 0@0B-phi 1@560r 2@304r +HCX [0B,48r:0) 0@0B-phi +HDI [0B,96r:0)[128r,144r:5)[272r,320r:4)[384r,400r:3)[528r,576r:2)[3680r,3696r:1) 0@0B-phi 1@3680r 2@528r 3@384r 4@272r 5@128r +HDX [0B,64r:0)[304r,320r:2)[560r,576r:1) 0@0B-phi 1@560r 2@304r +SIL [0B,80r:0)[288r,320r:2)[544r,576r:1) 0@0B-phi 1@544r 2@288r +SIH [0B,80r:0)[288r,320r:2)[544r,576r:1) 0@0B-phi 1@544r 2@288r +HSI [0B,80r:0)[288r,320r:2)[544r,576r:1) 0@0B-phi 1@544r 2@288r +R8B [0B,32r:0) 0@0B-phi +R8BH [0B,32r:0) 0@0B-phi +R8WH [0B,32r:0) 0@0B-phi +R9B [0B,16r:0) 0@0B-phi +R9BH [0B,16r:0) 0@0B-phi +R9WH [0B,16r:0) 0@0B-phi +%3 [736r,1152B:0)[1296B,1472r:0) 0@736r weight:0.000000e+00 +%4 [720r,1152B:0)[1296B,1408r:0) 0@720r weight:0.000000e+00 +%7 [1456r,1504r:0) 0@1456r weight:0.000000e+00 +%9 [1600r,3552r:0) 0@1600r weight:0.000000e+00 +%10 [1584r,3072r:0) 0@1584r weight:0.000000e+00 +%11 [1568r,3488r:0) 0@1568r weight:0.000000e+00 +%12 [1552r,2624r:0)[3648B,3728r:0) 0@1552r weight:0.000000e+00 +%13 [1616r,2640r:0) 0@1616r weight:0.000000e+00 +%14 [1632r,2144r:0) 0@1632r weight:0.000000e+00 +%15 [2208r,2512r:0) 0@2208r weight:0.000000e+00 +%17 [2576r,2608r:0) 0@2576r weight:0.000000e+00 +%20 [2720r,2992r:0) 0@2720r weight:0.000000e+00 +%21 [2704r,3616r:0) 0@2704r weight:0.000000e+00 +%23 [3120r,3584r:0) 0@3120r weight:0.000000e+00 +%25 [3536r,3600r:0) 0@3536r weight:0.000000e+00 +%27 [96r,1152B:0)[1296B,1536B:0) 0@96r weight:0.000000e+00 +%28 [80r,1152B:0)[1296B,1536B:0) 0@80r weight:0.000000e+00 +%29 [64r,3648B:0) 0@64r weight:0.000000e+00 +%30 [48r,3648B:0) 0@48r weight:0.000000e+00 +%31 [32r,3744r:0) 0@32r weight:0.000000e+00 +%32 [16r,3728r:0) 0@16r weight:0.000000e+00 +%33 [624r,640r:0) 0@624r weight:0.000000e+00 +%34 [640r,672r:0) 0@640r weight:0.000000e+00 +%35 [656r,688r:0) 0@656r weight:0.000000e+00 +%36 [480r,528r:0) 0@480r weight:0.000000e+00 +%37 [496r,544r:0) 0@496r weight:0.000000e+00 +%39 [608r,3680r:0) 0@608r weight:0.000000e+00 +%40 [448r,464r:0) 0@448r weight:0.000000e+00 +%41 [464r,560r:0) 0@464r weight:0.000000e+00 +%42 [432r,448r:0) 0@432r weight:0.000000e+00 +%43 [224r,272r:0) 0@224r weight:0.000000e+00 +%44 [240r,288r:0) 0@240r weight:0.000000e+00 +%46 [352r,3744r:0) 0@352r weight:0.000000e+00 +%47 [192r,208r:0) 0@192r weight:0.000000e+00 +%48 [208r,304r:0) 0@208r weight:0.000000e+00 +%49 [176r,192r:0) 0@176r weight:0.000000e+00 +%50 [752r,1088r:0) 0@752r weight:0.000000e+00 +%51 [832r,832d:0) 0@832r weight:0.000000e+00 +%52 [912r,928r:0) 0@912r weight:0.000000e+00 +%53 [928r,928d:0) 0@928r weight:0.000000e+00 +%54 [1008r,1008d:0) 0@1008r weight:0.000000e+00 +%55 [1088r,1088d:0) 0@1088r weight:0.000000e+00 +%56 [1168r,1184r:0) 0@1168r weight:0.000000e+00 +%57 [1184r,1216r:0) 0@1184r weight:0.000000e+00 +%58 [1200r,1264r:0) 0@1200r weight:0.000000e+00 +%59 [1712r,1712d:0) 0@1712r weight:0.000000e+00 +%60 [1808r,1824r:0) 0@1808r weight:0.000000e+00 +%61 [1824r,1824d:0) 0@1824r weight:0.000000e+00 +%62 [1920r,1920d:0) 0@1920r weight:0.000000e+00 +%63 [2016r,2016d:0) 0@2016r weight:0.000000e+00 +%66 [2112r,2128r:0) 0@2112r weight:0.000000e+00 +%68 [2224r,2432r:0) 0@2224r weight:0.000000e+00 +%69 [2240r,2240d:0) 0@2240r weight:0.000000e+00 +%70 [2320r,2336r:0) 0@2320r weight:0.000000e+00 +%71 [2336r,2336d:0) 0@2336r weight:0.000000e+00 +%72 [2416r,2416d:0) 0@2416r weight:0.000000e+00 +%73 [2496r,2528r:0) 0@2496r weight:0.000000e+00 +%74 [2528r,2544r:0) 0@2528r weight:0.000000e+00 +%75 [2640r,2656r:0) 0@2640r weight:0.000000e+00 +%76 [2624r,2672r:0) 0@2624r weight:0.000000e+00 +%78 [2592r,2608r:0) 0@2592r weight:0.000000e+00 +%79 [2736r,2736d:0) 0@2736r weight:0.000000e+00 +%80 [2816r,2832r:0) 0@2816r weight:0.000000e+00 +%81 [2832r,2832d:0) 0@2832r weight:0.000000e+00 +%82 [2912r,2912d:0) 0@2912r weight:0.000000e+00 +%83 [2992r,2992d:0) 0@2992r weight:0.000000e+00 +%84 [3072r,3088r:0) 0@3072r weight:0.000000e+00 +%85 [3136r,3408r:0) 0@3136r weight:0.000000e+00 +%86 [3152r,3152d:0) 0@3152r weight:0.000000e+00 +%87 [3232r,3248r:0) 0@3232r weight:0.000000e+00 +%88 [3248r,3248d:0) 0@3248r weight:0.000000e+00 +%89 [3328r,3328d:0) 0@3328r weight:0.000000e+00 +%90 [3408r,3408d:0) 0@3408r weight:0.000000e+00 +%91 [3488r,3504r:0) 0@3488r weight:0.000000e+00 +%92 [3552r,3568r:0) 0@3552r weight:0.000000e+00 +%93 [1408r,1424r:0) 0@1408r weight:0.000000e+00 +%96 [1376r,1392r:0) 0@1376r weight:0.000000e+00 +%98 [1344r,1360r:0) 0@1344r weight:0.000000e+00 +%99 [1360r,1392r:0) 0@1360r weight:0.000000e+00 +%100 [1328r,1344r:0) 0@1328r weight:0.000000e+00 +%102 [1472r,1488r:0) 0@1472r weight:0.000000e+00 +%103 [672r,704B:1)[704B,736r:2)[1488r,1536B:0) 0@1488r 1@672r 2@704B-phi weight:0.000000e+00 +%104 [688r,704B:1)[704B,720r:2)[1504r,1536B:0) 0@1504r 1@688r 2@704B-phi weight:0.000000e+00 +%105 [848r,896B:4)[944r,992B:3)[1024r,1072B:2)[1104r,1152B:1)[1424r,1440B:0)[1440B,1456r:5) 0@1424r 1@1104r 2@1024r 3@944r 4@848r 5@1440B-phi weight:0.000000e+00 +%106 [1216r,1296B:1)[1536B,1600r:2)[3568r,3648B:0) 0@3568r 1@1216r 2@1536B-phi weight:0.000000e+00 +%107 [1232r,1296B:1)[1536B,1584r:2)[3584r,3648B:0) 0@3584r 1@1232r 2@1536B-phi weight:0.000000e+00 +%108 [1248r,1296B:1)[1536B,1568r:2)[3600r,3648B:0) 0@3600r 1@1248r 2@1536B-phi weight:0.000000e+00 +%109 [1264r,1296B:1)[1536B,1552r:2)[3616r,3648B:0) 0@3616r 1@1264r 2@1536B-phi weight:0.000000e+00 +%110 [2256r,2304B:3)[2352r,2400B:2)[2432r,2480B:1)[2544r,2560B:0)[2560B,2576r:4) 0@2544r 1@2432r 2@2352r 3@2256r 4@2560B-phi weight:0.000000e+00 +%111 [1728r,1792B:5)[1840r,1904B:4)[1936r,2000B:3)[2032r,2096B:2)[2144r,2192B:1)[2656r,2688B:0)[2688B,2720r:6) 0@2656r 1@2144r 2@2032r 3@1936r 4@1840r 5@1728r 6@2688B-phi weight:0.000000e+00 +%112 [1744r,1792B:5)[1856r,1904B:4)[1952r,2000B:3)[2048r,2096B:2)[2160r,2192B:1)[2672r,2688B:0)[2688B,2704r:6) 0@2672r 1@2160r 2@2048r 3@1952r 4@1856r 5@1744r 6@2688B-phi weight:0.000000e+00 +%113 [2752r,2800B:4)[2848r,2896B:3)[2928r,2976B:2)[3008r,3056B:1)[3088r,3104B:0)[3104B,3120r:5) 0@3088r 1@3008r 2@2928r 3@2848r 4@2752r 5@3104B-phi weight:0.000000e+00 +%114 [3168r,3216B:4)[3264r,3312B:3)[3344r,3392B:2)[3424r,3472B:1)[3504r,3520B:0)[3520B,3536r:5) 0@3504r 1@3424r 2@3344r 3@3264r 4@3168r 5@3520B-phi weight:0.000000e+00 +RegMasks: 144r 320r 400r 576r 3696r +BB_37: 0B 688B +BB_38: 704B 800B +BB_38: 816B 880B +BB_38: 896B 976B +BB_38: 992B 1056B +BB_38: 1072B 1136B +BB_39: 1152B 1280B +BB_40: 1296B 1424B +BB_41: 1440B 1520B +BB_42: 1536B 1680B +BB_42: 1696B 1776B +BB_42: 1792B 1888B +BB_42: 1904B 1984B +BB_42: 2000B 2080B +BB_43: 2096B 2176B +BB_44: 2192B 2288B +BB_44: 2304B 2384B +BB_44: 2400B 2464B +BB_45: 2480B 2544B +BB_46: 2560B 2672B +BB_47: 2688B 2784B +BB_47: 2800B 2880B +BB_47: 2896B 2960B +BB_47: 2976B 3040B +BB_48: 3056B 3088B +BB_49: 3104B 3200B +BB_49: 3216B 3296B +BB_49: 3312B 3376B +BB_49: 3392B 3456B +BB_50: 3472B 3504B +BB_51: 3520B 3632B +BB_52: 3648B 3760B +CompareMultAlignments +DH [0B,16r:0)[928r,960r:1) 0@0B-phi 1@928r +DIL [0B,48r:0)[896r,960r:1) 0@0B-phi 1@896r +DIH [0B,48r:0)[896r,960r:1) 0@0B-phi 1@896r +DL [0B,16r:0)[928r,960r:1) 0@0B-phi 1@928r +HDI [0B,48r:0)[896r,960r:1) 0@0B-phi 1@896r +HDX [0B,16r:0)[928r,960r:1) 0@0B-phi 1@928r +SIL [0B,32r:0)[912r,960r:1) 0@0B-phi 1@912r +SIH [0B,32r:0)[912r,960r:1) 0@0B-phi 1@912r +HSI [0B,32r:0)[912r,960r:1) 0@0B-phi 1@912r +%2 [400r,496r:0) 0@400r weight:0.000000e+00 +%4 [576r,704r:0) 0@576r weight:0.000000e+00 +%5 [384B,416r:0)[560r,1232B:0) 0@560r weight:0.000000e+00 +%6 [544r,752r:0) 0@544r weight:0.000000e+00 +%10 [800r,1120r:0) 0@800r weight:0.000000e+00 +%11 [784r,1104r:0) 0@784r weight:0.000000e+00 +%15 [1248r,1264r:0) 0@1248r weight:0.000000e+00 +%17 [1456r,1472r:0) 0@1456r weight:0.000000e+00 +%18 [48r,64r:0) 0@48r weight:0.000000e+00 +%19 [64r,1232B:0) 0@64r weight:0.000000e+00 +%20 [32r,80r:0) 0@32r weight:0.000000e+00 +%21 [80r,1232B:0) 0@80r weight:0.000000e+00 +%22 [16r,96r:0) 0@16r weight:0.000000e+00 +%23 [96r,1312r:0) 0@96r weight:0.000000e+00 +%24 [112r,144r:0) 0@112r weight:0.000000e+00 +%25 [256r,272r:0) 0@256r weight:0.000000e+00 +%26 [272r,320r:0) 0@272r weight:0.000000e+00 +%27 [288r,336r:0) 0@288r weight:0.000000e+00 +%28 [304r,352r:0) 0@304r weight:0.000000e+00 +%29 [224r,240r:0) 0@224r weight:0.000000e+00 +%30 [240r,1232B:0) 0@240r weight:0.000000e+00 +%31 [192r,208r:0) 0@192r weight:0.000000e+00 +%32 [208r,1232B:0) 0@208r weight:0.000000e+00 +%33 [384B,448r:0)[592r,1232B:0) 0@592r weight:0.000000e+00 +%34 [704r,720r:0) 0@704r weight:0.000000e+00 +%35 [720r,1232B:0) 0@720r weight:0.000000e+00 +%36 [672r,688r:0) 0@672r weight:0.000000e+00 +%37 [688r,1232B:0) 0@688r weight:0.000000e+00 +%38 [1008r,1056r:0) 0@1008r weight:0.000000e+00 +%39 [1024r,1040r:0) 0@1024r weight:0.000000e+00 +%44 [992r,1104r:0) 0@992r weight:0.000000e+00 +%45 [864r,944r:0) 0@864r weight:0.000000e+00 +%46 [848r,928r:0) 0@848r weight:0.000000e+00 +%47 [832r,912r:0) 0@832r weight:0.000000e+00 +%48 [816r,896r:0) 0@816r weight:0.000000e+00 +%49 [1120r,1168r:0) 0@1120r weight:0.000000e+00 +%50 [1104r,1184r:0) 0@1104r weight:0.000000e+00 +%51 [416r,464r:0) 0@416r weight:0.000000e+00 +%53 [1408r,1424r:0) 0@1408r weight:0.000000e+00 +%56 [1392r,1408r:0) 0@1392r weight:0.000000e+00 +%59 [1376r,1392r:0) 0@1376r weight:0.000000e+00 +%60 [1344r,1360r:0) 0@1344r weight:0.000000e+00 +%61 [1360r,1376r:0) 0@1360r weight:0.000000e+00 +%63 [1328r,1376r:0) 0@1328r weight:0.000000e+00 +%64 [1312r,1328r:0) 0@1312r weight:0.000000e+00 +%66 [1280r,1296r:0) 0@1280r weight:0.000000e+00 +%67 [1296r,1392r:0) 0@1296r weight:0.000000e+00 +%68 [1264r,1296r:0) 0@1264r weight:0.000000e+00 +%69 [384B,400r:2)[624r,656B:1)[1152r,1232B:0) 0@1152r 1@624r 2@384B-phi weight:0.000000e+00 +%70 [320r,384B:1)[448r,528B:0)[528B,576r:2) 0@448r 1@320r 2@528B-phi weight:0.000000e+00 +%71 [336r,384B:1)[464r,528B:0)[528B,560r:2) 0@464r 1@336r 2@528B-phi weight:0.000000e+00 +%72 [352r,384B:1)[480r,528B:0)[528B,544r:2) 0@480r 1@352r 2@528B-phi weight:0.000000e+00 +%73 [736r,768B:1)[768B,800r:2)[1168r,1232B:0) 0@1168r 1@736r 2@768B-phi weight:0.000000e+00 +%74 [752r,768B:1)[768B,784r:2)[1184r,1232B:0) 0@1184r 1@752r 2@768B-phi weight:0.000000e+00 +%75 [144r,176B:1)[496r,528B:0)[1232B,1248r:2) 0@496r 1@144r 2@1232B-phi weight:0.000000e+00 +%76 [1056r,1088B:1)[1424r,1440B:0)[1440B,1456r:2) 0@1424r 1@1056r 2@1440B-phi weight:0.000000e+00 +RegMasks: 960r +BB_53: 0B 160B +BB_54: 176B 368B +BB_55: 384B 512B +BB_56: 528B 640B +BB_57: 656B 752B +BB_58: 768B 1072B +BB_59: 1088B 1216B +BB_60: 1232B 1424B +BB_61: 1440B 1488B +CompareRefMultAlignments +CH [0B,16r:0)[976r,1008r:1) 0@0B-phi 1@976r +CL [0B,16r:0)[976r,1008r:1) 0@0B-phi 1@976r +DH [0B,32r:0)[960r,1008r:1) 0@0B-phi 1@960r +DIL [0B,64r:0)[928r,1008r:1) 0@0B-phi 1@928r +DIH [0B,64r:0)[928r,1008r:1) 0@0B-phi 1@928r +DL [0B,32r:0)[960r,1008r:1) 0@0B-phi 1@960r +HCX [0B,16r:0)[976r,1008r:1) 0@0B-phi 1@976r +HDI [0B,64r:0)[928r,1008r:1) 0@0B-phi 1@928r +HDX [0B,32r:0)[960r,1008r:1) 0@0B-phi 1@960r +SIL [0B,48r:0)[944r,1008r:1) 0@0B-phi 1@944r +SIH [0B,48r:0)[944r,1008r:1) 0@0B-phi 1@944r +HSI [0B,48r:0)[944r,1008r:1) 0@0B-phi 1@944r +%2 [432r,528r:0) 0@432r weight:0.000000e+00 +%4 [608r,736r:0) 0@608r weight:0.000000e+00 +%5 [416B,448r:0)[592r,1280B:0) 0@592r weight:0.000000e+00 +%6 [576r,784r:0) 0@576r weight:0.000000e+00 +%10 [832r,1168r:0) 0@832r weight:0.000000e+00 +%11 [816r,1152r:0) 0@816r weight:0.000000e+00 +%15 [1296r,1312r:0) 0@1296r weight:0.000000e+00 +%17 [1504r,1520r:0) 0@1504r weight:0.000000e+00 +%18 [64r,80r:0) 0@64r weight:0.000000e+00 +%19 [80r,1280B:0) 0@80r weight:0.000000e+00 +%20 [48r,96r:0) 0@48r weight:0.000000e+00 +%21 [96r,1280B:0) 0@96r weight:0.000000e+00 +%22 [32r,112r:0) 0@32r weight:0.000000e+00 +%23 [112r,1280B:0) 0@112r weight:0.000000e+00 +%24 [16r,128r:0) 0@16r weight:0.000000e+00 +%25 [128r,1360r:0) 0@128r weight:0.000000e+00 +%26 [144r,176r:0) 0@144r weight:0.000000e+00 +%27 [288r,304r:0) 0@288r weight:0.000000e+00 +%28 [304r,352r:0) 0@304r weight:0.000000e+00 +%29 [320r,368r:0) 0@320r weight:0.000000e+00 +%30 [336r,384r:0) 0@336r weight:0.000000e+00 +%31 [256r,272r:0) 0@256r weight:0.000000e+00 +%32 [272r,1280B:0) 0@272r weight:0.000000e+00 +%33 [224r,240r:0) 0@224r weight:0.000000e+00 +%34 [240r,1280B:0) 0@240r weight:0.000000e+00 +%35 [416B,480r:0)[624r,1280B:0) 0@624r weight:0.000000e+00 +%36 [736r,752r:0) 0@736r weight:0.000000e+00 +%37 [752r,1280B:0) 0@752r weight:0.000000e+00 +%38 [704r,720r:0) 0@704r weight:0.000000e+00 +%39 [720r,1280B:0) 0@720r weight:0.000000e+00 +%40 [1056r,1104r:0) 0@1056r weight:0.000000e+00 +%41 [1072r,1088r:0) 0@1072r weight:0.000000e+00 +%46 [1040r,1152r:0) 0@1040r weight:0.000000e+00 +%47 [896r,992r:0) 0@896r weight:0.000000e+00 +%48 [880r,976r:0) 0@880r weight:0.000000e+00 +%49 [864r,960r:0) 0@864r weight:0.000000e+00 +%50 [848r,944r:0) 0@848r weight:0.000000e+00 +%51 [1168r,1216r:0) 0@1168r weight:0.000000e+00 +%52 [1152r,1232r:0) 0@1152r weight:0.000000e+00 +%53 [448r,496r:0) 0@448r weight:0.000000e+00 +%55 [1456r,1472r:0) 0@1456r weight:0.000000e+00 +%58 [1440r,1456r:0) 0@1440r weight:0.000000e+00 +%61 [1424r,1440r:0) 0@1424r weight:0.000000e+00 +%62 [1392r,1408r:0) 0@1392r weight:0.000000e+00 +%63 [1408r,1424r:0) 0@1408r weight:0.000000e+00 +%65 [1376r,1424r:0) 0@1376r weight:0.000000e+00 +%66 [1360r,1376r:0) 0@1360r weight:0.000000e+00 +%68 [1328r,1344r:0) 0@1328r weight:0.000000e+00 +%69 [1344r,1440r:0) 0@1344r weight:0.000000e+00 +%70 [1312r,1344r:0) 0@1312r weight:0.000000e+00 +%71 [416B,432r:2)[656r,688B:1)[1200r,1280B:0) 0@1200r 1@656r 2@416B-phi weight:0.000000e+00 +%72 [352r,416B:1)[480r,560B:0)[560B,608r:2) 0@480r 1@352r 2@560B-phi weight:0.000000e+00 +%73 [368r,416B:1)[496r,560B:0)[560B,592r:2) 0@496r 1@368r 2@560B-phi weight:0.000000e+00 +%74 [384r,416B:1)[512r,560B:0)[560B,576r:2) 0@512r 1@384r 2@560B-phi weight:0.000000e+00 +%75 [768r,800B:1)[800B,832r:2)[1216r,1280B:0) 0@1216r 1@768r 2@800B-phi weight:0.000000e+00 +%76 [784r,800B:1)[800B,816r:2)[1232r,1280B:0) 0@1232r 1@784r 2@800B-phi weight:0.000000e+00 +%77 [176r,208B:1)[528r,560B:0)[1280B,1296r:2) 0@528r 1@176r 2@1280B-phi weight:0.000000e+00 +%78 [1104r,1136B:1)[1472r,1488B:0)[1488B,1504r:2) 0@1472r 1@1104r 2@1488B-phi weight:0.000000e+00 +RegMasks: 1008r +BB_62: 0B 192B +BB_63: 208B 400B +BB_64: 416B 544B +BB_65: 560B 672B +BB_66: 688B 784B +BB_67: 800B 1120B +BB_68: 1136B 1264B +BB_69: 1280B 1472B +BB_70: 1488B 1536B +PairwiseIdentity +DIL [0B,32r:0) 0@0B-phi +DIH [0B,32r:0) 0@0B-phi +HDI [0B,32r:0) 0@0B-phi +SIL [0B,16r:0) 0@0B-phi +SIH [0B,16r:0) 0@0B-phi +HSI [0B,16r:0) 0@0B-phi +%1 [384r,1504r:0) 0@384r weight:0.000000e+00 +%2 [368r,928r:0) 0@368r weight:0.000000e+00 +%3 [352r,1424r:0) 0@352r weight:0.000000e+00 +%4 [336r,912r:0) 0@336r weight:0.000000e+00 +%5 [320r,992r:0) 0@320r weight:0.000000e+00 +%9 [1072r,1616r:0) 0@1072r weight:0.000000e+00 +%10 [1056r,1632r:0) 0@1056r weight:0.000000e+00 +%12 [1472r,1648r:0) 0@1472r weight:0.000000e+00 +%15 [1728r,1856r:0) 0@1728r weight:0.000000e+00 +%16 [1712r,1760r:0) 0@1712r weight:0.000000e+00 +%17 [1696r,1760r:0) 0@1696r weight:0.000000e+00 +%20 [1936r,1952r:0) 0@1936r weight:0.000000e+00 +%21 [32r,48r:0) 0@32r weight:0.000000e+00 +%22 [48r,1680B:0) 0@48r weight:0.000000e+00 +%23 [16r,64r:0) 0@16r weight:0.000000e+00 +%24 [64r,1680B:0) 0@64r weight:0.000000e+00 +%25 [96r,272r:0) 0@96r weight:0.000000e+00 +%26 [112r,128r:0) 0@112r weight:0.000000e+00 +%27 [128r,160r:0) 0@128r weight:0.000000e+00 +%28 [80r,176r:0) 0@80r weight:0.000000e+00 +%29 [400r,1344r:0) 0@400r weight:0.000000e+00 +%30 [512r,512d:0) 0@512r weight:0.000000e+00 +%31 [608r,624r:0) 0@608r weight:0.000000e+00 +%32 [624r,624d:0) 0@624r weight:0.000000e+00 +%33 [720r,720d:0) 0@720r weight:0.000000e+00 +%34 [816r,816d:0) 0@816r weight:0.000000e+00 +%36 [992r,1008r:0) 0@992r weight:0.000000e+00 +%38 [960r,976r:0) 0@960r weight:0.000000e+00 +%39 [976r,992r:0) 0@976r weight:0.000000e+00 +%40 [944r,960r:0) 0@944r weight:0.000000e+00 +%41 [912r,1024r:0) 0@912r weight:0.000000e+00 +%42 [1088r,1088d:0) 0@1088r weight:0.000000e+00 +%43 [1168r,1184r:0) 0@1168r weight:0.000000e+00 +%44 [1184r,1184d:0) 0@1184r weight:0.000000e+00 +%45 [1264r,1264d:0) 0@1264r weight:0.000000e+00 +%46 [1344r,1344d:0) 0@1344r weight:0.000000e+00 +%47 [1424r,1440r:0) 0@1424r weight:0.000000e+00 +%48 [1504r,1552r:0) 0@1504r weight:0.000000e+00 +%49 [1488r,1536r:0) 0@1488r weight:0.000000e+00 +%50 [1776r,1808r:0) 0@1776r weight:0.000000e+00 +%51 [1760r,1872r:0) 0@1760r weight:0.000000e+00 +%54 [1888r,1904r:0) 0@1888r weight:0.000000e+00 +%55 [1872r,1888r:0) 0@1872r weight:0.000000e+00 +%56 [1856r,1888r:0) 0@1856r weight:0.000000e+00 +%57 [160r,304B:1)[304B,384r:2)[1536r,1680B:0) 0@1536r 1@160r 2@304B-phi weight:0.000000e+00 +%58 [176r,304B:1)[304B,368r:2)[1552r,1680B:0) 0@1552r 1@176r 2@304B-phi weight:0.000000e+00 +%59 [192r,304B:1)[304B,352r:2)[1568r,1680B:0) 0@1568r 1@192r 2@304B-phi weight:0.000000e+00 +%60 [208r,304B:1)[304B,336r:2)[1584r,1680B:0) 0@1584r 1@208r 2@304B-phi weight:0.000000e+00 +%61 [224r,304B:1)[304B,320r:2)[1600r,1680B:0) 0@1600r 1@224r 2@304B-phi weight:0.000000e+00 +%62 [528r,592B:4)[640r,704B:3)[736r,800B:2)[832r,896B:1)[1008r,1040B:0)[1040B,1072r:5) 0@1008r 1@832r 2@736r 3@640r 4@528r 5@1040B-phi weight:0.000000e+00 +%63 [544r,592B:4)[656r,704B:3)[752r,800B:2)[848r,896B:1)[1024r,1040B:0)[1040B,1056r:5) 0@1024r 1@848r 2@752r 3@656r 4@544r 5@1040B-phi weight:0.000000e+00 +%64 [1104r,1152B:4)[1200r,1248B:3)[1280r,1328B:2)[1360r,1408B:1)[1440r,1456B:0)[1456B,1472r:5) 0@1440r 1@1360r 2@1280r 3@1200r 4@1104r 5@1456B-phi weight:0.000000e+00 +%65 [240r,304B:2)[432r,496B:1)[1616r,1680B:0)[1680B,1728r:3) 0@1616r 1@432r 2@240r 3@1680B-phi weight:0.000000e+00 +%66 [256r,304B:2)[448r,496B:1)[1632r,1680B:0)[1680B,1712r:3) 0@1632r 1@448r 2@256r 3@1680B-phi weight:0.000000e+00 +%67 [272r,304B:2)[464r,496B:1)[1648r,1680B:0)[1680B,1696r:3) 0@1648r 1@464r 2@272r 3@1680B-phi weight:0.000000e+00 +%68 [1808r,1840B:1)[1904r,1920B:0)[1920B,1936r:2) 0@1904r 1@1808r 2@1920B-phi weight:0.000000e+00 +RegMasks: +BB_71: 0B 288B +BB_72: 304B 480B +BB_73: 496B 576B +BB_73: 592B 688B +BB_73: 704B 784B +BB_73: 800B 880B +BB_74: 896B 1024B +BB_75: 1040B 1136B +BB_75: 1152B 1232B +BB_75: 1248B 1312B +BB_75: 1328B 1392B +BB_76: 1408B 1440B +BB_77: 1456B 1664B +BB_78: 1680B 1824B +BB_79: 1840B 1904B +BB_80: 1920B 1968B +AlignmentIdentityBySampling +CH [0B,16r:0) 0@0B-phi +CL [0B,16r:0) 0@0B-phi +DH [0B,32r:0) 0@0B-phi +DIL [0B,64r:0) 0@0B-phi +DIH [0B,64r:0) 0@0B-phi +DL [0B,32r:0) 0@0B-phi +HCX [0B,16r:0) 0@0B-phi +HDI [0B,64r:0) 0@0B-phi +HDX [0B,32r:0) 0@0B-phi +SIL [0B,48r:0) 0@0B-phi +SIH [0B,48r:0) 0@0B-phi +HSI [0B,48r:0) 0@0B-phi +%1 [416r,2624r:0) 0@416r weight:0.000000e+00 +%2 [400r,2640r:0) 0@400r weight:0.000000e+00 +%8 [1056r,2176r:0) 0@1056r weight:0.000000e+00 +%9 [1040r,1600r:0) 0@1040r weight:0.000000e+00 +%10 [1024r,2096r:0) 0@1024r weight:0.000000e+00 +%11 [1008r,1584r:0) 0@1008r weight:0.000000e+00 +%12 [992r,1664r:0) 0@992r weight:0.000000e+00 +%16 [1744r,2288r:0) 0@1744r weight:0.000000e+00 +%17 [1728r,2304r:0) 0@1728r weight:0.000000e+00 +%19 [2144r,2320r:0) 0@2144r weight:0.000000e+00 +%22 [2400r,2528r:0) 0@2400r weight:0.000000e+00 +%23 [2384r,2432r:0) 0@2384r weight:0.000000e+00 +%24 [2368r,2432r:0) 0@2368r weight:0.000000e+00 +%27 [2608r,2624r:0) 0@2608r weight:0.000000e+00 +%30 [2752r,2784r:0) 0@2752r weight:0.000000e+00 +%32 [2832r,2848r:0) 0@2832r weight:0.000000e+00 +%33 [64r,80r:0) 0@64r weight:0.000000e+00 +%34 [80r,2736B:0) 0@80r weight:0.000000e+00 +%35 [48r,96r:0) 0@48r weight:0.000000e+00 +%36 [96r,96d:0) 0@96r weight:0.000000e+00 +%37 [32r,112r:0) 0@32r weight:0.000000e+00 +%38 [112r,304r:0) 0@112r weight:0.000000e+00 +%39 [16r,128r:0) 0@16r weight:0.000000e+00 +%40 [128r,2768r:0) 0@128r weight:0.000000e+00 +%41 [144r,176r:0) 0@144r weight:0.000000e+00 +%42 [224r,256r:0) 0@224r weight:0.000000e+00 +%43 [320r,352r:0) 0@320r weight:0.000000e+00 +%44 [336r,368r:0) 0@336r weight:0.000000e+00 +%45 [304r,2736B:0) 0@304r weight:0.000000e+00 +%47 [512r,688r:0) 0@512r weight:0.000000e+00 +%49 [496r,512r:0) 0@496r weight:0.000000e+00 +%50 [480r,496r:0) 0@480r weight:0.000000e+00 +%52 [624r,720r:0) 0@624r weight:0.000000e+00 +%54 [608r,624r:0) 0@608r weight:0.000000e+00 +%55 [592r,608r:0) 0@592r weight:0.000000e+00 +%56 [768r,944r:0) 0@768r weight:0.000000e+00 +%57 [784r,800r:0) 0@784r weight:0.000000e+00 +%58 [800r,832r:0) 0@800r weight:0.000000e+00 +%59 [752r,848r:0) 0@752r weight:0.000000e+00 +%61 [736r,2352B:0) 0@736r weight:0.000000e+00 +%62 [720r,736r:0) 0@720r weight:0.000000e+00 +%64 [704r,2352B:0) 0@704r weight:0.000000e+00 +%65 [688r,704r:0) 0@688r weight:0.000000e+00 +%66 [1072r,2016r:0) 0@1072r weight:0.000000e+00 +%67 [1184r,1184d:0) 0@1184r weight:0.000000e+00 +%68 [1280r,1296r:0) 0@1280r weight:0.000000e+00 +%69 [1296r,1296d:0) 0@1296r weight:0.000000e+00 +%70 [1392r,1392d:0) 0@1392r weight:0.000000e+00 +%71 [1488r,1488d:0) 0@1488r weight:0.000000e+00 +%73 [1664r,1680r:0) 0@1664r weight:0.000000e+00 +%75 [1632r,1648r:0) 0@1632r weight:0.000000e+00 +%76 [1648r,1664r:0) 0@1648r weight:0.000000e+00 +%77 [1616r,1632r:0) 0@1616r weight:0.000000e+00 +%78 [1584r,1696r:0) 0@1584r weight:0.000000e+00 +%79 [1760r,1760d:0) 0@1760r weight:0.000000e+00 +%80 [1840r,1856r:0) 0@1840r weight:0.000000e+00 +%81 [1856r,1856d:0) 0@1856r weight:0.000000e+00 +%82 [1936r,1936d:0) 0@1936r weight:0.000000e+00 +%83 [2016r,2016d:0) 0@2016r weight:0.000000e+00 +%84 [2096r,2112r:0) 0@2096r weight:0.000000e+00 +%85 [2176r,2224r:0) 0@2176r weight:0.000000e+00 +%86 [2160r,2208r:0) 0@2160r weight:0.000000e+00 +%87 [2448r,2480r:0) 0@2448r weight:0.000000e+00 +%88 [2432r,2544r:0) 0@2432r weight:0.000000e+00 +%91 [2560r,2576r:0) 0@2560r weight:0.000000e+00 +%92 [2544r,2560r:0) 0@2544r weight:0.000000e+00 +%93 [2528r,2560r:0) 0@2528r weight:0.000000e+00 +%94 [2640r,2688r:0) 0@2640r weight:0.000000e+00 +%95 [2624r,2704r:0) 0@2624r weight:0.000000e+00 +%97 [2784r,2800r:0) 0@2784r weight:0.000000e+00 +%98 [2768r,2784r:0) 0@2768r weight:0.000000e+00 +%99 [352r,384B:1)[384B,416r:2)[2672r,2736B:0) 0@2672r 1@352r 2@384B-phi weight:0.000000e+00 +%100 [368r,384B:1)[384B,400r:2)[2688r,2736B:0) 0@2688r 1@368r 2@384B-phi weight:0.000000e+00 +%101 [832r,976B:1)[976B,1056r:2)[2208r,2352B:0) 0@2208r 1@832r 2@976B-phi weight:0.000000e+00 +%102 [848r,976B:1)[976B,1040r:2)[2224r,2352B:0) 0@2224r 1@848r 2@976B-phi weight:0.000000e+00 +%103 [864r,976B:1)[976B,1024r:2)[2240r,2352B:0) 0@2240r 1@864r 2@976B-phi weight:0.000000e+00 +%104 [880r,976B:1)[976B,1008r:2)[2256r,2352B:0) 0@2256r 1@880r 2@976B-phi weight:0.000000e+00 +%105 [896r,976B:1)[976B,992r:2)[2272r,2352B:0) 0@2272r 1@896r 2@976B-phi weight:0.000000e+00 +%106 [1200r,1264B:4)[1312r,1376B:3)[1408r,1472B:2)[1504r,1568B:1)[1680r,1712B:0)[1712B,1744r:5) 0@1680r 1@1504r 2@1408r 3@1312r 4@1200r 5@1712B-phi weight:0.000000e+00 +%107 [1216r,1264B:4)[1328r,1376B:3)[1424r,1472B:2)[1520r,1568B:1)[1696r,1712B:0)[1712B,1728r:5) 0@1696r 1@1520r 2@1424r 3@1328r 4@1216r 5@1712B-phi weight:0.000000e+00 +%108 [1776r,1824B:4)[1872r,1920B:3)[1952r,2000B:2)[2032r,2080B:1)[2112r,2128B:0)[2128B,2144r:5) 0@2112r 1@2032r 2@1952r 3@1872r 4@1776r 5@2128B-phi weight:0.000000e+00 +%109 [912r,976B:2)[1104r,1168B:1)[2288r,2352B:0)[2352B,2400r:3) 0@2288r 1@1104r 2@912r 3@2352B-phi weight:0.000000e+00 +%110 [928r,976B:2)[1120r,1168B:1)[2304r,2352B:0)[2352B,2384r:3) 0@2304r 1@1120r 2@928r 3@2352B-phi weight:0.000000e+00 +%111 [944r,976B:2)[1136r,1168B:1)[2320r,2352B:0)[2352B,2368r:3) 0@2320r 1@1136r 2@944r 3@2352B-phi weight:0.000000e+00 +%112 [2480r,2512B:1)[2576r,2592B:0)[2592B,2608r:2) 0@2576r 1@2480r 2@2592B-phi weight:0.000000e+00 +%113 [256r,288B:1)[2704r,2736B:0)[2736B,2752r:2) 0@2704r 1@256r 2@2736B-phi weight:0.000000e+00 +%114 [176r,208B:1)[2800r,2816B:0)[2816B,2832r:2) 0@2800r 1@176r 2@2816B-phi weight:0.000000e+00 +RegMasks: 448r 560r +BB_81: 0B 192B +BB_82: 208B 272B +BB_83: 288B 368B +BB_84: 384B 512B +BB_85: 528B 656B +BB_86: 672B 960B +BB_87: 976B 1152B +BB_88: 1168B 1248B +BB_88: 1264B 1360B +BB_88: 1376B 1456B +BB_88: 1472B 1552B +BB_89: 1568B 1696B +BB_90: 1712B 1808B +BB_90: 1824B 1904B +BB_90: 1920B 1984B +BB_90: 2000B 2064B +BB_91: 2080B 2112B +BB_92: 2128B 2336B +BB_93: 2352B 2496B +BB_94: 2512B 2576B +BB_95: 2592B 2720B +BB_96: 2736B 2800B +BB_97: 2816B 2864B +MajorityRuleConsensus +DH [0B,16r:0)[240r,256r:2)[1552r,1568r:1) 0@0B-phi 1@1552r 2@240r +DIL [0B,48r:0)[208r,256r:2)[1520r,1568r:1) 0@0B-phi 1@1520r 2@208r +DIH [0B,48r:0)[208r,256r:2)[1520r,1568r:1) 0@0B-phi 1@1520r 2@208r +DL [0B,16r:0)[240r,256r:2)[1552r,1568r:1) 0@0B-phi 1@1552r 2@240r +HDI [0B,48r:0)[208r,256r:2)[1520r,1568r:1) 0@0B-phi 1@1520r 2@208r +HDX [0B,16r:0)[240r,256r:2)[1552r,1568r:1) 0@0B-phi 1@1552r 2@240r +SIL [0B,32r:0)[224r,256r:2)[1536r,1568r:1) 0@0B-phi 1@1536r 2@224r +SIH [0B,32r:0)[224r,256r:2)[1536r,1568r:1) 0@0B-phi 1@1536r 2@224r +HSI [0B,32r:0)[224r,256r:2)[1536r,1568r:1) 0@0B-phi 1@1536r 2@224r +%33 [1456r,7168r:0) 0@1456r weight:0.000000e+00 +%34 [1440r,7088r:0) 0@1440r weight:0.000000e+00 +%36 [1840r,2240r:0) 0@1840r weight:0.000000e+00 +%40 [2368r,2384r:0) 0@2368r weight:0.000000e+00 +%42 [7152r,7232r:0) 0@7152r weight:0.000000e+00 +%44 [7280r,7296r:0) 0@7280r weight:0.000000e+00 +%45 [48r,64r:0) 0@48r weight:0.000000e+00 +%46 [64r,7264B:0) 0@64r weight:0.000000e+00 +%47 [32r,80r:0) 0@32r weight:0.000000e+00 +%48 [80r,496r:0) 0@80r weight:0.000000e+00 +%49 [16r,96r:0) 0@16r weight:0.000000e+00 +%50 [96r,464r:0) 0@96r weight:0.000000e+00 +%51 [304r,336r:0) 0@304r weight:0.000000e+00 +%52 [160r,208r:0) 0@160r weight:0.000000e+00 +%53 [176r,224r:0) 0@176r weight:0.000000e+00 +%55 [288r,7328r:0) 0@288r weight:0.000000e+00 +%57 [144r,240r:0) 0@144r weight:0.000000e+00 +%58 [128r,144r:0) 0@128r weight:0.000000e+00 +%59 [112r,7264B:0) 0@112r weight:0.000000e+00 +%60 [1344r,1360r:0) 0@1344r weight:0.000000e+00 +%61 [1360r,1392r:0) 0@1360r weight:0.000000e+00 +%62 [1376r,1408r:0) 0@1376r weight:0.000000e+00 +%63 [1312r,1328r:0) 0@1312r weight:0.000000e+00 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[1792r,1808r:0) 0@1792r weight:0.000000e+00 +%128 [1760r,2304B:0) 0@1760r weight:0.000000e+00 +%129 [1744r,1760r:0) 0@1744r weight:0.000000e+00 +%132 [1904r,1920r:0) 0@1904r weight:0.000000e+00 +%133 [1888r,1904r:0) 0@1888r weight:0.000000e+00 +%135 [1872r,2048r:0) 0@1872r weight:0.000000e+00 +%137 [1856r,1872r:0) 0@1856r weight:0.000000e+00 +%141 [2112r,2128r:0) 0@2112r weight:0.000000e+00 +%142 [2096r,2112r:0) 0@2096r weight:0.000000e+00 +%144 [2080r,2128r:0) 0@2080r weight:0.000000e+00 +%146 [2064r,2080r:0) 0@2064r weight:0.000000e+00 +%148 [2048r,2064r:0) 0@2048r weight:0.000000e+00 +%150 [2032r,2048r:0) 0@2032r weight:0.000000e+00 +%151 [2016r,2032r:0) 0@2016r weight:0.000000e+00 +%154 [2192r,2208r:0) 0@2192r weight:0.000000e+00 +%155 [2176r,2192r:0) 0@2176r weight:0.000000e+00 +%156 [2240r,2272r:0) 0@2240r weight:0.000000e+00 +%157 [2320r,2336r:0) 0@2320r weight:0.000000e+00 +%158 [2416r,2432r:0) 0@2416r weight:0.000000e+00 +%161 [2400r,2432r:0) 0@2400r weight:0.000000e+00 +%162 [2384r,2400r:0) 0@2384r weight:0.000000e+00 +%165 [7088r,7104r:0) 0@7088r weight:0.000000e+00 +%166 [7072r,7120r:0) 0@7072r weight:0.000000e+00 +%169 [6944r,6976r:0) 0@6944r weight:0.000000e+00 +%171 [7056r,7104r:0) 0@7056r weight:0.000000e+00 +%174 [6816r,6848r:0) 0@6816r weight:0.000000e+00 +%176 [6928r,7024r:0) 0@6928r weight:0.000000e+00 +%179 [6688r,6720r:0) 0@6688r weight:0.000000e+00 +%181 [6800r,6896r:0) 0@6800r weight:0.000000e+00 +%184 [6560r,6592r:0) 0@6560r weight:0.000000e+00 +%186 [6672r,6768r:0) 0@6672r weight:0.000000e+00 +%189 [6432r,6464r:0) 0@6432r weight:0.000000e+00 +%191 [6544r,6640r:0) 0@6544r weight:0.000000e+00 +%194 [6304r,6336r:0) 0@6304r weight:0.000000e+00 +%196 [6416r,6512r:0) 0@6416r weight:0.000000e+00 +%199 [6176r,6208r:0) 0@6176r weight:0.000000e+00 +%201 [6288r,6384r:0) 0@6288r weight:0.000000e+00 +%204 [6048r,6080r:0) 0@6048r weight:0.000000e+00 +%206 [6160r,6256r:0) 0@6160r weight:0.000000e+00 +%209 [5920r,5952r:0) 0@5920r weight:0.000000e+00 +%211 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